2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 static irqreturn_t pcie_isr(int irq, void *dev_id);
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
52 /* This is the interrupt polling timeout function. */
53 static void int_poll_timeout(unsigned long data)
55 struct controller *ctrl = (struct controller *)data;
57 /* Poll for interrupt events. regs == NULL => polling */
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
64 start_int_poll_timer(ctrl, pciehp_poll_time);
67 /* This function starts the interrupt polling timer. */
68 static void start_int_poll_timer(struct controller *ctrl, int sec)
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
80 static inline int pciehp_request_irq(struct controller *ctrl)
82 int retval, irq = ctrl->pcie->irq;
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller *ctrl)
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
104 free_irq(ctrl->pcie->irq, ctrl);
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
109 struct pci_dev *pdev = ctrl_dev(ctrl);
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status == (u16) ~0) {
115 ctrl_info(ctrl, "%s: no response from device\n",
120 if (slot_status & PCI_EXP_SLTSTA_CC) {
121 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
130 return 0; /* timeout */
133 static void pcie_wait_cmd(struct controller *ctrl)
135 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
136 unsigned long duration = msecs_to_jiffies(msecs);
137 unsigned long cmd_timeout = ctrl->cmd_started + duration;
138 unsigned long now, timeout;
142 * If the controller does not generate notifications for command
143 * completions, we never need to wait between writes.
145 if (NO_CMD_CMPL(ctrl))
152 * Even if the command has already timed out, we want to call
153 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
156 if (time_before_eq(cmd_timeout, now))
159 timeout = cmd_timeout - now;
161 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
162 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
163 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
165 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
168 * Controllers with errata like Intel CF118 don't generate
169 * completion notifications unless the power/indicator/interlock
170 * control bits are changed. On such controllers, we'll emit this
171 * timeout message when we wait for completion of commands that
172 * don't change those bits, e.g., commands that merely enable
176 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
178 jiffies_to_msecs(jiffies - ctrl->cmd_started));
181 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
184 struct pci_dev *pdev = ctrl_dev(ctrl);
187 mutex_lock(&ctrl->ctrl_lock);
190 * Always wait for any previous command that might still be in progress
194 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
195 if (slot_ctrl == (u16) ~0) {
196 ctrl_info(ctrl, "%s: no response from device\n", __func__);
201 slot_ctrl |= (cmd & mask);
204 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
205 ctrl->cmd_started = jiffies;
206 ctrl->slot_ctrl = slot_ctrl;
209 * Optionally wait for the hardware to be ready for a new command,
210 * indicating completion of the above issued command.
216 mutex_unlock(&ctrl->ctrl_lock);
220 * pcie_write_cmd - Issue controller command
221 * @ctrl: controller to which the command is issued
222 * @cmd: command value written to slot control register
223 * @mask: bitmask of slot control register to be modified
225 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
227 pcie_do_write_cmd(ctrl, cmd, mask, true);
230 /* Same as above without waiting for the hardware to latch */
231 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
233 pcie_do_write_cmd(ctrl, cmd, mask, false);
236 bool pciehp_check_link_active(struct controller *ctrl)
238 struct pci_dev *pdev = ctrl_dev(ctrl);
242 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
243 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
246 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
251 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
255 if (pciehp_check_link_active(ctrl) == active)
257 while (timeout > 0) {
260 if (pciehp_check_link_active(ctrl) == active)
263 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
264 active ? "set" : "cleared");
267 static void pcie_wait_link_active(struct controller *ctrl)
269 __pcie_wait_link_active(ctrl, true);
272 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
276 int delay = 1000, step = 20;
280 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
290 if (count > 1 && pciehp_debug)
291 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
292 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
293 PCI_FUNC(devfn), count, step, l);
298 int pciehp_check_link_status(struct controller *ctrl)
300 struct pci_dev *pdev = ctrl_dev(ctrl);
305 * Data Link Layer Link Active Reporting must be capable for
306 * hot-plug capable downstream port. But old controller might
307 * not implement it. In this case, we wait for 1000 ms.
309 if (ctrl->link_active_reporting)
310 pcie_wait_link_active(ctrl);
314 /* wait 100ms before read pci conf, and try in 1s */
316 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
319 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
320 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
321 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
322 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
323 ctrl_err(ctrl, "link training error: status %#06x\n",
328 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
336 static int __pciehp_link_set(struct controller *ctrl, bool enable)
338 struct pci_dev *pdev = ctrl_dev(ctrl);
341 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
344 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
346 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
348 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
349 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
353 static int pciehp_link_enable(struct controller *ctrl)
355 return __pciehp_link_set(ctrl, true);
358 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
361 struct slot *slot = hotplug_slot->private;
362 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
365 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
366 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
370 void pciehp_get_attention_status(struct slot *slot, u8 *status)
372 struct controller *ctrl = slot->ctrl;
373 struct pci_dev *pdev = ctrl_dev(ctrl);
376 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
377 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
378 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
380 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
381 case PCI_EXP_SLTCTL_ATTN_IND_ON:
382 *status = 1; /* On */
384 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
385 *status = 2; /* Blink */
387 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
388 *status = 0; /* Off */
396 void pciehp_get_power_status(struct slot *slot, u8 *status)
398 struct controller *ctrl = slot->ctrl;
399 struct pci_dev *pdev = ctrl_dev(ctrl);
402 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
403 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
404 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
406 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
407 case PCI_EXP_SLTCTL_PWR_ON:
408 *status = 1; /* On */
410 case PCI_EXP_SLTCTL_PWR_OFF:
411 *status = 0; /* Off */
419 void pciehp_get_latch_status(struct slot *slot, u8 *status)
421 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
424 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
425 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
428 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
430 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
433 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
434 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
437 int pciehp_query_power_fault(struct slot *slot)
439 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
442 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
443 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
446 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
449 struct slot *slot = hotplug_slot->private;
450 struct controller *ctrl = slot->ctrl;
452 pcie_write_cmd_nowait(ctrl, status << 6,
453 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
457 void pciehp_set_attention_status(struct slot *slot, u8 value)
459 struct controller *ctrl = slot->ctrl;
466 case 0: /* turn off */
467 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
469 case 1: /* turn on */
470 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
472 case 2: /* turn blink */
473 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
478 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
479 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
480 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
483 void pciehp_green_led_on(struct slot *slot)
485 struct controller *ctrl = slot->ctrl;
490 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
492 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
493 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
494 PCI_EXP_SLTCTL_PWR_IND_ON);
497 void pciehp_green_led_off(struct slot *slot)
499 struct controller *ctrl = slot->ctrl;
504 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
506 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
507 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
508 PCI_EXP_SLTCTL_PWR_IND_OFF);
511 void pciehp_green_led_blink(struct slot *slot)
513 struct controller *ctrl = slot->ctrl;
518 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
520 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
521 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
522 PCI_EXP_SLTCTL_PWR_IND_BLINK);
525 int pciehp_power_on_slot(struct slot *slot)
527 struct controller *ctrl = slot->ctrl;
528 struct pci_dev *pdev = ctrl_dev(ctrl);
532 /* Clear sticky power-fault bit from previous power failures */
533 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
534 if (slot_status & PCI_EXP_SLTSTA_PFD)
535 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
537 ctrl->power_fault_detected = 0;
539 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
540 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
541 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
542 PCI_EXP_SLTCTL_PWR_ON);
544 retval = pciehp_link_enable(ctrl);
546 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
551 void pciehp_power_off_slot(struct slot *slot)
553 struct controller *ctrl = slot->ctrl;
555 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
556 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
557 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
558 PCI_EXP_SLTCTL_PWR_OFF);
561 static irqreturn_t pciehp_isr(int irq, void *dev_id)
563 struct controller *ctrl = (struct controller *)dev_id;
564 struct pci_dev *pdev = ctrl_dev(ctrl);
565 struct slot *slot = ctrl->slot;
570 /* Interrupts cannot originate from a controller that's asleep */
571 if (pdev->current_state == PCI_D3cold)
574 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
575 if (status == (u16) ~0) {
576 ctrl_info(ctrl, "%s: no response from device\n", __func__);
581 * Slot Status contains plain status bits as well as event
582 * notification bits; right now we only want the event bits.
584 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
585 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
586 PCI_EXP_SLTSTA_DLLSC);
589 * If we've already reported a power fault, don't report it again
590 * until we've done something to handle it.
592 if (ctrl->power_fault_detected)
593 events &= ~PCI_EXP_SLTSTA_PFD;
598 /* Capture link status before clearing interrupts */
599 if (events & PCI_EXP_SLTSTA_DLLSC)
600 link = pciehp_check_link_active(ctrl);
602 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
603 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
605 /* Check Command Complete Interrupt Pending */
606 if (events & PCI_EXP_SLTSTA_CC) {
609 wake_up(&ctrl->queue);
612 if (pdev->ignore_hotplug) {
613 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
617 /* Check Attention Button Pressed */
618 if (events & PCI_EXP_SLTSTA_ABP) {
619 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
621 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
625 * Check Link Status Changed at higher precedence than Presence
626 * Detect Changed. The PDS value may be set to "card present" from
627 * out-of-band detection, which may be in conflict with a Link Down
628 * and cause the wrong event to queue.
630 if (events & PCI_EXP_SLTSTA_DLLSC) {
631 ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot),
632 link ? "Up" : "Down");
633 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
635 } else if (events & PCI_EXP_SLTSTA_PDC) {
636 present = !!(status & PCI_EXP_SLTSTA_PDS);
637 ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot),
638 present ? "" : "not ");
639 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
643 /* Check Power Fault Detected */
644 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
645 ctrl->power_fault_detected = 1;
646 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
647 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
653 static irqreturn_t pcie_isr(int irq, void *dev_id)
655 irqreturn_t rc, handled = IRQ_NONE;
658 * To guarantee that all interrupt events are serviced, we need to
659 * re-inspect Slot Status register after clearing what is presumed
660 * to be the last pending interrupt.
663 rc = pciehp_isr(irq, dev_id);
664 if (rc == IRQ_HANDLED)
665 handled = IRQ_HANDLED;
666 } while (rc == IRQ_HANDLED);
668 /* Return IRQ_HANDLED if we handled one or more events */
672 static void pcie_enable_notification(struct controller *ctrl)
677 * TBD: Power fault detected software notification support.
679 * Power fault detected software notification is not enabled
680 * now, because it caused power fault detected interrupt storm
681 * on some machines. On those machines, power fault detected
682 * bit in the slot status register was set again immediately
683 * when it is cleared in the interrupt service routine, and
684 * next power fault detected interrupt was notified again.
688 * Always enable link events: thus link-up and link-down shall
689 * always be treated as hotplug and unplug respectively. Enable
690 * presence detect only if Attention Button is not present.
692 cmd = PCI_EXP_SLTCTL_DLLSCE;
693 if (ATTN_BUTTN(ctrl))
694 cmd |= PCI_EXP_SLTCTL_ABPE;
696 cmd |= PCI_EXP_SLTCTL_PDCE;
697 if (!pciehp_poll_mode)
698 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
700 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
701 PCI_EXP_SLTCTL_PFDE |
702 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
703 PCI_EXP_SLTCTL_DLLSCE);
705 pcie_write_cmd_nowait(ctrl, cmd, mask);
706 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
707 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
710 void pcie_reenable_notification(struct controller *ctrl)
713 * Clear both Presence and Data Link Layer Changed to make sure
714 * those events still fire after we have re-enabled them.
716 pcie_capability_write_word(ctrl->pcie->port, PCI_EXP_SLTSTA,
717 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
718 pcie_enable_notification(ctrl);
721 static void pcie_disable_notification(struct controller *ctrl)
725 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
726 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
727 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
728 PCI_EXP_SLTCTL_DLLSCE);
729 pcie_write_cmd(ctrl, 0, mask);
730 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
731 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
735 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
736 * bus reset of the bridge, but at the same time we want to ensure that it is
737 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
738 * disable link state notification and presence detection change notification
739 * momentarily, if we see that they could interfere. Also, clear any spurious
742 int pciehp_reset_slot(struct slot *slot, int probe)
744 struct controller *ctrl = slot->ctrl;
745 struct pci_dev *pdev = ctrl_dev(ctrl);
746 u16 stat_mask = 0, ctrl_mask = 0;
751 if (!ATTN_BUTTN(ctrl)) {
752 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
753 stat_mask |= PCI_EXP_SLTSTA_PDC;
755 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
756 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
758 pcie_write_cmd(ctrl, 0, ctrl_mask);
759 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
760 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
761 if (pciehp_poll_mode)
762 del_timer_sync(&ctrl->poll_timer);
764 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
766 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
767 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
768 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
769 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
770 if (pciehp_poll_mode)
771 int_poll_timeout(ctrl->poll_timer.data);
776 int pcie_init_notification(struct controller *ctrl)
778 if (pciehp_request_irq(ctrl))
780 pcie_enable_notification(ctrl);
781 ctrl->notification_enabled = 1;
785 void pcie_shutdown_notification(struct controller *ctrl)
787 if (ctrl->notification_enabled) {
788 pcie_disable_notification(ctrl);
789 pciehp_free_irq(ctrl);
790 ctrl->notification_enabled = 0;
794 static int pcie_init_slot(struct controller *ctrl)
798 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
802 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
807 mutex_init(&slot->lock);
808 mutex_init(&slot->hotplug_lock);
809 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
817 static void pcie_cleanup_slot(struct controller *ctrl)
819 struct slot *slot = ctrl->slot;
821 destroy_workqueue(slot->wq);
825 static inline void dbg_ctrl(struct controller *ctrl)
827 struct pci_dev *pdev = ctrl->pcie->port;
833 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
834 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
835 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
836 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
837 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
840 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
842 struct controller *pcie_init(struct pcie_device *dev)
844 struct controller *ctrl;
845 u32 slot_cap, link_cap;
846 struct pci_dev *pdev = dev->port;
848 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
850 dev_err(&dev->device, "%s: Out of memory\n", __func__);
854 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
856 if (pdev->hotplug_user_indicators)
857 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
860 * We assume no Thunderbolt controllers support Command Complete events,
861 * but some controllers falsely claim they do.
863 if (pdev->is_thunderbolt)
864 slot_cap |= PCI_EXP_SLTCAP_NCCS;
866 ctrl->slot_cap = slot_cap;
867 mutex_init(&ctrl->ctrl_lock);
868 init_waitqueue_head(&ctrl->queue);
871 /* Check if Data Link Layer Link Active Reporting is implemented */
872 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
873 if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
874 ctrl->link_active_reporting = 1;
876 /* Clear all remaining event bits in Slot Status register */
877 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
878 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
879 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
880 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
882 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
883 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
884 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
885 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
886 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
887 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
888 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
889 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
890 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
891 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
892 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
893 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
895 if (pcie_init_slot(ctrl))
906 void pciehp_release_ctrl(struct controller *ctrl)
908 pcie_cleanup_slot(ctrl);