1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI Express PCI Hot Plug Driver
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
10 * All rights reserved.
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
15 #define dev_fmt(fmt) "pciehp: " fmt
17 #include <linux/bitfield.h>
18 #include <linux/dmi.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/jiffies.h>
22 #include <linux/kthread.h>
23 #include <linux/pci.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
26 #include <linux/slab.h>
31 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
33 * Match all Dell systems, as some Dell systems have inband
34 * presence disabled on NVMe slots (but don't support the bit to
35 * report it). Setting inband presence disabled should have no
36 * negative effect, except on broken hotplug slots that never
37 * assert presence detect--and those will still work, they will
38 * just have a bit of extra delay before being probed.
41 .ident = "Dell System",
43 DMI_MATCH(DMI_OEM_STRING, "Dell System"),
49 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
51 return ctrl->pcie->port;
54 static irqreturn_t pciehp_isr(int irq, void *dev_id);
55 static irqreturn_t pciehp_ist(int irq, void *dev_id);
56 static int pciehp_poll(void *data);
58 static inline int pciehp_request_irq(struct controller *ctrl)
60 int retval, irq = ctrl->pcie->irq;
62 if (pciehp_poll_mode) {
63 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
66 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
69 /* Installs the interrupt handler */
70 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
71 IRQF_SHARED, "pciehp", ctrl);
73 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
78 static inline void pciehp_free_irq(struct controller *ctrl)
81 kthread_stop(ctrl->poll_thread);
83 free_irq(ctrl->pcie->irq, ctrl);
86 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
88 struct pci_dev *pdev = ctrl_dev(ctrl);
92 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
93 if (PCI_POSSIBLE_ERROR(slot_status)) {
94 ctrl_info(ctrl, "%s: no response from device\n",
99 if (slot_status & PCI_EXP_SLTSTA_CC) {
100 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
108 } while (timeout >= 0);
109 return 0; /* timeout */
112 static void pcie_wait_cmd(struct controller *ctrl)
114 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
115 unsigned long duration = msecs_to_jiffies(msecs);
116 unsigned long cmd_timeout = ctrl->cmd_started + duration;
117 unsigned long now, timeout;
121 * If the controller does not generate notifications for command
122 * completions, we never need to wait between writes.
124 if (NO_CMD_CMPL(ctrl))
131 * Even if the command has already timed out, we want to call
132 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
135 if (time_before_eq(cmd_timeout, now))
138 timeout = cmd_timeout - now;
140 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
141 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
142 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
144 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
147 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
149 jiffies_to_msecs(jiffies - ctrl->cmd_started));
152 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
153 PCI_EXP_SLTCTL_PIC | \
154 PCI_EXP_SLTCTL_AIC | \
157 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
160 struct pci_dev *pdev = ctrl_dev(ctrl);
161 u16 slot_ctrl_orig, slot_ctrl;
163 mutex_lock(&ctrl->ctrl_lock);
166 * Always wait for any previous command that might still be in progress
170 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
171 if (PCI_POSSIBLE_ERROR(slot_ctrl)) {
172 ctrl_info(ctrl, "%s: no response from device\n", __func__);
176 slot_ctrl_orig = slot_ctrl;
178 slot_ctrl |= (cmd & mask);
181 ctrl->slot_ctrl = slot_ctrl;
182 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
183 ctrl->cmd_started = jiffies;
186 * Controllers with the Intel CF118 and similar errata advertise
187 * Command Completed support, but they only set Command Completed
188 * if we change the "Control" bits for power, power indicator,
189 * attention indicator, or interlock. If we only change the
190 * "Enable" bits, they never set the Command Completed bit.
192 if (pdev->broken_cmd_compl &&
193 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
197 * Optionally wait for the hardware to be ready for a new command,
198 * indicating completion of the above issued command.
204 mutex_unlock(&ctrl->ctrl_lock);
208 * pcie_write_cmd - Issue controller command
209 * @ctrl: controller to which the command is issued
210 * @cmd: command value written to slot control register
211 * @mask: bitmask of slot control register to be modified
213 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
215 pcie_do_write_cmd(ctrl, cmd, mask, true);
218 /* Same as above without waiting for the hardware to latch */
219 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
221 pcie_do_write_cmd(ctrl, cmd, mask, false);
225 * pciehp_check_link_active() - Is the link active
226 * @ctrl: PCIe hotplug controller
228 * Check whether the downstream link is currently active. Note it is
229 * possible that the card is removed immediately after this so the
230 * caller may need to take it into account.
232 * If the hotplug controller itself is not available anymore returns
235 int pciehp_check_link_active(struct controller *ctrl)
237 struct pci_dev *pdev = ctrl_dev(ctrl);
241 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
242 if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status))
245 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
246 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
251 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
255 int delay = 1000, step = 20;
259 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
270 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
271 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
272 PCI_FUNC(devfn), count, step, l);
277 static void pcie_wait_for_presence(struct pci_dev *pdev)
283 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
284 if (slot_status & PCI_EXP_SLTSTA_PDS)
288 } while (timeout > 0);
291 int pciehp_check_link_status(struct controller *ctrl)
293 struct pci_dev *pdev = ctrl_dev(ctrl);
297 if (!pcie_wait_for_link(pdev, true)) {
298 ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
302 if (ctrl->inband_presence_disabled)
303 pcie_wait_for_presence(pdev);
305 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
308 /* ignore link or presence changes up to this point */
310 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
311 &ctrl->pending_events);
313 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
314 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
315 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
316 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
317 ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
318 slot_name(ctrl), lnk_status);
322 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
325 ctrl_info(ctrl, "Slot(%s): No device found\n",
333 static int __pciehp_link_set(struct controller *ctrl, bool enable)
335 struct pci_dev *pdev = ctrl_dev(ctrl);
337 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
339 enable ? 0 : PCI_EXP_LNKCTL_LD);
344 static int pciehp_link_enable(struct controller *ctrl)
346 return __pciehp_link_set(ctrl, true);
349 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
352 struct controller *ctrl = to_ctrl(hotplug_slot);
353 struct pci_dev *pdev = ctrl_dev(ctrl);
356 pci_config_pm_runtime_get(pdev);
357 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
358 pci_config_pm_runtime_put(pdev);
359 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
363 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
365 struct controller *ctrl = to_ctrl(hotplug_slot);
366 struct pci_dev *pdev = ctrl_dev(ctrl);
369 pci_config_pm_runtime_get(pdev);
370 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
371 pci_config_pm_runtime_put(pdev);
372 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
373 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
375 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
376 case PCI_EXP_SLTCTL_ATTN_IND_ON:
377 *status = 1; /* On */
379 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
380 *status = 2; /* Blink */
382 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
383 *status = 0; /* Off */
393 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
395 struct pci_dev *pdev = ctrl_dev(ctrl);
398 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
399 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
400 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
402 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
403 case PCI_EXP_SLTCTL_PWR_ON:
404 *status = 1; /* On */
406 case PCI_EXP_SLTCTL_PWR_OFF:
407 *status = 0; /* Off */
415 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
417 struct pci_dev *pdev = ctrl_dev(ctrl);
420 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
421 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
425 * pciehp_card_present() - Is the card present
426 * @ctrl: PCIe hotplug controller
428 * Function checks whether the card is currently present in the slot and
429 * in that case returns true. Note it is possible that the card is
430 * removed immediately after the check so the caller may need to take
433 * It the hotplug controller itself is not available anymore returns
436 int pciehp_card_present(struct controller *ctrl)
438 struct pci_dev *pdev = ctrl_dev(ctrl);
442 ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
443 if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(slot_status))
446 return !!(slot_status & PCI_EXP_SLTSTA_PDS);
450 * pciehp_card_present_or_link_active() - whether given slot is occupied
451 * @ctrl: PCIe hotplug controller
453 * Unlike pciehp_card_present(), which determines presence solely from the
454 * Presence Detect State bit, this helper also returns true if the Link Active
455 * bit is set. This is a concession to broken hotplug ports which hardwire
456 * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
458 * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
459 * port is not present anymore returns %-ENODEV.
461 int pciehp_card_present_or_link_active(struct controller *ctrl)
465 ret = pciehp_card_present(ctrl);
469 return pciehp_check_link_active(ctrl);
472 int pciehp_query_power_fault(struct controller *ctrl)
474 struct pci_dev *pdev = ctrl_dev(ctrl);
477 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
478 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
481 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
484 struct controller *ctrl = to_ctrl(hotplug_slot);
485 struct pci_dev *pdev = ctrl_dev(ctrl);
487 pci_config_pm_runtime_get(pdev);
488 pcie_write_cmd_nowait(ctrl, FIELD_PREP(PCI_EXP_SLTCTL_AIC, status),
489 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
490 pci_config_pm_runtime_put(pdev);
495 * pciehp_set_indicators() - set attention indicator, power indicator, or both
496 * @ctrl: PCIe hotplug controller
498 * PCI_EXP_SLTCTL_PWR_IND_ON
499 * PCI_EXP_SLTCTL_PWR_IND_BLINK
500 * PCI_EXP_SLTCTL_PWR_IND_OFF
502 * PCI_EXP_SLTCTL_ATTN_IND_ON
503 * PCI_EXP_SLTCTL_ATTN_IND_BLINK
504 * PCI_EXP_SLTCTL_ATTN_IND_OFF
506 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
509 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
511 u16 cmd = 0, mask = 0;
513 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
514 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
515 mask |= PCI_EXP_SLTCTL_PIC;
518 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
519 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
520 mask |= PCI_EXP_SLTCTL_AIC;
524 pcie_write_cmd_nowait(ctrl, cmd, mask);
525 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
526 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
530 int pciehp_power_on_slot(struct controller *ctrl)
532 struct pci_dev *pdev = ctrl_dev(ctrl);
536 /* Clear power-fault bit from previous power failures */
537 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
538 if (slot_status & PCI_EXP_SLTSTA_PFD)
539 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
541 ctrl->power_fault_detected = 0;
543 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
544 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
545 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
546 PCI_EXP_SLTCTL_PWR_ON);
548 retval = pciehp_link_enable(ctrl);
550 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
555 void pciehp_power_off_slot(struct controller *ctrl)
557 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
558 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
559 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
560 PCI_EXP_SLTCTL_PWR_OFF);
563 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
564 struct pci_dev *pdev, int irq)
567 * Ignore link changes which occurred while waiting for DPC recovery.
568 * Could be several if DPC triggered multiple times consecutively.
570 synchronize_hardirq(irq);
571 atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
572 if (pciehp_poll_mode)
573 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
574 PCI_EXP_SLTSTA_DLLSC);
575 ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
579 * If the link is unexpectedly down after successful recovery,
580 * the corresponding link change may have been ignored above.
581 * Synthesize it to ensure that it is acted on.
583 down_read_nested(&ctrl->reset_lock, ctrl->depth);
584 if (!pciehp_check_link_active(ctrl))
585 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
586 up_read(&ctrl->reset_lock);
589 static irqreturn_t pciehp_isr(int irq, void *dev_id)
591 struct controller *ctrl = (struct controller *)dev_id;
592 struct pci_dev *pdev = ctrl_dev(ctrl);
593 struct device *parent = pdev->dev.parent;
594 u16 status, events = 0;
597 * Interrupts only occur in D3hot or shallower and only if enabled
598 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
600 if (pdev->current_state == PCI_D3cold ||
601 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
605 * Keep the port accessible by holding a runtime PM ref on its parent.
606 * Defer resume of the parent to the IRQ thread if it's suspended.
607 * Mask the interrupt until then.
610 pm_runtime_get_noresume(parent);
611 if (!pm_runtime_active(parent)) {
612 pm_runtime_put(parent);
613 disable_irq_nosync(irq);
614 atomic_or(RERUN_ISR, &ctrl->pending_events);
615 return IRQ_WAKE_THREAD;
620 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
621 if (PCI_POSSIBLE_ERROR(status)) {
622 ctrl_info(ctrl, "%s: no response from device\n", __func__);
624 pm_runtime_put(parent);
629 * Slot Status contains plain status bits as well as event
630 * notification bits; right now we only want the event bits.
632 status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
633 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
634 PCI_EXP_SLTSTA_DLLSC;
637 * If we've already reported a power fault, don't report it again
638 * until we've done something to handle it.
640 if (ctrl->power_fault_detected)
641 status &= ~PCI_EXP_SLTSTA_PFD;
642 else if (status & PCI_EXP_SLTSTA_PFD)
643 ctrl->power_fault_detected = true;
648 pm_runtime_put(parent);
653 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
656 * In MSI mode, all event bits must be zero before the port
657 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
658 * So re-read the Slot Status register in case a bit was set
659 * between read and write.
661 if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
665 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
667 pm_runtime_put(parent);
670 * Command Completed notifications are not deferred to the
671 * IRQ thread because it may be waiting for their arrival.
673 if (events & PCI_EXP_SLTSTA_CC) {
676 wake_up(&ctrl->queue);
678 if (events == PCI_EXP_SLTSTA_CC)
681 events &= ~PCI_EXP_SLTSTA_CC;
684 if (pdev->ignore_hotplug) {
685 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
689 /* Save pending events for consumption by IRQ thread. */
690 atomic_or(events, &ctrl->pending_events);
691 return IRQ_WAKE_THREAD;
694 static irqreturn_t pciehp_ist(int irq, void *dev_id)
696 struct controller *ctrl = (struct controller *)dev_id;
697 struct pci_dev *pdev = ctrl_dev(ctrl);
701 ctrl->ist_running = true;
702 pci_config_pm_runtime_get(pdev);
704 /* rerun pciehp_isr() if the port was inaccessible on interrupt */
705 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
706 ret = pciehp_isr(irq, dev_id);
708 if (ret != IRQ_WAKE_THREAD)
712 synchronize_hardirq(irq);
713 events = atomic_xchg(&ctrl->pending_events, 0);
719 /* Check Attention Button Pressed */
720 if (events & PCI_EXP_SLTSTA_ABP)
721 pciehp_handle_button_press(ctrl);
723 /* Check Power Fault Detected */
724 if (events & PCI_EXP_SLTSTA_PFD) {
725 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
726 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
727 PCI_EXP_SLTCTL_ATTN_IND_ON);
731 * Ignore Link Down/Up events caused by Downstream Port Containment
732 * if recovery from the error succeeded.
734 if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
735 ctrl->state == ON_STATE) {
736 events &= ~PCI_EXP_SLTSTA_DLLSC;
737 pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
741 * Disable requests have higher priority than Presence Detect Changed
742 * or Data Link Layer State Changed events.
744 down_read_nested(&ctrl->reset_lock, ctrl->depth);
745 if (events & DISABLE_SLOT)
746 pciehp_handle_disable_request(ctrl);
747 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
748 pciehp_handle_presence_or_link_change(ctrl, events);
749 up_read(&ctrl->reset_lock);
753 pci_config_pm_runtime_put(pdev);
754 ctrl->ist_running = false;
755 wake_up(&ctrl->requester);
759 static int pciehp_poll(void *data)
761 struct controller *ctrl = data;
763 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
765 while (!kthread_should_stop()) {
766 /* poll for interrupt events or user requests */
767 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
768 atomic_read(&ctrl->pending_events))
769 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
771 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
772 pciehp_poll_time = 2; /* clamp to sane value */
774 schedule_timeout_idle(pciehp_poll_time * HZ);
780 static void pcie_enable_notification(struct controller *ctrl)
785 * TBD: Power fault detected software notification support.
787 * Power fault detected software notification is not enabled
788 * now, because it caused power fault detected interrupt storm
789 * on some machines. On those machines, power fault detected
790 * bit in the slot status register was set again immediately
791 * when it is cleared in the interrupt service routine, and
792 * next power fault detected interrupt was notified again.
796 * Always enable link events: thus link-up and link-down shall
797 * always be treated as hotplug and unplug respectively. Enable
798 * presence detect only if Attention Button is not present.
800 cmd = PCI_EXP_SLTCTL_DLLSCE;
801 if (ATTN_BUTTN(ctrl))
802 cmd |= PCI_EXP_SLTCTL_ABPE;
804 cmd |= PCI_EXP_SLTCTL_PDCE;
805 if (!pciehp_poll_mode)
806 cmd |= PCI_EXP_SLTCTL_HPIE;
807 if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl))
808 cmd |= PCI_EXP_SLTCTL_CCIE;
810 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
811 PCI_EXP_SLTCTL_PFDE |
812 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
813 PCI_EXP_SLTCTL_DLLSCE);
815 pcie_write_cmd_nowait(ctrl, cmd, mask);
816 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
817 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
820 static void pcie_disable_notification(struct controller *ctrl)
824 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
825 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
826 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
827 PCI_EXP_SLTCTL_DLLSCE);
828 pcie_write_cmd(ctrl, 0, mask);
829 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
830 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
833 void pcie_clear_hotplug_events(struct controller *ctrl)
835 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
836 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
839 void pcie_enable_interrupt(struct controller *ctrl)
843 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
844 pcie_write_cmd(ctrl, mask, mask);
847 void pcie_disable_interrupt(struct controller *ctrl)
852 * Mask hot-plug interrupt to prevent it triggering immediately
853 * when the link goes inactive (we still get PME when any of the
854 * enabled events is detected). Same goes with Link Layer State
855 * changed event which generates PME immediately when the link goes
856 * inactive so mask it as well.
858 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
859 pcie_write_cmd(ctrl, 0, mask);
863 * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
864 * @dev: PCI Express port service device
866 * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset
867 * further up in the hierarchy to recover from an error. The reset was
868 * propagated down to this hotplug port. Ignore the resulting link flap.
869 * If the link failed to retrain successfully, synthesize the ignored event.
870 * Surprise removal during reset is detected through Presence Detect Changed.
872 int pciehp_slot_reset(struct pcie_device *dev)
874 struct controller *ctrl = get_service_data(dev);
876 if (ctrl->state != ON_STATE)
879 pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA,
880 PCI_EXP_SLTSTA_DLLSC);
882 if (!pciehp_check_link_active(ctrl))
883 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
889 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
890 * bus reset of the bridge, but at the same time we want to ensure that it is
891 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
892 * disable link state notification and presence detection change notification
893 * momentarily, if we see that they could interfere. Also, clear any spurious
896 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
898 struct controller *ctrl = to_ctrl(hotplug_slot);
899 struct pci_dev *pdev = ctrl_dev(ctrl);
900 u16 stat_mask = 0, ctrl_mask = 0;
906 down_write_nested(&ctrl->reset_lock, ctrl->depth);
908 if (!ATTN_BUTTN(ctrl)) {
909 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
910 stat_mask |= PCI_EXP_SLTSTA_PDC;
912 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
913 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
915 pcie_write_cmd(ctrl, 0, ctrl_mask);
916 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
917 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
919 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
921 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
922 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
923 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
924 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
926 up_write(&ctrl->reset_lock);
930 int pcie_init_notification(struct controller *ctrl)
932 if (pciehp_request_irq(ctrl))
934 pcie_enable_notification(ctrl);
935 ctrl->notification_enabled = 1;
939 void pcie_shutdown_notification(struct controller *ctrl)
941 if (ctrl->notification_enabled) {
942 pcie_disable_notification(ctrl);
943 pciehp_free_irq(ctrl);
944 ctrl->notification_enabled = 0;
948 static inline void dbg_ctrl(struct controller *ctrl)
950 struct pci_dev *pdev = ctrl->pcie->port;
953 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
954 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
955 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16);
956 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
957 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16);
960 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
962 static inline int pcie_hotplug_depth(struct pci_dev *dev)
964 struct pci_bus *bus = dev->bus;
967 while (bus->parent) {
969 if (bus->self && bus->self->is_hotplug_bridge)
976 struct controller *pcie_init(struct pcie_device *dev)
978 struct controller *ctrl;
979 u32 slot_cap, slot_cap2;
981 struct pci_dev *pdev = dev->port;
982 struct pci_bus *subordinate = pdev->subordinate;
984 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
989 ctrl->depth = pcie_hotplug_depth(dev->port);
990 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
992 if (pdev->hotplug_user_indicators)
993 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
996 * We assume no Thunderbolt controllers support Command Complete events,
997 * but some controllers falsely claim they do.
999 if (pdev->is_thunderbolt)
1000 slot_cap |= PCI_EXP_SLTCAP_NCCS;
1002 ctrl->slot_cap = slot_cap;
1003 mutex_init(&ctrl->ctrl_lock);
1004 mutex_init(&ctrl->state_lock);
1005 init_rwsem(&ctrl->reset_lock);
1006 init_waitqueue_head(&ctrl->requester);
1007 init_waitqueue_head(&ctrl->queue);
1008 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
1011 down_read(&pci_bus_sem);
1012 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
1013 up_read(&pci_bus_sem);
1015 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
1016 if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
1017 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
1018 PCI_EXP_SLTCTL_IBPD_DISABLE);
1019 ctrl->inband_presence_disabled = 1;
1022 if (dmi_first_match(inband_presence_disabled_dmi_table))
1023 ctrl->inband_presence_disabled = 1;
1025 /* Clear all remaining event bits in Slot Status register. */
1026 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1027 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1028 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1029 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1031 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1032 FIELD_GET(PCI_EXP_SLTCAP_PSN, slot_cap),
1033 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1034 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1035 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1036 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1037 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1038 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1039 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1040 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1041 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1042 FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1043 FLAG(pdev->link_active_reporting, true),
1044 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1047 * If empty slot's power status is on, turn power off. The IRQ isn't
1048 * requested yet, so avoid triggering a notification with this command.
1050 if (POWER_CTRL(ctrl)) {
1051 pciehp_get_power_status(ctrl, &poweron);
1052 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1053 pcie_disable_notification(ctrl);
1054 pciehp_power_off_slot(ctrl);
1061 void pciehp_release_ctrl(struct controller *ctrl)
1063 cancel_delayed_work_sync(&ctrl->button_work);
1067 static void quirk_cmd_compl(struct pci_dev *pdev)
1071 if (pci_is_pcie(pdev)) {
1072 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1073 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1074 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1075 pdev->broken_cmd_compl = 1;
1078 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1079 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1080 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x010e,
1081 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1082 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1083 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1084 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1085 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1086 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1087 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1089 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);