2 * PCIe host controller driver for NWL PCIe Bridge
3 * Based on pcie-xilinx.c, pci-tegra.c
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/msi.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24 #include <linux/of_irq.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/irqchip/chained_irq.h>
29 /* Bridge core config registers */
30 #define BRCFG_PCIE_RX0 0x00000000
31 #define BRCFG_INTERRUPT 0x00000010
32 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
34 /* Egress - Bridge translation registers */
35 #define E_BREG_CAPABILITIES 0x00000200
36 #define E_BREG_CONTROL 0x00000208
37 #define E_BREG_BASE_LO 0x00000210
38 #define E_BREG_BASE_HI 0x00000214
39 #define E_ECAM_CAPABILITIES 0x00000220
40 #define E_ECAM_CONTROL 0x00000228
41 #define E_ECAM_BASE_LO 0x00000230
42 #define E_ECAM_BASE_HI 0x00000234
44 /* Ingress - address translations */
45 #define I_MSII_CAPABILITIES 0x00000300
46 #define I_MSII_CONTROL 0x00000308
47 #define I_MSII_BASE_LO 0x00000310
48 #define I_MSII_BASE_HI 0x00000314
50 #define I_ISUB_CONTROL 0x000003E8
51 #define SET_ISUB_CONTROL BIT(0)
52 /* Rxed msg fifo - Interrupt status registers */
53 #define MSGF_MISC_STATUS 0x00000400
54 #define MSGF_MISC_MASK 0x00000404
55 #define MSGF_LEG_STATUS 0x00000420
56 #define MSGF_LEG_MASK 0x00000424
57 #define MSGF_MSI_STATUS_LO 0x00000440
58 #define MSGF_MSI_STATUS_HI 0x00000444
59 #define MSGF_MSI_MASK_LO 0x00000448
60 #define MSGF_MSI_MASK_HI 0x0000044C
62 /* Msg filter mask bits */
63 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
64 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
65 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
66 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
67 CFG_ENABLE_INT_MSG_FWD | \
68 CFG_ENABLE_ERR_MSG_FWD)
70 /* Misc interrupt status mask bits */
71 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
72 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
73 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
74 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
75 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
76 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
77 #define MSGF_MISC_SR_FATAL_AER BIT(16)
78 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
79 #define MSGF_MISC_SR_CORR_AER BIT(18)
80 #define MSGF_MISC_SR_UR_DETECT BIT(20)
81 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
82 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
83 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
84 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
85 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
87 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
88 MSGF_MISC_SR_RXMSG_OVER | \
89 MSGF_MISC_SR_SLAVE_ERR | \
90 MSGF_MISC_SR_MASTER_ERR | \
91 MSGF_MISC_SR_I_ADDR_ERR | \
92 MSGF_MISC_SR_E_ADDR_ERR | \
93 MSGF_MISC_SR_FATAL_AER | \
94 MSGF_MISC_SR_NON_FATAL_AER | \
95 MSGF_MISC_SR_CORR_AER | \
96 MSGF_MISC_SR_UR_DETECT | \
97 MSGF_MISC_SR_NON_FATAL_DEV | \
98 MSGF_MISC_SR_FATAL_DEV | \
99 MSGF_MISC_SR_LINK_DOWN | \
100 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
101 MSGF_MSIC_SR_LINK_BWIDTH)
103 /* Legacy interrupt status mask bits */
104 #define MSGF_LEG_SR_INTA BIT(0)
105 #define MSGF_LEG_SR_INTB BIT(1)
106 #define MSGF_LEG_SR_INTC BIT(2)
107 #define MSGF_LEG_SR_INTD BIT(3)
108 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
109 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
111 /* MSI interrupt status mask bits */
112 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
113 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
115 #define MSII_PRESENT BIT(0)
116 #define MSII_ENABLE BIT(0)
117 #define MSII_STATUS_ENABLE BIT(15)
119 /* Bridge config interrupt mask */
120 #define BRCFG_INTERRUPT_MASK BIT(0)
121 #define BREG_PRESENT BIT(0)
122 #define BREG_ENABLE BIT(0)
123 #define BREG_ENABLE_FORCE BIT(1)
125 /* E_ECAM status mask bits */
126 #define E_ECAM_PRESENT BIT(0)
127 #define E_ECAM_CR_ENABLE BIT(0)
128 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
129 #define E_ECAM_SIZE_SHIFT 16
130 #define ECAM_BUS_LOC_SHIFT 20
131 #define ECAM_DEV_LOC_SHIFT 12
132 #define NWL_ECAM_VALUE_DEFAULT 12
134 #define CFG_DMA_REG_BAR GENMASK(2, 0)
136 #define INT_PCI_MSI_NR (2 * 32)
138 /* Readin the PS_LINKUP */
139 #define PS_LINKUP_OFFSET 0x00000238
140 #define PCIE_PHY_LINKUP_BIT BIT(0)
141 #define PHY_RDY_LINKUP_BIT BIT(1)
143 /* Parameters for the waiting for link up routine */
144 #define LINK_WAIT_MAX_RETRIES 10
145 #define LINK_WAIT_USLEEP_MIN 90000
146 #define LINK_WAIT_USLEEP_MAX 100000
148 struct nwl_msi { /* MSI information */
149 struct irq_domain *msi_domain;
150 unsigned long *bitmap;
151 struct irq_domain *dev_domain;
152 struct mutex lock; /* protect bitmap variable */
159 void __iomem *breg_base;
160 void __iomem *pcireg_base;
161 void __iomem *ecam_base;
162 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
164 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
174 struct irq_domain *legacy_irq_domain;
176 raw_spinlock_t leg_mask_lock;
179 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
181 return readl(pcie->breg_base + off);
184 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
186 writel(val, pcie->breg_base + off);
189 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
191 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
196 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
198 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
203 static int nwl_wait_for_link(struct nwl_pcie *pcie)
205 struct device *dev = pcie->dev;
208 /* check if the link is up or not */
209 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
210 if (nwl_phy_link_up(pcie))
212 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
215 dev_err(dev, "PHY link never came up\n");
219 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
221 struct nwl_pcie *pcie = bus->sysdata;
223 /* Check link before accessing downstream ports */
224 if (bus->number != pcie->root_busno) {
225 if (!nwl_pcie_link_up(pcie))
229 /* Only one device down on each root port */
230 if (bus->number == pcie->root_busno && devfn > 0)
237 * nwl_pcie_map_bus - Get configuration base
239 * @bus: Bus structure of current bus
240 * @devfn: Device/function
241 * @where: Offset from base
243 * Return: Base address of the configuration space needed to be
246 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
249 struct nwl_pcie *pcie = bus->sysdata;
252 if (!nwl_pcie_valid_device(bus, devfn))
255 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
256 (devfn << ECAM_DEV_LOC_SHIFT);
258 return pcie->ecam_base + relbus + where;
261 /* PCIe operations */
262 static struct pci_ops nwl_pcie_ops = {
263 .map_bus = nwl_pcie_map_bus,
264 .read = pci_generic_config_read,
265 .write = pci_generic_config_write,
268 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
270 struct nwl_pcie *pcie = data;
271 struct device *dev = pcie->dev;
274 /* Checking for misc interrupts */
275 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
276 MSGF_MISC_SR_MASKALL;
280 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
281 dev_err(dev, "Received Message FIFO Overflow\n");
283 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
284 dev_err(dev, "Slave error\n");
286 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
287 dev_err(dev, "Master error\n");
289 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
290 dev_err(dev, "In Misc Ingress address translation error\n");
292 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
293 dev_err(dev, "In Misc Egress address translation error\n");
295 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
296 dev_err(dev, "Fatal Error in AER Capability\n");
298 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
299 dev_err(dev, "Non-Fatal Error in AER Capability\n");
301 if (misc_stat & MSGF_MISC_SR_CORR_AER)
302 dev_err(dev, "Correctable Error in AER Capability\n");
304 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
305 dev_err(dev, "Unsupported request Detected\n");
307 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
308 dev_err(dev, "Non-Fatal Error Detected\n");
310 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
311 dev_err(dev, "Fatal Error Detected\n");
313 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
314 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
316 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
317 dev_info(dev, "Link Bandwidth Management Status bit set\n");
319 /* Clear misc interrupt status */
320 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
325 static void nwl_pcie_leg_handler(struct irq_desc *desc)
327 struct irq_chip *chip = irq_desc_get_chip(desc);
328 struct nwl_pcie *pcie;
329 unsigned long status;
333 chained_irq_enter(chip, desc);
334 pcie = irq_desc_get_handler_data(desc);
336 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
337 MSGF_LEG_SR_MASKALL) != 0) {
338 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
339 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
341 generic_handle_irq(virq);
345 chained_irq_exit(chip, desc);
348 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
351 unsigned long status;
357 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
358 for_each_set_bit(bit, &status, 32) {
359 nwl_bridge_writel(pcie, 1 << bit, status_reg);
360 virq = irq_find_mapping(msi->dev_domain, bit);
362 generic_handle_irq(virq);
367 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
369 struct irq_chip *chip = irq_desc_get_chip(desc);
370 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
372 chained_irq_enter(chip, desc);
373 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
374 chained_irq_exit(chip, desc);
377 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
379 struct irq_chip *chip = irq_desc_get_chip(desc);
380 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
382 chained_irq_enter(chip, desc);
383 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
384 chained_irq_exit(chip, desc);
387 static void nwl_mask_leg_irq(struct irq_data *data)
389 struct irq_desc *desc = irq_to_desc(data->irq);
390 struct nwl_pcie *pcie;
395 pcie = irq_desc_get_chip_data(desc);
396 mask = 1 << (data->hwirq - 1);
397 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
398 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
399 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
400 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
403 static void nwl_unmask_leg_irq(struct irq_data *data)
405 struct irq_desc *desc = irq_to_desc(data->irq);
406 struct nwl_pcie *pcie;
411 pcie = irq_desc_get_chip_data(desc);
412 mask = 1 << (data->hwirq - 1);
413 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
414 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
415 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
416 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
419 static struct irq_chip nwl_leg_irq_chip = {
420 .name = "nwl_pcie:legacy",
421 .irq_enable = nwl_unmask_leg_irq,
422 .irq_disable = nwl_mask_leg_irq,
423 .irq_mask = nwl_mask_leg_irq,
424 .irq_unmask = nwl_unmask_leg_irq,
427 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
428 irq_hw_number_t hwirq)
430 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
431 irq_set_chip_data(irq, domain->host_data);
432 irq_set_status_flags(irq, IRQ_LEVEL);
437 static const struct irq_domain_ops legacy_domain_ops = {
438 .map = nwl_legacy_map,
439 .xlate = pci_irqd_intx_xlate,
442 #ifdef CONFIG_PCI_MSI
443 static struct irq_chip nwl_msi_irq_chip = {
444 .name = "nwl_pcie:msi",
445 .irq_enable = unmask_msi_irq,
446 .irq_disable = mask_msi_irq,
447 .irq_mask = mask_msi_irq,
448 .irq_unmask = unmask_msi_irq,
452 static struct msi_domain_info nwl_msi_domain_info = {
453 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
454 MSI_FLAG_MULTI_PCI_MSI),
455 .chip = &nwl_msi_irq_chip,
459 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
461 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
462 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
464 msg->address_lo = lower_32_bits(msi_addr);
465 msg->address_hi = upper_32_bits(msi_addr);
466 msg->data = data->hwirq;
469 static int nwl_msi_set_affinity(struct irq_data *irq_data,
470 const struct cpumask *mask, bool force)
475 static struct irq_chip nwl_irq_chip = {
476 .name = "Xilinx MSI",
477 .irq_compose_msi_msg = nwl_compose_msi_msg,
478 .irq_set_affinity = nwl_msi_set_affinity,
481 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
482 unsigned int nr_irqs, void *args)
484 struct nwl_pcie *pcie = domain->host_data;
485 struct nwl_msi *msi = &pcie->msi;
489 mutex_lock(&msi->lock);
490 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
491 get_count_order(nr_irqs));
493 mutex_unlock(&msi->lock);
497 for (i = 0; i < nr_irqs; i++) {
498 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
499 domain->host_data, handle_simple_irq,
502 mutex_unlock(&msi->lock);
506 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
507 unsigned int nr_irqs)
509 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
510 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
511 struct nwl_msi *msi = &pcie->msi;
513 mutex_lock(&msi->lock);
514 bitmap_release_region(msi->bitmap, data->hwirq,
515 get_count_order(nr_irqs));
516 mutex_unlock(&msi->lock);
519 static const struct irq_domain_ops dev_msi_domain_ops = {
520 .alloc = nwl_irq_domain_alloc,
521 .free = nwl_irq_domain_free,
524 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
526 #ifdef CONFIG_PCI_MSI
527 struct device *dev = pcie->dev;
528 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
529 struct nwl_msi *msi = &pcie->msi;
531 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
532 &dev_msi_domain_ops, pcie);
533 if (!msi->dev_domain) {
534 dev_err(dev, "failed to create dev IRQ domain\n");
537 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
538 &nwl_msi_domain_info,
540 if (!msi->msi_domain) {
541 dev_err(dev, "failed to create msi IRQ domain\n");
542 irq_domain_remove(msi->dev_domain);
549 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
551 struct device *dev = pcie->dev;
552 struct device_node *node = dev->of_node;
553 struct device_node *legacy_intc_node;
555 legacy_intc_node = of_get_next_child(node, NULL);
556 if (!legacy_intc_node) {
557 dev_err(dev, "No legacy intc node found\n");
561 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
565 of_node_put(legacy_intc_node);
566 if (!pcie->legacy_irq_domain) {
567 dev_err(dev, "failed to create IRQ domain\n");
571 raw_spin_lock_init(&pcie->leg_mask_lock);
572 nwl_pcie_init_msi_irq_domain(pcie);
576 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
578 struct device *dev = pcie->dev;
579 struct platform_device *pdev = to_platform_device(dev);
580 struct nwl_msi *msi = &pcie->msi;
583 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
585 mutex_init(&msi->lock);
587 msi->bitmap = kzalloc(size, GFP_KERNEL);
591 /* Get msi_1 IRQ number */
592 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
593 if (msi->irq_msi1 < 0) {
594 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
599 irq_set_chained_handler_and_data(msi->irq_msi1,
600 nwl_pcie_msi_handler_high, pcie);
602 /* Get msi_0 IRQ number */
603 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
604 if (msi->irq_msi0 < 0) {
605 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
610 irq_set_chained_handler_and_data(msi->irq_msi0,
611 nwl_pcie_msi_handler_low, pcie);
613 /* Check for msii_present bit */
614 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
616 dev_err(dev, "MSI not present\n");
622 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
623 MSII_ENABLE, I_MSII_CONTROL);
625 /* Enable MSII status */
626 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
627 MSII_STATUS_ENABLE, I_MSII_CONTROL);
629 /* setup AFI/FPCI range */
630 base = pcie->phys_pcie_reg_base;
631 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
632 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
635 * For high range MSI interrupts: disable, clear any pending,
638 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
640 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
641 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
643 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
646 * For low range MSI interrupts: disable, clear any pending,
649 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
651 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
652 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
654 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
663 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
665 struct device *dev = pcie->dev;
666 struct platform_device *pdev = to_platform_device(dev);
667 u32 breg_val, ecam_val, first_busno = 0;
670 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
672 dev_err(dev, "BREG is not present\n");
676 /* Write bridge_off to breg base */
677 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
679 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
683 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
686 /* Disable DMA channel registers */
687 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
688 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
690 /* Enable Ingress subtractive decode translation */
691 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
693 /* Enable msg filtering details */
694 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
695 BRCFG_PCIE_RX_MSG_FILTER);
697 err = nwl_wait_for_link(pcie);
701 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
703 dev_err(dev, "ECAM is not present\n");
708 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
709 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
711 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
712 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
715 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
717 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
721 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
722 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
723 /* Write primary, secondary and subordinate bus numbers */
724 ecam_val = first_busno;
725 ecam_val |= (first_busno + 1) << 8;
726 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
727 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
729 if (nwl_pcie_link_up(pcie))
730 dev_info(dev, "Link is UP\n");
732 dev_info(dev, "Link is DOWN\n");
734 /* Get misc IRQ number */
735 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
736 if (pcie->irq_misc < 0) {
737 dev_err(dev, "failed to get misc IRQ %d\n",
742 err = devm_request_irq(dev, pcie->irq_misc,
743 nwl_pcie_misc_handler, IRQF_SHARED,
744 "nwl_pcie:misc", pcie);
746 dev_err(dev, "fail to register misc IRQ#%d\n",
751 /* Disable all misc interrupts */
752 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
754 /* Clear pending misc interrupts */
755 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
756 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
758 /* Enable all misc interrupts */
759 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
762 /* Disable all legacy interrupts */
763 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
765 /* Clear pending legacy interrupts */
766 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
767 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
769 /* Enable all legacy interrupts */
770 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
772 /* Enable the bridge config interrupt */
773 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
774 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
779 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
780 struct platform_device *pdev)
782 struct device *dev = pcie->dev;
783 struct device_node *node = dev->of_node;
784 struct resource *res;
787 /* Check for device type */
788 type = of_get_property(node, "device_type", NULL);
789 if (!type || strcmp(type, "pci")) {
790 dev_err(dev, "invalid \"device_type\" %s\n", type);
794 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
795 pcie->breg_base = devm_ioremap_resource(dev, res);
796 if (IS_ERR(pcie->breg_base))
797 return PTR_ERR(pcie->breg_base);
798 pcie->phys_breg_base = res->start;
800 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
801 pcie->pcireg_base = devm_ioremap_resource(dev, res);
802 if (IS_ERR(pcie->pcireg_base))
803 return PTR_ERR(pcie->pcireg_base);
804 pcie->phys_pcie_reg_base = res->start;
806 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
807 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
808 if (IS_ERR(pcie->ecam_base))
809 return PTR_ERR(pcie->ecam_base);
810 pcie->phys_ecam_base = res->start;
812 /* Get intx IRQ number */
813 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
814 if (pcie->irq_intx < 0) {
815 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
816 return pcie->irq_intx;
819 irq_set_chained_handler_and_data(pcie->irq_intx,
820 nwl_pcie_leg_handler, pcie);
825 static const struct of_device_id nwl_pcie_of_match[] = {
826 { .compatible = "xlnx,nwl-pcie-2.11", },
830 static int nwl_pcie_probe(struct platform_device *pdev)
832 struct device *dev = &pdev->dev;
833 struct device_node *node = dev->of_node;
834 struct nwl_pcie *pcie;
836 struct pci_bus *child;
837 struct pci_host_bridge *bridge;
839 resource_size_t iobase = 0;
842 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
846 pcie = pci_host_bridge_priv(bridge);
849 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
851 err = nwl_pcie_parse_dt(pcie, pdev);
853 dev_err(dev, "Parsing DT failed\n");
857 pcie->clk = devm_clk_get(dev, NULL);
858 if (IS_ERR(pcie->clk))
859 return PTR_ERR(pcie->clk);
861 err = clk_prepare_enable(pcie->clk);
863 dev_err(dev, "can't enable PCIe ref clock\n");
867 err = nwl_pcie_bridge_init(pcie);
869 dev_err(dev, "HW Initialization failed\n");
873 err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
875 dev_err(dev, "Getting bridge resources failed\n");
879 err = devm_request_pci_bus_resources(dev, &res);
883 err = nwl_pcie_init_irq_domain(pcie);
885 dev_err(dev, "Failed creating IRQ Domain\n");
889 list_splice_init(&res, &bridge->windows);
890 bridge->dev.parent = dev;
891 bridge->sysdata = pcie;
892 bridge->busnr = pcie->root_busno;
893 bridge->ops = &nwl_pcie_ops;
894 bridge->map_irq = of_irq_parse_and_map_pci;
895 bridge->swizzle_irq = pci_common_swizzle;
897 if (IS_ENABLED(CONFIG_PCI_MSI)) {
898 err = nwl_pcie_enable_msi(pcie);
900 dev_err(dev, "failed to enable MSI support: %d\n", err);
905 err = pci_scan_root_bus_bridge(bridge);
911 pci_assign_unassigned_bus_resources(bus);
912 list_for_each_entry(child, &bus->children, node)
913 pcie_bus_configure_settings(child);
914 pci_bus_add_devices(bus);
918 pci_free_resource_list(&res);
922 static struct platform_driver nwl_pcie_driver = {
925 .suppress_bind_attrs = true,
926 .of_match_table = nwl_pcie_of_match,
928 .probe = nwl_pcie_probe,
930 builtin_platform_driver(nwl_pcie_driver);