2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
57 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
58 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
59 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
60 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
61 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
62 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
63 #define PCIE_CLIENT_INTR_SHIFT 5
64 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
65 #define PCIE_CLIENT_INT_MSG BIT(14)
66 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
67 #define PCIE_CLIENT_INT_DPA BIT(12)
68 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
69 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
70 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
71 #define PCIE_CLIENT_INT_INTD BIT(8)
72 #define PCIE_CLIENT_INT_INTC BIT(7)
73 #define PCIE_CLIENT_INT_INTB BIT(6)
74 #define PCIE_CLIENT_INT_INTA BIT(5)
75 #define PCIE_CLIENT_INT_LOCAL BIT(4)
76 #define PCIE_CLIENT_INT_UDMA BIT(3)
77 #define PCIE_CLIENT_INT_PHY BIT(2)
78 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
79 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
81 #define PCIE_CLIENT_INT_LEGACY \
82 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
83 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
85 #define PCIE_CLIENT_INT_CLI \
86 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
87 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
88 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
89 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
92 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
93 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
94 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
95 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
96 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
97 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
98 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
99 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
100 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
101 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
102 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
103 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
104 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
105 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
106 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
107 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
108 #define PCIE_CORE_INT_PRFPE BIT(0)
109 #define PCIE_CORE_INT_CRFPE BIT(1)
110 #define PCIE_CORE_INT_RRPE BIT(2)
111 #define PCIE_CORE_INT_PRFO BIT(3)
112 #define PCIE_CORE_INT_CRFO BIT(4)
113 #define PCIE_CORE_INT_RT BIT(5)
114 #define PCIE_CORE_INT_RTR BIT(6)
115 #define PCIE_CORE_INT_PE BIT(7)
116 #define PCIE_CORE_INT_MTR BIT(8)
117 #define PCIE_CORE_INT_UCR BIT(9)
118 #define PCIE_CORE_INT_FCE BIT(10)
119 #define PCIE_CORE_INT_CT BIT(11)
120 #define PCIE_CORE_INT_UTC BIT(18)
121 #define PCIE_CORE_INT_MMVC BIT(19)
122 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
123 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
125 #define PCIE_CORE_INT \
126 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
127 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
128 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
129 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
130 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
131 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
134 #define PCIE_RC_CONFIG_BASE 0xa00000
135 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
136 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
137 #define PCIE_RC_CONFIG_SCC_SHIFT 16
138 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
139 #define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
140 #define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
141 #define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
142 #define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
143 #define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
144 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
146 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
147 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
148 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
149 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
150 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
151 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
152 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
154 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
155 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
156 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
157 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
158 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
160 /* Size of one AXI Region (not Region 0) */
161 #define AXI_REGION_SIZE BIT(20)
162 /* Size of Region 0, equal to sum of sizes of other regions */
163 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
164 #define OB_REG_SIZE_SHIFT 5
165 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
166 #define AXI_WRAPPER_IO_WRITE 0x6
167 #define AXI_WRAPPER_MEM_WRITE 0x2
169 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
170 #define MIN_AXI_ADDR_BITS_PASSED 8
171 #define ROCKCHIP_VENDOR_ID 0x1d87
172 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
173 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
174 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
175 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
176 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
177 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
178 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
180 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
181 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
182 #define RC_REGION_0_PASS_BITS (25 - 1)
183 #define MAX_AXI_WRAPPER_REGION_NUM 33
185 struct rockchip_pcie {
186 void __iomem *reg_base; /* DT axi-base */
187 void __iomem *apb_base; /* DT apb-base */
189 struct reset_control *core_rst;
190 struct reset_control *mgmt_rst;
191 struct reset_control *mgmt_sticky_rst;
192 struct reset_control *pipe_rst;
193 struct reset_control *pm_rst;
194 struct reset_control *aclk_rst;
195 struct reset_control *pclk_rst;
196 struct clk *aclk_pcie;
197 struct clk *aclk_perf_pcie;
198 struct clk *hclk_pcie;
199 struct clk *clk_pcie_pm;
200 struct regulator *vpcie3v3; /* 3.3V power supply */
201 struct regulator *vpcie1v8; /* 1.8V power supply */
202 struct regulator *vpcie0v9; /* 0.9V power supply */
203 struct gpio_desc *ep_gpio;
207 struct irq_domain *irq_domain;
210 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
212 return readl(rockchip->apb_base + reg);
215 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
218 writel(val, rockchip->apb_base + reg);
221 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
225 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
226 status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
227 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
230 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
234 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
235 status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
236 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
239 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
243 /* Update Tx credit maximum update interval */
244 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
245 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
246 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
247 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
250 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
251 struct pci_bus *bus, int dev)
253 /* access only one slot on each root port */
254 if (bus->number == rockchip->root_bus_nr && dev > 0)
258 * do not read more than one device on the bus directly attached
259 * to RC's downstream side.
261 if (bus->primary == rockchip->root_bus_nr && dev > 0)
267 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
268 int where, int size, u32 *val)
270 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
272 if (!IS_ALIGNED((uintptr_t)addr, size)) {
274 return PCIBIOS_BAD_REGISTER_NUMBER;
279 } else if (size == 2) {
281 } else if (size == 1) {
285 return PCIBIOS_BAD_REGISTER_NUMBER;
287 return PCIBIOS_SUCCESSFUL;
290 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
291 int where, int size, u32 val)
293 u32 mask, tmp, offset;
295 offset = where & ~0x3;
298 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
299 return PCIBIOS_SUCCESSFUL;
302 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
305 * N.B. This read/modify/write isn't safe in general because it can
306 * corrupt RW1C bits in adjacent registers. But the hardware
307 * doesn't support smaller writes.
309 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
310 tmp |= val << ((where & 0x3) * 8);
311 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
313 return PCIBIOS_SUCCESSFUL;
316 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
317 struct pci_bus *bus, u32 devfn,
318 int where, int size, u32 *val)
322 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
323 PCI_FUNC(devfn), where);
325 if (!IS_ALIGNED(busdev, size)) {
327 return PCIBIOS_BAD_REGISTER_NUMBER;
331 *val = readl(rockchip->reg_base + busdev);
332 } else if (size == 2) {
333 *val = readw(rockchip->reg_base + busdev);
334 } else if (size == 1) {
335 *val = readb(rockchip->reg_base + busdev);
338 return PCIBIOS_BAD_REGISTER_NUMBER;
340 return PCIBIOS_SUCCESSFUL;
343 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
344 struct pci_bus *bus, u32 devfn,
345 int where, int size, u32 val)
349 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
350 PCI_FUNC(devfn), where);
351 if (!IS_ALIGNED(busdev, size))
352 return PCIBIOS_BAD_REGISTER_NUMBER;
355 writel(val, rockchip->reg_base + busdev);
357 writew(val, rockchip->reg_base + busdev);
359 writeb(val, rockchip->reg_base + busdev);
361 return PCIBIOS_BAD_REGISTER_NUMBER;
363 return PCIBIOS_SUCCESSFUL;
366 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
369 struct rockchip_pcie *rockchip = bus->sysdata;
371 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
373 return PCIBIOS_DEVICE_NOT_FOUND;
376 if (bus->number == rockchip->root_bus_nr)
377 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
379 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
382 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
383 int where, int size, u32 val)
385 struct rockchip_pcie *rockchip = bus->sysdata;
387 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
388 return PCIBIOS_DEVICE_NOT_FOUND;
390 if (bus->number == rockchip->root_bus_nr)
391 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
393 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
396 static struct pci_ops rockchip_pcie_ops = {
397 .read = rockchip_pcie_rd_conf,
398 .write = rockchip_pcie_wr_conf,
402 * rockchip_pcie_init_port - Initialize hardware
403 * @rockchip: PCIe port information
405 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
407 struct device *dev = rockchip->dev;
410 unsigned long timeout;
412 gpiod_set_value(rockchip->ep_gpio, 0);
414 err = reset_control_assert(rockchip->aclk_rst);
416 dev_err(dev, "assert aclk_rst err %d\n", err);
420 err = reset_control_assert(rockchip->pclk_rst);
422 dev_err(dev, "assert pclk_rst err %d\n", err);
426 err = reset_control_assert(rockchip->pm_rst);
428 dev_err(dev, "assert pm_rst err %d\n", err);
434 err = reset_control_deassert(rockchip->pm_rst);
436 dev_err(dev, "deassert pm_rst err %d\n", err);
440 err = reset_control_deassert(rockchip->aclk_rst);
442 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
446 err = reset_control_deassert(rockchip->pclk_rst);
448 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
452 err = phy_init(rockchip->phy);
454 dev_err(dev, "fail to init phy, err %d\n", err);
458 err = reset_control_assert(rockchip->core_rst);
460 dev_err(dev, "assert core_rst err %d\n", err);
464 err = reset_control_assert(rockchip->mgmt_rst);
466 dev_err(dev, "assert mgmt_rst err %d\n", err);
470 err = reset_control_assert(rockchip->mgmt_sticky_rst);
472 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
476 err = reset_control_assert(rockchip->pipe_rst);
478 dev_err(dev, "assert pipe_rst err %d\n", err);
482 rockchip_pcie_write(rockchip,
483 PCIE_CLIENT_CONF_ENABLE |
484 PCIE_CLIENT_LINK_TRAIN_ENABLE |
485 PCIE_CLIENT_ARI_ENABLE |
486 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
487 PCIE_CLIENT_MODE_RC |
488 PCIE_CLIENT_GEN_SEL_2,
491 err = phy_power_on(rockchip->phy);
493 dev_err(dev, "fail to power on phy, err %d\n", err);
498 * Please don't reorder the deassert sequence of the following
501 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
503 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
507 err = reset_control_deassert(rockchip->core_rst);
509 dev_err(dev, "deassert core_rst err %d\n", err);
513 err = reset_control_deassert(rockchip->mgmt_rst);
515 dev_err(dev, "deassert mgmt_rst err %d\n", err);
519 err = reset_control_deassert(rockchip->pipe_rst);
521 dev_err(dev, "deassert pipe_rst err %d\n", err);
526 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
527 * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
528 * reliable and enabling ASPM doesn't work. This is a controller
529 * bug we need to work around.
531 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
532 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
534 /* Fix the transmitted FTS count desired to exit from L0s. */
535 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
536 status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
537 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
538 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
540 /* Enable Gen1 training */
541 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
544 gpiod_set_value(rockchip->ep_gpio, 1);
546 /* 500ms timeout value should be enough for Gen1/2 training */
547 timeout = jiffies + msecs_to_jiffies(500);
550 status = rockchip_pcie_read(rockchip,
551 PCIE_CLIENT_BASIC_STATUS1);
552 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
553 PCIE_CLIENT_LINK_STATUS_UP) {
554 dev_dbg(dev, "PCIe link training gen1 pass!\n");
558 if (time_after(jiffies, timeout)) {
559 dev_err(dev, "PCIe link training gen1 timeout!\n");
567 * Enable retrain for gen2. This should be configured only after
570 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
571 status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
572 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
574 timeout = jiffies + msecs_to_jiffies(500);
576 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
577 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
578 PCIE_CORE_PL_CONF_SPEED_5G) {
579 dev_dbg(dev, "PCIe link training gen2 pass!\n");
583 if (time_after(jiffies, timeout)) {
584 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
591 /* Check the final link width from negotiated lane counter from MGMT */
592 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
593 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
594 PCIE_CORE_PL_CONF_LANE_MASK);
595 dev_dbg(dev, "current link width is x%d\n", status);
597 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
598 PCIE_RC_CONFIG_VENDOR);
599 rockchip_pcie_write(rockchip,
600 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
601 PCIE_RC_CONFIG_RID_CCR);
602 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
604 rockchip_pcie_write(rockchip,
605 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
606 PCIE_CORE_OB_REGION_ADDR0);
607 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
608 PCIE_CORE_OB_REGION_ADDR1);
609 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
610 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
615 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
617 struct rockchip_pcie *rockchip = arg;
618 struct device *dev = rockchip->dev;
622 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
623 if (reg & PCIE_CLIENT_INT_LOCAL) {
624 dev_dbg(dev, "local interrupt received\n");
625 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
626 if (sub_reg & PCIE_CORE_INT_PRFPE)
627 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
629 if (sub_reg & PCIE_CORE_INT_CRFPE)
630 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
632 if (sub_reg & PCIE_CORE_INT_RRPE)
633 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
635 if (sub_reg & PCIE_CORE_INT_PRFO)
636 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
638 if (sub_reg & PCIE_CORE_INT_CRFO)
639 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
641 if (sub_reg & PCIE_CORE_INT_RT)
642 dev_dbg(dev, "replay timer timed out\n");
644 if (sub_reg & PCIE_CORE_INT_RTR)
645 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
647 if (sub_reg & PCIE_CORE_INT_PE)
648 dev_dbg(dev, "phy error detected on receive side\n");
650 if (sub_reg & PCIE_CORE_INT_MTR)
651 dev_dbg(dev, "malformed TLP received from the link\n");
653 if (sub_reg & PCIE_CORE_INT_UCR)
654 dev_dbg(dev, "malformed TLP received from the link\n");
656 if (sub_reg & PCIE_CORE_INT_FCE)
657 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
659 if (sub_reg & PCIE_CORE_INT_CT)
660 dev_dbg(dev, "a request timed out waiting for completion\n");
662 if (sub_reg & PCIE_CORE_INT_UTC)
663 dev_dbg(dev, "unmapped TC error\n");
665 if (sub_reg & PCIE_CORE_INT_MMVC)
666 dev_dbg(dev, "MSI mask register changes\n");
668 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
669 } else if (reg & PCIE_CLIENT_INT_PHY) {
670 dev_dbg(dev, "phy link changes\n");
671 rockchip_pcie_update_txcredit_mui(rockchip);
672 rockchip_pcie_clr_bw_int(rockchip);
675 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
676 PCIE_CLIENT_INT_STATUS);
681 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
683 struct rockchip_pcie *rockchip = arg;
684 struct device *dev = rockchip->dev;
687 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
688 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
689 dev_dbg(dev, "legacy done interrupt received\n");
691 if (reg & PCIE_CLIENT_INT_MSG)
692 dev_dbg(dev, "message done interrupt received\n");
694 if (reg & PCIE_CLIENT_INT_HOT_RST)
695 dev_dbg(dev, "hot reset interrupt received\n");
697 if (reg & PCIE_CLIENT_INT_DPA)
698 dev_dbg(dev, "dpa interrupt received\n");
700 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
701 dev_dbg(dev, "fatal error interrupt received\n");
703 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
704 dev_dbg(dev, "no fatal error interrupt received\n");
706 if (reg & PCIE_CLIENT_INT_CORR_ERR)
707 dev_dbg(dev, "correctable error interrupt received\n");
709 if (reg & PCIE_CLIENT_INT_PHY)
710 dev_dbg(dev, "phy interrupt received\n");
712 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
713 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
714 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
715 PCIE_CLIENT_INT_NFATAL_ERR |
716 PCIE_CLIENT_INT_CORR_ERR |
717 PCIE_CLIENT_INT_PHY),
718 PCIE_CLIENT_INT_STATUS);
723 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
725 struct irq_chip *chip = irq_desc_get_chip(desc);
726 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
727 struct device *dev = rockchip->dev;
732 chained_irq_enter(chip, desc);
734 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
735 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
738 hwirq = ffs(reg) - 1;
741 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
743 generic_handle_irq(virq);
745 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
748 chained_irq_exit(chip, desc);
753 * rockchip_pcie_parse_dt - Parse Device Tree
754 * @rockchip: PCIe port information
756 * Return: '0' on success and error value on failure
758 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
760 struct device *dev = rockchip->dev;
761 struct platform_device *pdev = to_platform_device(dev);
762 struct device_node *node = dev->of_node;
763 struct resource *regs;
767 regs = platform_get_resource_byname(pdev,
770 rockchip->reg_base = devm_ioremap_resource(dev, regs);
771 if (IS_ERR(rockchip->reg_base))
772 return PTR_ERR(rockchip->reg_base);
774 regs = platform_get_resource_byname(pdev,
777 rockchip->apb_base = devm_ioremap_resource(dev, regs);
778 if (IS_ERR(rockchip->apb_base))
779 return PTR_ERR(rockchip->apb_base);
781 rockchip->phy = devm_phy_get(dev, "pcie-phy");
782 if (IS_ERR(rockchip->phy)) {
783 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
784 dev_err(dev, "missing phy\n");
785 return PTR_ERR(rockchip->phy);
789 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
790 if (!err && (rockchip->lanes == 0 ||
791 rockchip->lanes == 3 ||
792 rockchip->lanes > 4)) {
793 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
797 rockchip->core_rst = devm_reset_control_get(dev, "core");
798 if (IS_ERR(rockchip->core_rst)) {
799 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
800 dev_err(dev, "missing core reset property in node\n");
801 return PTR_ERR(rockchip->core_rst);
804 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
805 if (IS_ERR(rockchip->mgmt_rst)) {
806 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
807 dev_err(dev, "missing mgmt reset property in node\n");
808 return PTR_ERR(rockchip->mgmt_rst);
811 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
812 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
813 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
814 dev_err(dev, "missing mgmt-sticky reset property in node\n");
815 return PTR_ERR(rockchip->mgmt_sticky_rst);
818 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
819 if (IS_ERR(rockchip->pipe_rst)) {
820 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
821 dev_err(dev, "missing pipe reset property in node\n");
822 return PTR_ERR(rockchip->pipe_rst);
825 rockchip->pm_rst = devm_reset_control_get(dev, "pm");
826 if (IS_ERR(rockchip->pm_rst)) {
827 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
828 dev_err(dev, "missing pm reset property in node\n");
829 return PTR_ERR(rockchip->pm_rst);
832 rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
833 if (IS_ERR(rockchip->pclk_rst)) {
834 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
835 dev_err(dev, "missing pclk reset property in node\n");
836 return PTR_ERR(rockchip->pclk_rst);
839 rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
840 if (IS_ERR(rockchip->aclk_rst)) {
841 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
842 dev_err(dev, "missing aclk reset property in node\n");
843 return PTR_ERR(rockchip->aclk_rst);
846 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
847 if (IS_ERR(rockchip->ep_gpio)) {
848 dev_err(dev, "missing ep-gpios property in node\n");
849 return PTR_ERR(rockchip->ep_gpio);
852 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
853 if (IS_ERR(rockchip->aclk_pcie)) {
854 dev_err(dev, "aclk clock not found\n");
855 return PTR_ERR(rockchip->aclk_pcie);
858 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
859 if (IS_ERR(rockchip->aclk_perf_pcie)) {
860 dev_err(dev, "aclk_perf clock not found\n");
861 return PTR_ERR(rockchip->aclk_perf_pcie);
864 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
865 if (IS_ERR(rockchip->hclk_pcie)) {
866 dev_err(dev, "hclk clock not found\n");
867 return PTR_ERR(rockchip->hclk_pcie);
870 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
871 if (IS_ERR(rockchip->clk_pcie_pm)) {
872 dev_err(dev, "pm clock not found\n");
873 return PTR_ERR(rockchip->clk_pcie_pm);
876 irq = platform_get_irq_byname(pdev, "sys");
878 dev_err(dev, "missing sys IRQ resource\n");
882 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
883 IRQF_SHARED, "pcie-sys", rockchip);
885 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
889 irq = platform_get_irq_byname(pdev, "legacy");
891 dev_err(dev, "missing legacy IRQ resource\n");
895 irq_set_chained_handler_and_data(irq,
896 rockchip_pcie_legacy_int_handler,
899 irq = platform_get_irq_byname(pdev, "client");
901 dev_err(dev, "missing client IRQ resource\n");
905 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
906 IRQF_SHARED, "pcie-client", rockchip);
908 dev_err(dev, "failed to request PCIe client IRQ\n");
912 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
913 if (IS_ERR(rockchip->vpcie3v3)) {
914 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
915 return -EPROBE_DEFER;
916 dev_info(dev, "no vpcie3v3 regulator found\n");
919 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
920 if (IS_ERR(rockchip->vpcie1v8)) {
921 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
922 return -EPROBE_DEFER;
923 dev_info(dev, "no vpcie1v8 regulator found\n");
926 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
927 if (IS_ERR(rockchip->vpcie0v9)) {
928 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
929 return -EPROBE_DEFER;
930 dev_info(dev, "no vpcie0v9 regulator found\n");
936 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
938 struct device *dev = rockchip->dev;
941 if (!IS_ERR(rockchip->vpcie3v3)) {
942 err = regulator_enable(rockchip->vpcie3v3);
944 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
949 if (!IS_ERR(rockchip->vpcie1v8)) {
950 err = regulator_enable(rockchip->vpcie1v8);
952 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
953 goto err_disable_3v3;
957 if (!IS_ERR(rockchip->vpcie0v9)) {
958 err = regulator_enable(rockchip->vpcie0v9);
960 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
961 goto err_disable_1v8;
968 if (!IS_ERR(rockchip->vpcie1v8))
969 regulator_disable(rockchip->vpcie1v8);
971 if (!IS_ERR(rockchip->vpcie3v3))
972 regulator_disable(rockchip->vpcie3v3);
977 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
979 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
980 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
981 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
984 rockchip_pcie_enable_bw_int(rockchip);
987 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
988 irq_hw_number_t hwirq)
990 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
991 irq_set_chip_data(irq, domain->host_data);
996 static const struct irq_domain_ops intx_domain_ops = {
997 .map = rockchip_pcie_intx_map,
1000 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
1002 struct device *dev = rockchip->dev;
1003 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
1006 dev_err(dev, "missing child interrupt-controller node\n");
1010 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
1011 &intx_domain_ops, rockchip);
1012 if (!rockchip->irq_domain) {
1013 dev_err(dev, "failed to get a INTx IRQ domain\n");
1020 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1021 int region_no, int type, u8 num_pass_bits,
1022 u32 lower_addr, u32 upper_addr)
1029 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1031 if (num_pass_bits + 1 < 8)
1033 if (num_pass_bits > 63)
1035 if (region_no == 0) {
1036 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1039 if (region_no != 0) {
1040 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1044 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1046 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1047 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1048 ob_addr_1 = upper_addr;
1049 ob_desc_0 = (1 << 23 | type);
1051 rockchip_pcie_write(rockchip, ob_addr_0,
1052 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1053 rockchip_pcie_write(rockchip, ob_addr_1,
1054 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1055 rockchip_pcie_write(rockchip, ob_desc_0,
1056 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1057 rockchip_pcie_write(rockchip, 0,
1058 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1063 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1064 int region_no, u8 num_pass_bits,
1065 u32 lower_addr, u32 upper_addr)
1071 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1073 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1075 if (num_pass_bits > 63)
1078 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1080 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1081 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1082 ib_addr_1 = upper_addr;
1084 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1085 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1090 static int rockchip_pcie_probe(struct platform_device *pdev)
1092 struct rockchip_pcie *rockchip;
1093 struct device *dev = &pdev->dev;
1094 struct pci_bus *bus, *child;
1095 struct resource_entry *win;
1096 resource_size_t io_base;
1097 struct resource *mem;
1098 struct resource *io;
1099 phys_addr_t io_bus_addr = 0;
1101 phys_addr_t mem_bus_addr = 0;
1112 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1116 rockchip->dev = dev;
1118 err = rockchip_pcie_parse_dt(rockchip);
1122 err = clk_prepare_enable(rockchip->aclk_pcie);
1124 dev_err(dev, "unable to enable aclk_pcie clock\n");
1128 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1130 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1131 goto err_aclk_perf_pcie;
1134 err = clk_prepare_enable(rockchip->hclk_pcie);
1136 dev_err(dev, "unable to enable hclk_pcie clock\n");
1140 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1142 dev_err(dev, "unable to enable hclk_pcie clock\n");
1146 err = rockchip_pcie_set_vpcie(rockchip);
1148 dev_err(dev, "failed to set vpcie regulator\n");
1152 err = rockchip_pcie_init_port(rockchip);
1156 rockchip_pcie_enable_interrupts(rockchip);
1158 err = rockchip_pcie_init_irq_domain(rockchip);
1162 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1167 err = devm_request_pci_bus_resources(dev, &res);
1171 /* Get the I/O and memory ranges from DT */
1173 resource_list_for_each_entry(win, &res) {
1174 switch (resource_type(win->res)) {
1178 io_size = resource_size(io);
1179 io_bus_addr = io->start - win->offset;
1180 err = pci_remap_iospace(io, io_base);
1182 dev_warn(dev, "error %d: failed to map resource %pR\n",
1187 case IORESOURCE_MEM:
1190 mem_size = resource_size(mem);
1191 mem_bus_addr = mem->start - win->offset;
1193 case IORESOURCE_BUS:
1194 rockchip->root_bus_nr = win->res->start;
1202 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1203 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1204 AXI_WRAPPER_MEM_WRITE,
1210 dev_err(dev, "program RC mem outbound ATU failed\n");
1216 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1218 dev_err(dev, "program RC mem inbound ATU failed\n");
1222 offset = mem_size >> 20;
1225 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1226 err = rockchip_pcie_prog_ob_atu(rockchip,
1227 reg_no + 1 + offset,
1228 AXI_WRAPPER_IO_WRITE,
1234 dev_err(dev, "program RC io outbound ATU failed\n");
1240 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1246 pci_bus_size_bridges(bus);
1247 pci_bus_assign_resources(bus);
1248 list_for_each_entry(child, &bus->children, node)
1249 pcie_bus_configure_settings(child);
1251 pci_bus_add_devices(bus);
1253 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1258 if (!IS_ERR(rockchip->vpcie3v3))
1259 regulator_disable(rockchip->vpcie3v3);
1260 if (!IS_ERR(rockchip->vpcie1v8))
1261 regulator_disable(rockchip->vpcie1v8);
1262 if (!IS_ERR(rockchip->vpcie0v9))
1263 regulator_disable(rockchip->vpcie0v9);
1265 clk_disable_unprepare(rockchip->clk_pcie_pm);
1267 clk_disable_unprepare(rockchip->hclk_pcie);
1269 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1271 clk_disable_unprepare(rockchip->aclk_pcie);
1276 static const struct of_device_id rockchip_pcie_of_match[] = {
1277 { .compatible = "rockchip,rk3399-pcie", },
1281 static struct platform_driver rockchip_pcie_driver = {
1283 .name = "rockchip-pcie",
1284 .of_match_table = rockchip_pcie_of_match,
1286 .probe = rockchip_pcie_probe,
1289 builtin_platform_driver(rockchip_pcie_driver);