2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys DesignWare Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/bitrev.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/iopoll.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/kernel.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/module.h>
31 #include <linux/of_address.h>
32 #include <linux/of_device.h>
33 #include <linux/of_pci.h>
34 #include <linux/of_platform.h>
35 #include <linux/of_irq.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/phy/phy.h>
39 #include <linux/platform_device.h>
40 #include <linux/reset.h>
41 #include <linux/regmap.h>
44 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
45 * bits. This allows atomic updates of the register without locking.
47 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
48 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
50 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
51 #define MAX_LANE_NUM 4
53 #define PCIE_CLIENT_BASE 0x0
54 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
55 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
56 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
57 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
58 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
59 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
60 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
61 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
62 #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
63 #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
64 #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18
65 #define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19
66 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
67 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
68 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
69 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
70 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
71 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
72 #define PCIE_CLIENT_INTR_SHIFT 5
73 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
74 #define PCIE_CLIENT_INT_MSG BIT(14)
75 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
76 #define PCIE_CLIENT_INT_DPA BIT(12)
77 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
78 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
79 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
80 #define PCIE_CLIENT_INT_INTD BIT(8)
81 #define PCIE_CLIENT_INT_INTC BIT(7)
82 #define PCIE_CLIENT_INT_INTB BIT(6)
83 #define PCIE_CLIENT_INT_INTA BIT(5)
84 #define PCIE_CLIENT_INT_LOCAL BIT(4)
85 #define PCIE_CLIENT_INT_UDMA BIT(3)
86 #define PCIE_CLIENT_INT_PHY BIT(2)
87 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
88 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
90 #define PCIE_CLIENT_INT_LEGACY \
91 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
92 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
94 #define PCIE_CLIENT_INT_CLI \
95 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
96 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
97 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
98 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
101 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
102 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
103 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
104 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
105 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
106 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
107 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
108 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
109 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
110 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
111 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
112 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
113 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
114 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
115 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
116 #define PCIE_CORE_LANE_MAP (PCIE_CORE_CTRL_MGMT_BASE + 0x200)
117 #define PCIE_CORE_LANE_MAP_MASK 0x0000000f
118 #define PCIE_CORE_LANE_MAP_REVERSE BIT(16)
119 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
120 #define PCIE_CORE_INT_PRFPE BIT(0)
121 #define PCIE_CORE_INT_CRFPE BIT(1)
122 #define PCIE_CORE_INT_RRPE BIT(2)
123 #define PCIE_CORE_INT_PRFO BIT(3)
124 #define PCIE_CORE_INT_CRFO BIT(4)
125 #define PCIE_CORE_INT_RT BIT(5)
126 #define PCIE_CORE_INT_RTR BIT(6)
127 #define PCIE_CORE_INT_PE BIT(7)
128 #define PCIE_CORE_INT_MTR BIT(8)
129 #define PCIE_CORE_INT_UCR BIT(9)
130 #define PCIE_CORE_INT_FCE BIT(10)
131 #define PCIE_CORE_INT_CT BIT(11)
132 #define PCIE_CORE_INT_UTC BIT(18)
133 #define PCIE_CORE_INT_MMVC BIT(19)
134 #define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44)
135 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
136 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
138 #define PCIE_CORE_INT \
139 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
140 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
141 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
142 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
143 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
144 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
147 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000
148 #define PCIE_RC_CONFIG_BASE 0xa00000
149 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
150 #define PCIE_RC_CONFIG_SCC_SHIFT 16
151 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
152 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
153 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
154 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
155 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8)
156 #define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5)
157 #define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5)
158 #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
159 #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
160 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
161 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
162 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
163 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
165 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
166 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
167 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
168 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
169 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
170 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
171 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
173 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
174 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
175 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
176 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
177 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
179 /* Size of one AXI Region (not Region 0) */
180 #define AXI_REGION_SIZE BIT(20)
181 /* Size of Region 0, equal to sum of sizes of other regions */
182 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
183 #define OB_REG_SIZE_SHIFT 5
184 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
185 #define AXI_WRAPPER_IO_WRITE 0x6
186 #define AXI_WRAPPER_MEM_WRITE 0x2
187 #define AXI_WRAPPER_TYPE0_CFG 0xa
188 #define AXI_WRAPPER_TYPE1_CFG 0xb
189 #define AXI_WRAPPER_NOR_MSG 0xc
191 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
192 #define MIN_AXI_ADDR_BITS_PASSED 8
193 #define PCIE_RC_SEND_PME_OFF 0x11960
194 #define ROCKCHIP_VENDOR_ID 0x1d87
195 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
196 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
197 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
198 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
199 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
200 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
201 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
202 #define PCIE_LINK_IS_L2(x) \
203 (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)
204 #define PCIE_LINK_UP(x) \
205 (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
206 #define PCIE_LINK_IS_GEN2(x) \
207 (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G)
209 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
210 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
211 #define RC_REGION_0_PASS_BITS (25 - 1)
212 #define RC_REGION_0_TYPE_MASK GENMASK(3, 0)
213 #define MAX_AXI_WRAPPER_REGION_NUM 33
215 struct rockchip_pcie {
216 void __iomem *reg_base; /* DT axi-base */
217 void __iomem *apb_base; /* DT apb-base */
219 struct phy *phys[MAX_LANE_NUM];
220 struct reset_control *core_rst;
221 struct reset_control *mgmt_rst;
222 struct reset_control *mgmt_sticky_rst;
223 struct reset_control *pipe_rst;
224 struct reset_control *pm_rst;
225 struct reset_control *aclk_rst;
226 struct reset_control *pclk_rst;
227 struct clk *aclk_pcie;
228 struct clk *aclk_perf_pcie;
229 struct clk *hclk_pcie;
230 struct clk *clk_pcie_pm;
231 struct regulator *vpcie12v; /* 12V power supply */
232 struct regulator *vpcie3v3; /* 3.3V power supply */
233 struct regulator *vpcie1v8; /* 1.8V power supply */
234 struct regulator *vpcie0v9; /* 0.9V power supply */
235 struct gpio_desc *ep_gpio;
241 struct irq_domain *irq_domain;
243 struct pci_bus *root_bus;
245 phys_addr_t io_bus_addr;
247 void __iomem *msg_region;
249 phys_addr_t msg_bus_addr;
250 phys_addr_t mem_bus_addr;
253 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
255 return readl(rockchip->apb_base + reg);
258 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
261 writel(val, rockchip->apb_base + reg);
264 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
268 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
269 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
270 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
273 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
277 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
278 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
279 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
282 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
286 /* Update Tx credit maximum update interval */
287 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
288 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
289 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
290 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
293 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
294 struct pci_bus *bus, int dev)
296 /* access only one slot on each root port */
297 if (bus->number == rockchip->root_bus_nr && dev > 0)
301 * do not read more than one device on the bus directly attached
302 * to RC's downstream side.
304 if (bus->primary == rockchip->root_bus_nr && dev > 0)
310 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
315 if (rockchip->legacy_phy)
316 return GENMASK(MAX_LANE_NUM - 1, 0);
318 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
319 map = val & PCIE_CORE_LANE_MAP_MASK;
321 /* The link may be using a reverse-indexed mapping. */
322 if (val & PCIE_CORE_LANE_MAP_REVERSE)
323 map = bitrev8(map) >> 4;
328 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
329 int where, int size, u32 *val)
333 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
335 if (!IS_ALIGNED((uintptr_t)addr, size)) {
337 return PCIBIOS_BAD_REGISTER_NUMBER;
342 } else if (size == 2) {
344 } else if (size == 1) {
348 return PCIBIOS_BAD_REGISTER_NUMBER;
350 return PCIBIOS_SUCCESSFUL;
353 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
354 int where, int size, u32 val)
356 u32 mask, tmp, offset;
359 offset = where & ~0x3;
360 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
364 return PCIBIOS_SUCCESSFUL;
367 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
370 * N.B. This read/modify/write isn't safe in general because it can
371 * corrupt RW1C bits in adjacent registers. But the hardware
372 * doesn't support smaller writes.
374 tmp = readl(addr) & mask;
375 tmp |= val << ((where & 0x3) * 8);
378 return PCIBIOS_SUCCESSFUL;
381 static void rockchip_pcie_cfg_configuration_accesses(
382 struct rockchip_pcie *rockchip, u32 type)
386 /* Configuration Accesses for region 0 */
387 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
389 rockchip_pcie_write(rockchip,
390 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
391 PCIE_CORE_OB_REGION_ADDR0);
392 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
393 PCIE_CORE_OB_REGION_ADDR1);
394 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
395 ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
396 ob_desc_0 |= (type | (0x1 << 23));
397 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
398 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
401 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
402 struct pci_bus *bus, u32 devfn,
403 int where, int size, u32 *val)
407 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
408 PCI_FUNC(devfn), where);
410 if (!IS_ALIGNED(busdev, size)) {
412 return PCIBIOS_BAD_REGISTER_NUMBER;
415 if (bus->parent->number == rockchip->root_bus_nr)
416 rockchip_pcie_cfg_configuration_accesses(rockchip,
417 AXI_WRAPPER_TYPE0_CFG);
419 rockchip_pcie_cfg_configuration_accesses(rockchip,
420 AXI_WRAPPER_TYPE1_CFG);
423 *val = readl(rockchip->reg_base + busdev);
424 } else if (size == 2) {
425 *val = readw(rockchip->reg_base + busdev);
426 } else if (size == 1) {
427 *val = readb(rockchip->reg_base + busdev);
430 return PCIBIOS_BAD_REGISTER_NUMBER;
432 return PCIBIOS_SUCCESSFUL;
435 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
436 struct pci_bus *bus, u32 devfn,
437 int where, int size, u32 val)
441 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
442 PCI_FUNC(devfn), where);
443 if (!IS_ALIGNED(busdev, size))
444 return PCIBIOS_BAD_REGISTER_NUMBER;
446 if (bus->parent->number == rockchip->root_bus_nr)
447 rockchip_pcie_cfg_configuration_accesses(rockchip,
448 AXI_WRAPPER_TYPE0_CFG);
450 rockchip_pcie_cfg_configuration_accesses(rockchip,
451 AXI_WRAPPER_TYPE1_CFG);
454 writel(val, rockchip->reg_base + busdev);
456 writew(val, rockchip->reg_base + busdev);
458 writeb(val, rockchip->reg_base + busdev);
460 return PCIBIOS_BAD_REGISTER_NUMBER;
462 return PCIBIOS_SUCCESSFUL;
465 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
468 struct rockchip_pcie *rockchip = bus->sysdata;
470 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
472 return PCIBIOS_DEVICE_NOT_FOUND;
475 if (bus->number == rockchip->root_bus_nr)
476 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
478 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
481 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
482 int where, int size, u32 val)
484 struct rockchip_pcie *rockchip = bus->sysdata;
486 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
487 return PCIBIOS_DEVICE_NOT_FOUND;
489 if (bus->number == rockchip->root_bus_nr)
490 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
492 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
495 static struct pci_ops rockchip_pcie_ops = {
496 .read = rockchip_pcie_rd_conf,
497 .write = rockchip_pcie_wr_conf,
500 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
503 u32 status, scale, power;
505 if (IS_ERR(rockchip->vpcie3v3))
509 * Set RC's captured slot power limit and scale if
510 * vpcie3v3 available. The default values are both zero
511 * which means the software should set these two according
512 * to the actual power supply.
514 curr = regulator_get_current_limit(rockchip->vpcie3v3);
518 scale = 3; /* 0.001x */
519 curr = curr / 1000; /* convert to mA */
520 power = (curr * 3300) / 1000; /* milliwatt */
521 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
523 dev_warn(rockchip->dev, "invalid power supply\n");
530 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
531 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
532 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
533 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
537 * rockchip_pcie_init_port - Initialize hardware
538 * @rockchip: PCIe port information
540 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
542 struct device *dev = rockchip->dev;
546 gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
548 err = reset_control_assert(rockchip->aclk_rst);
550 dev_err(dev, "assert aclk_rst err %d\n", err);
554 err = reset_control_assert(rockchip->pclk_rst);
556 dev_err(dev, "assert pclk_rst err %d\n", err);
560 err = reset_control_assert(rockchip->pm_rst);
562 dev_err(dev, "assert pm_rst err %d\n", err);
566 for (i = 0; i < MAX_LANE_NUM; i++) {
567 err = phy_init(rockchip->phys[i]);
569 dev_err(dev, "init phy%d err %d\n", i, err);
574 err = reset_control_assert(rockchip->core_rst);
576 dev_err(dev, "assert core_rst err %d\n", err);
580 err = reset_control_assert(rockchip->mgmt_rst);
582 dev_err(dev, "assert mgmt_rst err %d\n", err);
586 err = reset_control_assert(rockchip->mgmt_sticky_rst);
588 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
592 err = reset_control_assert(rockchip->pipe_rst);
594 dev_err(dev, "assert pipe_rst err %d\n", err);
600 err = reset_control_deassert(rockchip->pm_rst);
602 dev_err(dev, "deassert pm_rst err %d\n", err);
606 err = reset_control_deassert(rockchip->aclk_rst);
608 dev_err(dev, "deassert aclk_rst err %d\n", err);
612 err = reset_control_deassert(rockchip->pclk_rst);
614 dev_err(dev, "deassert pclk_rst err %d\n", err);
618 if (rockchip->link_gen == 2)
619 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
622 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
625 rockchip_pcie_write(rockchip,
626 PCIE_CLIENT_CONF_ENABLE |
627 PCIE_CLIENT_LINK_TRAIN_ENABLE |
628 PCIE_CLIENT_ARI_ENABLE |
629 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
633 for (i = 0; i < MAX_LANE_NUM; i++) {
634 err = phy_power_on(rockchip->phys[i]);
636 dev_err(dev, "power on phy%d err %d\n", i, err);
637 goto err_power_off_phy;
642 * Please don't reorder the deassert sequence of the following
645 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
647 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
648 goto err_power_off_phy;
651 err = reset_control_deassert(rockchip->core_rst);
653 dev_err(dev, "deassert core_rst err %d\n", err);
654 goto err_power_off_phy;
657 err = reset_control_deassert(rockchip->mgmt_rst);
659 dev_err(dev, "deassert mgmt_rst err %d\n", err);
660 goto err_power_off_phy;
663 err = reset_control_deassert(rockchip->pipe_rst);
665 dev_err(dev, "deassert pipe_rst err %d\n", err);
666 goto err_power_off_phy;
669 /* Fix the transmitted FTS count desired to exit from L0s. */
670 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
671 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
672 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
673 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
675 rockchip_pcie_set_power_limit(rockchip);
677 /* Set RC's clock architecture as common clock */
678 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
679 status |= PCI_EXP_LNKSTA_SLC << 16;
680 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
682 /* Set RC's RCB to 128 */
683 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
684 status |= PCI_EXP_LNKCTL_RCB;
685 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
687 /* Enable Gen1 training */
688 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
691 gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
693 /* 500ms timeout value should be enough for Gen1/2 training */
694 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
695 status, PCIE_LINK_UP(status), 20,
696 500 * USEC_PER_MSEC);
698 dev_err(dev, "PCIe link training gen1 timeout!\n");
699 goto err_power_off_phy;
702 if (rockchip->link_gen == 2) {
704 * Enable retrain for gen2. This should be configured only after
707 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
708 status |= PCI_EXP_LNKCTL_RL;
709 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
711 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
712 status, PCIE_LINK_IS_GEN2(status), 20,
713 500 * USEC_PER_MSEC);
715 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
718 /* Check the final link width from negotiated lane counter from MGMT */
719 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
720 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
721 PCIE_CORE_PL_CONF_LANE_SHIFT);
722 dev_dbg(dev, "current link width is x%d\n", status);
724 /* Power off unused lane(s) */
725 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
726 for (i = 0; i < MAX_LANE_NUM; i++) {
727 if (!(rockchip->lanes_map & BIT(i))) {
728 dev_dbg(dev, "idling lane %d\n", i);
729 phy_power_off(rockchip->phys[i]);
733 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
734 PCIE_CORE_CONFIG_VENDOR);
735 rockchip_pcie_write(rockchip,
736 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
737 PCIE_RC_CONFIG_RID_CCR);
739 /* Clear THP cap's next cap pointer to remove L1 substate cap */
740 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
741 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
742 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
744 /* Clear L0s from RC's link cap */
745 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
746 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
747 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
748 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
751 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR);
752 status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK;
753 status |= PCIE_RC_CONFIG_DCSR_MPS_256;
754 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
759 phy_power_off(rockchip->phys[i]);
763 phy_exit(rockchip->phys[i]);
767 static void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
771 for (i = 0; i < MAX_LANE_NUM; i++) {
772 /* inactive lanes are already powered off */
773 if (rockchip->lanes_map & BIT(i))
774 phy_power_off(rockchip->phys[i]);
775 phy_exit(rockchip->phys[i]);
779 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
781 struct rockchip_pcie *rockchip = arg;
782 struct device *dev = rockchip->dev;
786 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
787 if (reg & PCIE_CLIENT_INT_LOCAL) {
788 dev_dbg(dev, "local interrupt received\n");
789 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
790 if (sub_reg & PCIE_CORE_INT_PRFPE)
791 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
793 if (sub_reg & PCIE_CORE_INT_CRFPE)
794 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
796 if (sub_reg & PCIE_CORE_INT_RRPE)
797 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
799 if (sub_reg & PCIE_CORE_INT_PRFO)
800 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
802 if (sub_reg & PCIE_CORE_INT_CRFO)
803 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
805 if (sub_reg & PCIE_CORE_INT_RT)
806 dev_dbg(dev, "replay timer timed out\n");
808 if (sub_reg & PCIE_CORE_INT_RTR)
809 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
811 if (sub_reg & PCIE_CORE_INT_PE)
812 dev_dbg(dev, "phy error detected on receive side\n");
814 if (sub_reg & PCIE_CORE_INT_MTR)
815 dev_dbg(dev, "malformed TLP received from the link\n");
817 if (sub_reg & PCIE_CORE_INT_UCR)
818 dev_dbg(dev, "malformed TLP received from the link\n");
820 if (sub_reg & PCIE_CORE_INT_FCE)
821 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
823 if (sub_reg & PCIE_CORE_INT_CT)
824 dev_dbg(dev, "a request timed out waiting for completion\n");
826 if (sub_reg & PCIE_CORE_INT_UTC)
827 dev_dbg(dev, "unmapped TC error\n");
829 if (sub_reg & PCIE_CORE_INT_MMVC)
830 dev_dbg(dev, "MSI mask register changes\n");
832 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
833 } else if (reg & PCIE_CLIENT_INT_PHY) {
834 dev_dbg(dev, "phy link changes\n");
835 rockchip_pcie_update_txcredit_mui(rockchip);
836 rockchip_pcie_clr_bw_int(rockchip);
839 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
840 PCIE_CLIENT_INT_STATUS);
845 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
847 struct rockchip_pcie *rockchip = arg;
848 struct device *dev = rockchip->dev;
851 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
852 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
853 dev_dbg(dev, "legacy done interrupt received\n");
855 if (reg & PCIE_CLIENT_INT_MSG)
856 dev_dbg(dev, "message done interrupt received\n");
858 if (reg & PCIE_CLIENT_INT_HOT_RST)
859 dev_dbg(dev, "hot reset interrupt received\n");
861 if (reg & PCIE_CLIENT_INT_DPA)
862 dev_dbg(dev, "dpa interrupt received\n");
864 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
865 dev_dbg(dev, "fatal error interrupt received\n");
867 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
868 dev_dbg(dev, "no fatal error interrupt received\n");
870 if (reg & PCIE_CLIENT_INT_CORR_ERR)
871 dev_dbg(dev, "correctable error interrupt received\n");
873 if (reg & PCIE_CLIENT_INT_PHY)
874 dev_dbg(dev, "phy interrupt received\n");
876 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
877 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
878 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
879 PCIE_CLIENT_INT_NFATAL_ERR |
880 PCIE_CLIENT_INT_CORR_ERR |
881 PCIE_CLIENT_INT_PHY),
882 PCIE_CLIENT_INT_STATUS);
887 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
889 struct irq_chip *chip = irq_desc_get_chip(desc);
890 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
891 struct device *dev = rockchip->dev;
896 chained_irq_enter(chip, desc);
898 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
899 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
902 hwirq = ffs(reg) - 1;
905 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
907 generic_handle_irq(virq);
909 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
912 chained_irq_exit(chip, desc);
915 static int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
917 struct device *dev = rockchip->dev;
922 phy = devm_phy_get(dev, "pcie-phy");
924 rockchip->legacy_phy = true;
925 rockchip->phys[0] = phy;
926 dev_warn(dev, "legacy phy model is deprecated!\n");
930 if (PTR_ERR(phy) == -EPROBE_DEFER)
933 dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");
935 for (i = 0; i < MAX_LANE_NUM; i++) {
936 name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);
940 phy = devm_of_phy_get(dev, dev->of_node, name);
944 if (PTR_ERR(phy) != -EPROBE_DEFER)
945 dev_err(dev, "missing phy for lane %d: %ld\n",
950 rockchip->phys[i] = phy;
956 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
959 struct device *dev = rockchip->dev;
960 struct platform_device *pdev = to_platform_device(dev);
962 irq = platform_get_irq_byname(pdev, "sys");
964 dev_err(dev, "missing sys IRQ resource\n");
968 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
969 IRQF_SHARED, "pcie-sys", rockchip);
971 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
975 irq = platform_get_irq_byname(pdev, "legacy");
977 dev_err(dev, "missing legacy IRQ resource\n");
981 irq_set_chained_handler_and_data(irq,
982 rockchip_pcie_legacy_int_handler,
985 irq = platform_get_irq_byname(pdev, "client");
987 dev_err(dev, "missing client IRQ resource\n");
991 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
992 IRQF_SHARED, "pcie-client", rockchip);
994 dev_err(dev, "failed to request PCIe client IRQ\n");
1002 * rockchip_pcie_parse_dt - Parse Device Tree
1003 * @rockchip: PCIe port information
1005 * Return: '0' on success and error value on failure
1007 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
1009 struct device *dev = rockchip->dev;
1010 struct platform_device *pdev = to_platform_device(dev);
1011 struct device_node *node = dev->of_node;
1012 struct resource *regs;
1015 regs = platform_get_resource_byname(pdev,
1018 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
1019 if (IS_ERR(rockchip->reg_base))
1020 return PTR_ERR(rockchip->reg_base);
1022 regs = platform_get_resource_byname(pdev,
1025 rockchip->apb_base = devm_ioremap_resource(dev, regs);
1026 if (IS_ERR(rockchip->apb_base))
1027 return PTR_ERR(rockchip->apb_base);
1029 err = rockchip_pcie_get_phys(rockchip);
1033 rockchip->lanes = 1;
1034 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
1035 if (!err && (rockchip->lanes == 0 ||
1036 rockchip->lanes == 3 ||
1037 rockchip->lanes > 4)) {
1038 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
1039 rockchip->lanes = 1;
1042 rockchip->link_gen = of_pci_get_max_link_speed(node);
1043 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
1044 rockchip->link_gen = 2;
1046 rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
1047 if (IS_ERR(rockchip->core_rst)) {
1048 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
1049 dev_err(dev, "missing core reset property in node\n");
1050 return PTR_ERR(rockchip->core_rst);
1053 rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
1054 if (IS_ERR(rockchip->mgmt_rst)) {
1055 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
1056 dev_err(dev, "missing mgmt reset property in node\n");
1057 return PTR_ERR(rockchip->mgmt_rst);
1060 rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
1062 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
1063 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
1064 dev_err(dev, "missing mgmt-sticky reset property in node\n");
1065 return PTR_ERR(rockchip->mgmt_sticky_rst);
1068 rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
1069 if (IS_ERR(rockchip->pipe_rst)) {
1070 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
1071 dev_err(dev, "missing pipe reset property in node\n");
1072 return PTR_ERR(rockchip->pipe_rst);
1075 rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
1076 if (IS_ERR(rockchip->pm_rst)) {
1077 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
1078 dev_err(dev, "missing pm reset property in node\n");
1079 return PTR_ERR(rockchip->pm_rst);
1082 rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
1083 if (IS_ERR(rockchip->pclk_rst)) {
1084 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
1085 dev_err(dev, "missing pclk reset property in node\n");
1086 return PTR_ERR(rockchip->pclk_rst);
1089 rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
1090 if (IS_ERR(rockchip->aclk_rst)) {
1091 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
1092 dev_err(dev, "missing aclk reset property in node\n");
1093 return PTR_ERR(rockchip->aclk_rst);
1096 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
1097 if (IS_ERR(rockchip->ep_gpio)) {
1098 dev_err(dev, "missing ep-gpios property in node\n");
1099 return PTR_ERR(rockchip->ep_gpio);
1102 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
1103 if (IS_ERR(rockchip->aclk_pcie)) {
1104 dev_err(dev, "aclk clock not found\n");
1105 return PTR_ERR(rockchip->aclk_pcie);
1108 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
1109 if (IS_ERR(rockchip->aclk_perf_pcie)) {
1110 dev_err(dev, "aclk_perf clock not found\n");
1111 return PTR_ERR(rockchip->aclk_perf_pcie);
1114 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
1115 if (IS_ERR(rockchip->hclk_pcie)) {
1116 dev_err(dev, "hclk clock not found\n");
1117 return PTR_ERR(rockchip->hclk_pcie);
1120 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
1121 if (IS_ERR(rockchip->clk_pcie_pm)) {
1122 dev_err(dev, "pm clock not found\n");
1123 return PTR_ERR(rockchip->clk_pcie_pm);
1126 err = rockchip_pcie_setup_irq(rockchip);
1130 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
1131 if (IS_ERR(rockchip->vpcie12v)) {
1132 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
1133 return PTR_ERR(rockchip->vpcie12v);
1134 dev_info(dev, "no vpcie12v regulator found\n");
1137 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
1138 if (IS_ERR(rockchip->vpcie3v3)) {
1139 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
1140 return PTR_ERR(rockchip->vpcie3v3);
1141 dev_info(dev, "no vpcie3v3 regulator found\n");
1144 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
1145 if (IS_ERR(rockchip->vpcie1v8)) {
1146 if (PTR_ERR(rockchip->vpcie1v8) != -ENODEV)
1147 return PTR_ERR(rockchip->vpcie1v8);
1148 dev_info(dev, "no vpcie1v8 regulator found\n");
1151 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
1152 if (IS_ERR(rockchip->vpcie0v9)) {
1153 if (PTR_ERR(rockchip->vpcie0v9) != -ENODEV)
1154 return PTR_ERR(rockchip->vpcie0v9);
1155 dev_info(dev, "no vpcie0v9 regulator found\n");
1161 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
1163 struct device *dev = rockchip->dev;
1166 if (!IS_ERR(rockchip->vpcie12v)) {
1167 err = regulator_enable(rockchip->vpcie12v);
1169 dev_err(dev, "fail to enable vpcie12v regulator\n");
1174 if (!IS_ERR(rockchip->vpcie3v3)) {
1175 err = regulator_enable(rockchip->vpcie3v3);
1177 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
1178 goto err_disable_12v;
1182 if (!IS_ERR(rockchip->vpcie1v8)) {
1183 err = regulator_enable(rockchip->vpcie1v8);
1185 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
1186 goto err_disable_3v3;
1190 if (!IS_ERR(rockchip->vpcie0v9)) {
1191 err = regulator_enable(rockchip->vpcie0v9);
1193 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
1194 goto err_disable_1v8;
1201 if (!IS_ERR(rockchip->vpcie1v8))
1202 regulator_disable(rockchip->vpcie1v8);
1204 if (!IS_ERR(rockchip->vpcie3v3))
1205 regulator_disable(rockchip->vpcie3v3);
1207 if (!IS_ERR(rockchip->vpcie12v))
1208 regulator_disable(rockchip->vpcie12v);
1213 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
1215 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
1216 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
1217 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
1218 PCIE_CORE_INT_MASK);
1220 rockchip_pcie_enable_bw_int(rockchip);
1223 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
1224 irq_hw_number_t hwirq)
1226 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
1227 irq_set_chip_data(irq, domain->host_data);
1232 static const struct irq_domain_ops intx_domain_ops = {
1233 .map = rockchip_pcie_intx_map,
1236 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
1238 struct device *dev = rockchip->dev;
1239 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
1242 dev_err(dev, "missing child interrupt-controller node\n");
1246 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
1247 &intx_domain_ops, rockchip);
1248 if (!rockchip->irq_domain) {
1249 dev_err(dev, "failed to get a INTx IRQ domain\n");
1256 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1257 int region_no, int type, u8 num_pass_bits,
1258 u32 lower_addr, u32 upper_addr)
1265 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1267 if (num_pass_bits + 1 < 8)
1269 if (num_pass_bits > 63)
1271 if (region_no == 0) {
1272 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1275 if (region_no != 0) {
1276 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1280 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1282 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1283 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1284 ob_addr_1 = upper_addr;
1285 ob_desc_0 = (1 << 23 | type);
1287 rockchip_pcie_write(rockchip, ob_addr_0,
1288 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1289 rockchip_pcie_write(rockchip, ob_addr_1,
1290 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1291 rockchip_pcie_write(rockchip, ob_desc_0,
1292 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1293 rockchip_pcie_write(rockchip, 0,
1294 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1299 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1300 int region_no, u8 num_pass_bits,
1301 u32 lower_addr, u32 upper_addr)
1307 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1309 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1311 if (num_pass_bits > 63)
1314 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1316 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1317 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1318 ib_addr_1 = upper_addr;
1320 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1321 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1326 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
1328 struct device *dev = rockchip->dev;
1333 rockchip_pcie_cfg_configuration_accesses(rockchip,
1334 AXI_WRAPPER_TYPE0_CFG);
1336 for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) {
1337 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1338 AXI_WRAPPER_MEM_WRITE,
1340 rockchip->mem_bus_addr +
1344 dev_err(dev, "program RC mem outbound ATU failed\n");
1349 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1351 dev_err(dev, "program RC mem inbound ATU failed\n");
1355 offset = rockchip->mem_size >> 20;
1356 for (reg_no = 0; reg_no < (rockchip->io_size >> 20); reg_no++) {
1357 err = rockchip_pcie_prog_ob_atu(rockchip,
1358 reg_no + 1 + offset,
1359 AXI_WRAPPER_IO_WRITE,
1361 rockchip->io_bus_addr +
1365 dev_err(dev, "program RC io outbound ATU failed\n");
1370 /* assign message regions */
1371 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
1372 AXI_WRAPPER_NOR_MSG,
1375 rockchip->msg_bus_addr = rockchip->mem_bus_addr +
1376 ((reg_no + offset) << 20);
1380 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
1385 /* send PME_TURN_OFF message */
1386 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
1388 /* read LTSSM and wait for falling into L2 link state */
1389 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
1390 value, PCIE_LINK_IS_L2(value), 20,
1391 jiffies_to_usecs(5 * HZ));
1393 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
1400 static int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
1402 struct device *dev = rockchip->dev;
1405 err = clk_prepare_enable(rockchip->aclk_pcie);
1407 dev_err(dev, "unable to enable aclk_pcie clock\n");
1411 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1413 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1414 goto err_aclk_perf_pcie;
1417 err = clk_prepare_enable(rockchip->hclk_pcie);
1419 dev_err(dev, "unable to enable hclk_pcie clock\n");
1423 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1425 dev_err(dev, "unable to enable clk_pcie_pm clock\n");
1426 goto err_clk_pcie_pm;
1432 clk_disable_unprepare(rockchip->hclk_pcie);
1434 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1436 clk_disable_unprepare(rockchip->aclk_pcie);
1440 static void rockchip_pcie_disable_clocks(void *data)
1442 struct rockchip_pcie *rockchip = data;
1444 clk_disable_unprepare(rockchip->clk_pcie_pm);
1445 clk_disable_unprepare(rockchip->hclk_pcie);
1446 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1447 clk_disable_unprepare(rockchip->aclk_pcie);
1450 static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev)
1452 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1455 /* disable core and cli int since we don't need to ack PME_ACK */
1456 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
1457 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK);
1458 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
1460 ret = rockchip_pcie_wait_l2(rockchip);
1462 rockchip_pcie_enable_interrupts(rockchip);
1466 rockchip_pcie_deinit_phys(rockchip);
1468 rockchip_pcie_disable_clocks(rockchip);
1470 if (!IS_ERR(rockchip->vpcie0v9))
1471 regulator_disable(rockchip->vpcie0v9);
1476 static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
1478 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1481 if (!IS_ERR(rockchip->vpcie0v9)) {
1482 err = regulator_enable(rockchip->vpcie0v9);
1484 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
1489 err = rockchip_pcie_enable_clocks(rockchip);
1491 goto err_disable_0v9;
1493 err = rockchip_pcie_init_port(rockchip);
1495 goto err_pcie_resume;
1497 err = rockchip_pcie_cfg_atu(rockchip);
1499 goto err_err_deinit_port;
1501 /* Need this to enter L1 again */
1502 rockchip_pcie_update_txcredit_mui(rockchip);
1503 rockchip_pcie_enable_interrupts(rockchip);
1507 err_err_deinit_port:
1508 rockchip_pcie_deinit_phys(rockchip);
1510 rockchip_pcie_disable_clocks(rockchip);
1512 if (!IS_ERR(rockchip->vpcie0v9))
1513 regulator_disable(rockchip->vpcie0v9);
1517 static int rockchip_pcie_probe(struct platform_device *pdev)
1519 struct rockchip_pcie *rockchip;
1520 struct device *dev = &pdev->dev;
1521 struct pci_bus *bus, *child;
1522 struct pci_host_bridge *bridge;
1523 struct resource_entry *win;
1524 resource_size_t io_base;
1525 struct resource *mem;
1526 struct resource *io;
1534 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
1538 rockchip = pci_host_bridge_priv(bridge);
1540 platform_set_drvdata(pdev, rockchip);
1541 rockchip->dev = dev;
1543 err = rockchip_pcie_parse_dt(rockchip);
1547 err = rockchip_pcie_enable_clocks(rockchip);
1551 err = rockchip_pcie_set_vpcie(rockchip);
1553 dev_err(dev, "failed to set vpcie regulator\n");
1557 err = rockchip_pcie_init_port(rockchip);
1561 rockchip_pcie_enable_interrupts(rockchip);
1563 err = rockchip_pcie_init_irq_domain(rockchip);
1565 goto err_deinit_port;
1567 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1570 goto err_remove_irq_domain;
1572 err = devm_request_pci_bus_resources(dev, &res);
1576 /* Get the I/O and memory ranges from DT */
1577 resource_list_for_each_entry(win, &res) {
1578 switch (resource_type(win->res)) {
1582 rockchip->io_size = resource_size(io);
1583 rockchip->io_bus_addr = io->start - win->offset;
1584 err = pci_remap_iospace(io, io_base);
1586 dev_warn(dev, "error %d: failed to map resource %pR\n",
1592 case IORESOURCE_MEM:
1595 rockchip->mem_size = resource_size(mem);
1596 rockchip->mem_bus_addr = mem->start - win->offset;
1598 case IORESOURCE_BUS:
1599 rockchip->root_bus_nr = win->res->start;
1606 err = rockchip_pcie_cfg_atu(rockchip);
1608 goto err_unmap_iospace;
1610 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
1611 if (!rockchip->msg_region) {
1613 goto err_unmap_iospace;
1616 list_splice_init(&res, &bridge->windows);
1617 bridge->dev.parent = dev;
1618 bridge->sysdata = rockchip;
1620 bridge->ops = &rockchip_pcie_ops;
1621 bridge->map_irq = of_irq_parse_and_map_pci;
1622 bridge->swizzle_irq = pci_common_swizzle;
1624 err = pci_scan_root_bus_bridge(bridge);
1626 goto err_unmap_iospace;
1630 rockchip->root_bus = bus;
1632 pci_bus_size_bridges(bus);
1633 pci_bus_assign_resources(bus);
1634 list_for_each_entry(child, &bus->children, node)
1635 pcie_bus_configure_settings(child);
1637 pci_bus_add_devices(bus);
1641 pci_unmap_iospace(rockchip->io);
1643 pci_free_resource_list(&res);
1644 err_remove_irq_domain:
1645 irq_domain_remove(rockchip->irq_domain);
1647 rockchip_pcie_deinit_phys(rockchip);
1649 if (!IS_ERR(rockchip->vpcie12v))
1650 regulator_disable(rockchip->vpcie12v);
1651 if (!IS_ERR(rockchip->vpcie3v3))
1652 regulator_disable(rockchip->vpcie3v3);
1653 if (!IS_ERR(rockchip->vpcie1v8))
1654 regulator_disable(rockchip->vpcie1v8);
1655 if (!IS_ERR(rockchip->vpcie0v9))
1656 regulator_disable(rockchip->vpcie0v9);
1658 rockchip_pcie_disable_clocks(rockchip);
1662 static int rockchip_pcie_remove(struct platform_device *pdev)
1664 struct device *dev = &pdev->dev;
1665 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1667 pci_stop_root_bus(rockchip->root_bus);
1668 pci_remove_root_bus(rockchip->root_bus);
1669 pci_unmap_iospace(rockchip->io);
1670 irq_domain_remove(rockchip->irq_domain);
1672 rockchip_pcie_deinit_phys(rockchip);
1674 rockchip_pcie_disable_clocks(rockchip);
1676 if (!IS_ERR(rockchip->vpcie12v))
1677 regulator_disable(rockchip->vpcie12v);
1678 if (!IS_ERR(rockchip->vpcie3v3))
1679 regulator_disable(rockchip->vpcie3v3);
1680 if (!IS_ERR(rockchip->vpcie1v8))
1681 regulator_disable(rockchip->vpcie1v8);
1682 if (!IS_ERR(rockchip->vpcie0v9))
1683 regulator_disable(rockchip->vpcie0v9);
1688 static const struct dev_pm_ops rockchip_pcie_pm_ops = {
1689 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq,
1690 rockchip_pcie_resume_noirq)
1693 static const struct of_device_id rockchip_pcie_of_match[] = {
1694 { .compatible = "rockchip,rk3399-pcie", },
1697 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match);
1699 static struct platform_driver rockchip_pcie_driver = {
1701 .name = "rockchip-pcie",
1702 .of_match_table = rockchip_pcie_of_match,
1703 .pm = &rockchip_pcie_pm_ops,
1705 .probe = rockchip_pcie_probe,
1706 .remove = rockchip_pcie_remove,
1708 module_platform_driver(rockchip_pcie_driver);
1710 MODULE_AUTHOR("Rockchip Inc");
1711 MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
1712 MODULE_LICENSE("GPL v2");