2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
10 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
34 #define PCIECAR 0x000010
35 #define PCIECCTLR 0x000018
36 #define CONFIG_SEND_ENABLE (1 << 31)
37 #define TYPE0 (0 << 8)
38 #define TYPE1 (1 << 8)
39 #define PCIECDR 0x000020
40 #define PCIEMSR 0x000028
41 #define PCIEINTXR 0x000400
42 #define PCIEMSITXR 0x000840
44 /* Transfer control */
45 #define PCIETCTLR 0x02000
47 #define PCIETSTR 0x02004
48 #define DATA_LINK_ACTIVE 1
49 #define PCIEERRFR 0x02020
50 #define UNSUPPORTED_REQUEST (1 << 4)
51 #define PCIEMSIFR 0x02044
52 #define PCIEMSIALR 0x02048
54 #define PCIEMSIAUR 0x0204c
55 #define PCIEMSIIER 0x02050
57 /* root port address */
58 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
60 /* local address reg & mask */
61 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
62 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
63 #define LAM_PREFETCH (1 << 3)
64 #define LAM_64BIT (1 << 2)
65 #define LAR_ENABLE (1 << 1)
67 /* PCIe address reg & mask */
68 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
69 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
70 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
71 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
72 #define PAR_ENABLE (1 << 31)
73 #define IO_SPACE (1 << 8)
76 #define PCICONF(x) (0x010000 + ((x) * 0x4))
77 #define PMCAP(x) (0x010040 + ((x) * 0x4))
78 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
79 #define VCCAP(x) (0x010100 + ((x) * 0x4))
82 #define IDSETR1 0x011004
83 #define TLCTLR 0x011048
84 #define MACSR 0x011054
85 #define SPCHGFIN (1 << 4)
86 #define SPCHGFAIL (1 << 6)
87 #define SPCHGSUC (1 << 7)
88 #define LINK_SPEED (0xf << 16)
89 #define LINK_SPEED_2_5GTS (1 << 16)
90 #define LINK_SPEED_5_0GTS (2 << 16)
91 #define MACCTLR 0x011058
92 #define SPEED_CHANGE (1 << 24)
93 #define SCRAMBLE_DISABLE (1 << 27)
94 #define MACS2R 0x011078
95 #define MACCGSPSETR 0x011084
96 #define SPCNGRSN (1 << 31)
99 #define H1_PCIEPHYADRR 0x04000c
100 #define WRITE_CMD (1 << 16)
101 #define PHY_ACK (1 << 24)
105 #define H1_PCIEPHYDOUTR 0x040014
106 #define H1_PCIEPHYSR 0x040018
109 #define GEN2_PCIEPHYADDR 0x780
110 #define GEN2_PCIEPHYDATA 0x784
111 #define GEN2_PCIEPHYCTRL 0x78c
113 #define INT_PCI_MSI_NR 32
115 #define RCONF(x) (PCICONF(0)+(x))
116 #define RPMCAP(x) (PMCAP(0)+(x))
117 #define REXPCAP(x) (EXPCAP(0)+(x))
118 #define RVCCAP(x) (VCCAP(0)+(x))
120 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
121 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
122 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
124 #define RCAR_PCI_MAX_RESOURCES 4
125 #define MAX_NR_INBOUND_MAPS 6
128 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
129 struct irq_domain *domain;
130 struct msi_controller chip;
137 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
139 return container_of(chip, struct rcar_msi, chip);
142 /* Structure representing the PCIe interface */
146 struct list_head resources;
153 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
156 writel(val, pcie->base + reg);
159 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
162 return readl(pcie->base + reg);
166 RCAR_PCI_ACCESS_READ,
167 RCAR_PCI_ACCESS_WRITE,
170 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
175 val &= ~(mask << shift);
176 val |= data << shift;
177 rcar_pci_write_reg(pcie, val, where & ~3);
180 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
182 int shift = 8 * (where & 3);
183 u32 val = rcar_pci_read_reg(pcie, where & ~3);
188 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
189 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
190 unsigned char access_type, struct pci_bus *bus,
191 unsigned int devfn, int where, u32 *data)
193 int dev, func, reg, index;
195 dev = PCI_SLOT(devfn);
196 func = PCI_FUNC(devfn);
201 * While each channel has its own memory-mapped extended config
202 * space, it's generally only accessible when in endpoint mode.
203 * When in root complex mode, the controller is unable to target
204 * itself with either type 0 or type 1 accesses, and indeed, any
205 * controller initiated target transfer to its own config space
206 * result in a completer abort.
208 * Each channel effectively only supports a single device, but as
209 * the same channel <-> device access works for any PCI_SLOT()
210 * value, we cheat a bit here and bind the controller's config
211 * space to devfn 0 in order to enable self-enumeration. In this
212 * case the regular ECAR/ECDR path is sidelined and the mangled
213 * config access itself is initiated as an internal bus transaction.
215 if (pci_is_root_bus(bus)) {
217 return PCIBIOS_DEVICE_NOT_FOUND;
219 if (access_type == RCAR_PCI_ACCESS_READ) {
220 *data = rcar_pci_read_reg(pcie, PCICONF(index));
222 /* Keep an eye out for changes to the root bus number */
223 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
224 pcie->root_bus_nr = *data & 0xff;
226 rcar_pci_write_reg(pcie, *data, PCICONF(index));
229 return PCIBIOS_SUCCESSFUL;
232 if (pcie->root_bus_nr < 0)
233 return PCIBIOS_DEVICE_NOT_FOUND;
236 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
238 /* Set the PIO address */
239 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
240 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
242 /* Enable the configuration access */
243 if (bus->parent->number == pcie->root_bus_nr)
244 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
246 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
248 /* Check for errors */
249 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
250 return PCIBIOS_DEVICE_NOT_FOUND;
252 /* Check for master and target aborts */
253 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
254 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
255 return PCIBIOS_DEVICE_NOT_FOUND;
257 if (access_type == RCAR_PCI_ACCESS_READ)
258 *data = rcar_pci_read_reg(pcie, PCIECDR);
260 rcar_pci_write_reg(pcie, *data, PCIECDR);
262 /* Disable the configuration access */
263 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
265 return PCIBIOS_SUCCESSFUL;
268 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
269 int where, int size, u32 *val)
271 struct rcar_pcie *pcie = bus->sysdata;
274 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
275 bus, devfn, where, val);
276 if (ret != PCIBIOS_SUCCESSFUL) {
282 *val = (*val >> (8 * (where & 3))) & 0xff;
284 *val = (*val >> (8 * (where & 2))) & 0xffff;
286 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
287 bus->number, devfn, where, size, (unsigned long)*val);
292 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
293 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
294 int where, int size, u32 val)
296 struct rcar_pcie *pcie = bus->sysdata;
300 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
301 bus, devfn, where, &data);
302 if (ret != PCIBIOS_SUCCESSFUL)
305 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
306 bus->number, devfn, where, size, (unsigned long)val);
309 shift = 8 * (where & 3);
310 data &= ~(0xff << shift);
311 data |= ((val & 0xff) << shift);
312 } else if (size == 2) {
313 shift = 8 * (where & 2);
314 data &= ~(0xffff << shift);
315 data |= ((val & 0xffff) << shift);
319 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
320 bus, devfn, where, &data);
325 static struct pci_ops rcar_pcie_ops = {
326 .read = rcar_pcie_read_conf,
327 .write = rcar_pcie_write_conf,
330 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
331 struct resource_entry *window)
333 /* Setup PCIe address space mappings for each resource */
334 resource_size_t size;
335 resource_size_t res_start;
336 struct resource *res = window->res;
339 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
342 * The PAMR mask is calculated in units of 128Bytes, which
343 * keeps things pretty simple.
345 size = resource_size(res);
346 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
347 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
349 if (res->flags & IORESOURCE_IO)
350 res_start = pci_pio_to_address(res->start) - window->offset;
352 res_start = res->start - window->offset;
354 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
355 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
358 /* First resource is for IO */
360 if (res->flags & IORESOURCE_IO)
363 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
366 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
368 struct resource_entry *win;
371 /* Setup PCI resources */
372 resource_list_for_each_entry(win, &pci->resources) {
373 struct resource *res = win->res;
378 switch (resource_type(res)) {
381 rcar_pcie_setup_window(i, pci, win);
385 pci->root_bus_nr = res->start;
391 pci_add_resource(resource, res);
397 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
399 struct device *dev = pcie->dev;
400 unsigned int timeout = 1000;
403 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
406 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
407 dev_err(dev, "Speed change already in progress\n");
411 macsr = rcar_pci_read_reg(pcie, MACSR);
412 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
415 /* Set target link speed to 5.0 GT/s */
416 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
417 PCI_EXP_LNKSTA_CLS_5_0GB);
419 /* Set speed change reason as intentional factor */
420 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
422 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
423 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
424 rcar_pci_write_reg(pcie, macsr, MACSR);
426 /* Start link speed change */
427 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
430 macsr = rcar_pci_read_reg(pcie, MACSR);
431 if (macsr & SPCHGFIN) {
432 /* Clear the interrupt bits */
433 rcar_pci_write_reg(pcie, macsr, MACSR);
435 if (macsr & SPCHGFAIL)
436 dev_err(dev, "Speed change failed\n");
444 dev_err(dev, "Speed change timed out\n");
447 dev_info(dev, "Current link speed is %s GT/s\n",
448 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
451 static int rcar_pcie_enable(struct rcar_pcie *pcie)
453 struct device *dev = pcie->dev;
454 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
455 struct pci_bus *bus, *child;
458 /* Try setting 5 GT/s link speed */
459 rcar_pcie_force_speedup(pcie);
461 rcar_pcie_setup(&bridge->windows, pcie);
463 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
465 bridge->dev.parent = dev;
466 bridge->sysdata = pcie;
467 bridge->busnr = pcie->root_bus_nr;
468 bridge->ops = &rcar_pcie_ops;
469 bridge->map_irq = of_irq_parse_and_map_pci;
470 bridge->swizzle_irq = pci_common_swizzle;
471 if (IS_ENABLED(CONFIG_PCI_MSI))
472 bridge->msi = &pcie->msi.chip;
474 ret = pci_scan_root_bus_bridge(bridge);
480 pci_bus_size_bridges(bus);
481 pci_bus_assign_resources(bus);
483 list_for_each_entry(child, &bus->children, node)
484 pcie_bus_configure_settings(child);
486 pci_bus_add_devices(bus);
491 static int phy_wait_for_ack(struct rcar_pcie *pcie)
493 struct device *dev = pcie->dev;
494 unsigned int timeout = 100;
497 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
503 dev_err(dev, "Access to PCIe phy timed out\n");
508 static void phy_write_reg(struct rcar_pcie *pcie,
509 unsigned int rate, unsigned int addr,
510 unsigned int lane, unsigned int data)
512 unsigned long phyaddr;
514 phyaddr = WRITE_CMD |
515 ((rate & 1) << RATE_POS) |
516 ((lane & 0xf) << LANE_POS) |
517 ((addr & 0xff) << ADR_POS);
520 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
521 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
523 /* Ignore errors as they will be dealt with if the data link is down */
524 phy_wait_for_ack(pcie);
527 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
528 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
530 /* Ignore errors as they will be dealt with if the data link is down */
531 phy_wait_for_ack(pcie);
534 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
536 unsigned int timeout = 10;
539 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
548 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
552 /* Begin initialization */
553 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
556 rcar_pci_write_reg(pcie, 1, PCIEMSR);
559 * Initial header for port config space is type 1, set the device
560 * class to match. Hardware takes care of propagating the IDSETR
561 * settings, so there is no need to bother with a quirk.
563 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
566 * Setup Secondary Bus Number & Subordinate Bus Number, even though
567 * they aren't used, to avoid bridge being detected as broken.
569 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
570 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
572 /* Initialize default capabilities. */
573 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
574 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
575 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
576 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
577 PCI_HEADER_TYPE_BRIDGE);
579 /* Enable data link layer active state reporting */
580 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
581 PCI_EXP_LNKCAP_DLLLARC);
583 /* Write out the physical slot number = 0 */
584 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
586 /* Set the completion timer timeout to the maximum 50ms. */
587 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
589 /* Terminate list of capabilities (Next Capability Offset=0) */
590 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
593 if (IS_ENABLED(CONFIG_PCI_MSI))
594 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
596 /* Finish initialization - establish a PCI Express link */
597 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
599 /* This will timeout if we don't have a link. */
600 err = rcar_pcie_wait_for_dl(pcie);
604 /* Enable INTx interrupts */
605 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
612 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
614 unsigned int timeout = 10;
616 /* Initialize the phy */
617 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
618 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
619 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
620 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
621 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
622 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
623 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
624 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
625 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
626 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
627 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
628 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
630 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
631 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
632 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
635 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
636 return rcar_pcie_hw_init(pcie);
644 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
647 * These settings come from the R-Car Series, 2nd Generation User's
648 * Manual, section 50.3.1 (2) Initialization of the physical layer.
650 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
651 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
652 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
653 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
655 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
656 /* The following value is for DC connection, no termination resistor */
657 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
658 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
659 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
661 return rcar_pcie_hw_init(pcie);
664 static int rcar_msi_alloc(struct rcar_msi *chip)
668 mutex_lock(&chip->lock);
670 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
671 if (msi < INT_PCI_MSI_NR)
672 set_bit(msi, chip->used);
676 mutex_unlock(&chip->lock);
681 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
685 mutex_lock(&chip->lock);
686 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
687 order_base_2(no_irqs));
688 mutex_unlock(&chip->lock);
693 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
695 mutex_lock(&chip->lock);
696 clear_bit(irq, chip->used);
697 mutex_unlock(&chip->lock);
700 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
702 struct rcar_pcie *pcie = data;
703 struct rcar_msi *msi = &pcie->msi;
704 struct device *dev = pcie->dev;
707 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
709 /* MSI & INTx share an interrupt - we only handle MSI here */
714 unsigned int index = find_first_bit(®, 32);
717 /* clear the interrupt */
718 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
720 irq = irq_find_mapping(msi->domain, index);
722 if (test_bit(index, msi->used))
723 generic_handle_irq(irq);
725 dev_info(dev, "unhandled MSI\n");
727 /* Unknown MSI, just clear it */
728 dev_dbg(dev, "unexpected MSI\n");
731 /* see if there's any more pending in this vector */
732 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
738 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
739 struct msi_desc *desc)
741 struct rcar_msi *msi = to_rcar_msi(chip);
742 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
747 hwirq = rcar_msi_alloc(msi);
751 irq = irq_find_mapping(msi->domain, hwirq);
753 rcar_msi_free(msi, hwirq);
757 irq_set_msi_desc(irq, desc);
759 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
760 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
763 pci_write_msi_msg(irq, &msg);
768 static int rcar_msi_setup_irqs(struct msi_controller *chip,
769 struct pci_dev *pdev, int nvec, int type)
771 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
772 struct rcar_msi *msi = to_rcar_msi(chip);
773 struct msi_desc *desc;
779 /* MSI-X interrupts are not supported */
780 if (type == PCI_CAP_ID_MSIX)
783 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
784 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
786 hwirq = rcar_msi_alloc_region(msi, nvec);
790 irq = irq_find_mapping(msi->domain, hwirq);
794 for (i = 0; i < nvec; i++) {
796 * irq_create_mapping() called from rcar_pcie_probe() pre-
797 * allocates descs, so there is no need to allocate descs here.
798 * We can therefore assume that if irq_find_mapping() above
799 * returns non-zero, then the descs are also successfully
802 if (irq_set_msi_desc_off(irq, i, desc)) {
808 desc->nvec_used = nvec;
809 desc->msi_attrib.multiple = order_base_2(nvec);
811 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
812 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
815 pci_write_msi_msg(irq, &msg);
820 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
822 struct rcar_msi *msi = to_rcar_msi(chip);
823 struct irq_data *d = irq_get_irq_data(irq);
825 rcar_msi_free(msi, d->hwirq);
828 static struct irq_chip rcar_msi_irq_chip = {
829 .name = "R-Car PCIe MSI",
830 .irq_enable = pci_msi_unmask_irq,
831 .irq_disable = pci_msi_mask_irq,
832 .irq_mask = pci_msi_mask_irq,
833 .irq_unmask = pci_msi_unmask_irq,
836 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
837 irq_hw_number_t hwirq)
839 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
840 irq_set_chip_data(irq, domain->host_data);
845 static const struct irq_domain_ops msi_domain_ops = {
849 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
851 struct device *dev = pcie->dev;
852 struct rcar_msi *msi = &pcie->msi;
856 mutex_init(&msi->lock);
859 msi->chip.setup_irq = rcar_msi_setup_irq;
860 msi->chip.setup_irqs = rcar_msi_setup_irqs;
861 msi->chip.teardown_irq = rcar_msi_teardown_irq;
863 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
864 &msi_domain_ops, &msi->chip);
866 dev_err(dev, "failed to create IRQ domain\n");
870 for (i = 0; i < INT_PCI_MSI_NR; i++)
871 irq_create_mapping(msi->domain, i);
873 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
874 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
875 IRQF_SHARED | IRQF_NO_THREAD,
876 rcar_msi_irq_chip.name, pcie);
878 dev_err(dev, "failed to request IRQ: %d\n", err);
882 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
883 IRQF_SHARED | IRQF_NO_THREAD,
884 rcar_msi_irq_chip.name, pcie);
886 dev_err(dev, "failed to request IRQ: %d\n", err);
890 /* setup MSI data target */
891 msi->pages = __get_free_pages(GFP_KERNEL, 0);
896 base = virt_to_phys((void *)msi->pages);
898 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
899 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
901 /* enable all MSI interrupts */
902 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
907 irq_domain_remove(msi->domain);
911 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
913 struct device *dev = pcie->dev;
917 err = of_address_to_resource(dev->of_node, 0, &res);
921 pcie->base = devm_ioremap_resource(dev, &res);
922 if (IS_ERR(pcie->base))
923 return PTR_ERR(pcie->base);
925 pcie->clk = devm_clk_get(dev, "pcie");
926 if (IS_ERR(pcie->clk)) {
927 dev_err(dev, "cannot get platform clock\n");
928 return PTR_ERR(pcie->clk);
930 err = clk_prepare_enable(pcie->clk);
934 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
935 if (IS_ERR(pcie->bus_clk)) {
936 dev_err(dev, "cannot get pcie bus clock\n");
937 err = PTR_ERR(pcie->bus_clk);
940 err = clk_prepare_enable(pcie->bus_clk);
944 i = irq_of_parse_and_map(dev->of_node, 0);
946 dev_err(dev, "cannot get platform resources for msi interrupt\n");
952 i = irq_of_parse_and_map(dev->of_node, 1);
954 dev_err(dev, "cannot get platform resources for msi interrupt\n");
963 clk_disable_unprepare(pcie->bus_clk);
965 clk_disable_unprepare(pcie->clk);
970 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
971 struct of_pci_range *range,
974 u64 restype = range->flags;
975 u64 cpu_addr = range->cpu_addr;
976 u64 cpu_end = range->cpu_addr + range->size;
977 u64 pci_addr = range->pci_addr;
978 u32 flags = LAM_64BIT | LAR_ENABLE;
983 if (restype & IORESOURCE_PREFETCH)
984 flags |= LAM_PREFETCH;
987 * If the size of the range is larger than the alignment of the start
988 * address, we have to use multiple entries to perform the mapping.
991 unsigned long nr_zeros = __ffs64(cpu_addr);
992 u64 alignment = 1ULL << nr_zeros;
994 size = min(range->size, alignment);
998 /* Hardware supports max 4GiB inbound region */
999 size = min(size, 1ULL << 32);
1001 mask = roundup_pow_of_two(size) - 1;
1004 while (cpu_addr < cpu_end) {
1006 * Set up 64-bit inbound regions as the range parser doesn't
1007 * distinguish between 32 and 64-bit types.
1009 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1011 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1012 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1015 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1017 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1019 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1025 if (idx > MAX_NR_INBOUND_MAPS) {
1026 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1035 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
1036 struct device_node *node)
1038 const int na = 3, ns = 2;
1041 parser->node = node;
1042 parser->pna = of_n_addr_cells(node);
1043 parser->np = parser->pna + na + ns;
1045 parser->range = of_get_property(node, "dma-ranges", &rlen);
1049 parser->end = parser->range + rlen / sizeof(__be32);
1053 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1054 struct device_node *np)
1056 struct of_pci_range range;
1057 struct of_pci_range_parser parser;
1061 if (pci_dma_range_parser_init(&parser, np))
1064 /* Get the dma-ranges from DT */
1065 for_each_of_pci_range(&parser, &range) {
1066 u64 end = range.cpu_addr + range.size - 1;
1068 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1069 range.flags, range.cpu_addr, end, range.pci_addr);
1071 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1079 static const struct of_device_id rcar_pcie_of_match[] = {
1080 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
1081 { .compatible = "renesas,pcie-r8a7790",
1082 .data = rcar_pcie_hw_init_gen2 },
1083 { .compatible = "renesas,pcie-r8a7791",
1084 .data = rcar_pcie_hw_init_gen2 },
1085 { .compatible = "renesas,pcie-rcar-gen2",
1086 .data = rcar_pcie_hw_init_gen2 },
1087 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
1088 { .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init },
1092 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
1095 struct device *dev = pci->dev;
1096 struct device_node *np = dev->of_node;
1097 resource_size_t iobase;
1098 struct resource_entry *win, *tmp;
1100 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
1105 err = devm_request_pci_bus_resources(dev, &pci->resources);
1107 goto out_release_res;
1109 resource_list_for_each_entry_safe(win, tmp, &pci->resources) {
1110 struct resource *res = win->res;
1112 if (resource_type(res) == IORESOURCE_IO) {
1113 err = devm_pci_remap_iospace(dev, res, iobase);
1115 dev_warn(dev, "error %d: failed to map resource %pR\n",
1118 resource_list_destroy_entry(win);
1126 pci_free_resource_list(&pci->resources);
1130 static int rcar_pcie_probe(struct platform_device *pdev)
1132 struct device *dev = &pdev->dev;
1133 struct rcar_pcie *pcie;
1136 int (*hw_init_fn)(struct rcar_pcie *);
1137 struct pci_host_bridge *bridge;
1139 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1143 pcie = pci_host_bridge_priv(bridge);
1147 INIT_LIST_HEAD(&pcie->resources);
1149 err = rcar_pcie_parse_request_of_pci_ranges(pcie);
1151 goto err_free_bridge;
1153 err = rcar_pcie_get_resources(pcie);
1155 dev_err(dev, "failed to request resources: %d\n", err);
1156 goto err_free_resource_list;
1159 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1161 goto err_free_resource_list;
1163 pm_runtime_enable(dev);
1164 err = pm_runtime_get_sync(dev);
1166 dev_err(dev, "pm_runtime_get_sync failed\n");
1167 goto err_pm_disable;
1170 /* Failure to get a link might just be that no cards are inserted */
1171 hw_init_fn = of_device_get_match_data(dev);
1172 err = hw_init_fn(pcie);
1174 dev_info(dev, "PCIe link down\n");
1179 data = rcar_pci_read_reg(pcie, MACSR);
1180 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1182 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1183 err = rcar_pcie_enable_msi(pcie);
1186 "failed to enable MSI support: %d\n",
1192 err = rcar_pcie_enable(pcie);
1199 pm_runtime_put(dev);
1202 pm_runtime_disable(dev);
1204 err_free_resource_list:
1205 pci_free_resource_list(&pcie->resources);
1207 pci_free_host_bridge(bridge);
1212 static struct platform_driver rcar_pcie_driver = {
1214 .name = "rcar-pcie",
1215 .of_match_table = rcar_pcie_of_match,
1216 .suppress_bind_attrs = true,
1218 .probe = rcar_pcie_probe,
1220 builtin_platform_driver(rcar_pcie_driver);