2 * MediaTek PCIe host controller driver.
4 * Copyright (c) 2017 MediaTek Inc.
5 * Author: Ryder Lee <ryder.lee@mediatek.com>
6 * Honghui Zhang <honghui.zhang@mediatek.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/iopoll.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/kernel.h>
24 #include <linux/of_address.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/reset.h>
33 /* PCIe shared registers */
34 #define PCIE_SYS_CFG 0x00
35 #define PCIE_INT_ENABLE 0x0c
36 #define PCIE_CFG_ADDR 0x20
37 #define PCIE_CFG_DATA 0x24
39 /* PCIe per port registers */
40 #define PCIE_BAR0_SETUP 0x10
41 #define PCIE_CLASS 0x34
42 #define PCIE_LINK_STATUS 0x50
44 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
45 #define PCIE_PORT_PERST(x) BIT(1 + (x))
46 #define PCIE_PORT_LINKUP BIT(0)
47 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
49 #define PCIE_BAR_ENABLE BIT(0)
50 #define PCIE_REVISION_ID BIT(0)
51 #define PCIE_CLASS_CODE (0x60400 << 8)
52 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
53 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
54 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
55 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
56 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
57 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
58 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
59 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
61 /* MediaTek specific configuration registers */
62 #define PCIE_FTS_NUM 0x70c
63 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
64 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
66 #define PCIE_FC_CREDIT 0x73c
67 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
68 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
70 /* PCIe V2 share registers */
71 #define PCIE_SYS_CFG_V2 0x0
72 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
73 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
75 /* PCIe V2 per-port registers */
76 #define PCIE_MSI_VECTOR 0x0c0
77 #define PCIE_INT_MASK 0x420
78 #define INTX_MASK GENMASK(19, 16)
80 #define PCIE_INT_STATUS 0x424
81 #define MSI_STATUS BIT(23)
82 #define PCIE_IMSI_STATUS 0x42c
83 #define PCIE_IMSI_ADDR 0x430
84 #define MSI_MASK BIT(23)
85 #define MTK_MSI_IRQS_NUM 32
87 #define PCIE_AHB_TRANS_BASE0_L 0x438
88 #define PCIE_AHB_TRANS_BASE0_H 0x43c
89 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
90 #define PCIE_AXI_WINDOW0 0x448
91 #define WIN_ENABLE BIT(7)
93 /* PCIe V2 configuration transaction header */
94 #define PCIE_CFG_HEADER0 0x460
95 #define PCIE_CFG_HEADER1 0x464
96 #define PCIE_CFG_HEADER2 0x468
97 #define PCIE_CFG_WDATA 0x470
98 #define PCIE_APP_TLP_REQ 0x488
99 #define PCIE_CFG_RDATA 0x48c
100 #define APP_CFG_REQ BIT(0)
101 #define APP_CPL_STATUS GENMASK(7, 5)
103 #define CFG_WRRD_TYPE_0 4
107 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
108 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
109 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
110 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
111 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
112 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
113 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
114 #define CFG_HEADER_DW0(type, fmt) \
115 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
116 #define CFG_HEADER_DW1(where, size) \
117 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
118 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
119 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
120 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
122 #define PCIE_RST_CTRL 0x510
123 #define PCIE_PHY_RSTB BIT(0)
124 #define PCIE_PIPE_SRSTB BIT(1)
125 #define PCIE_MAC_SRSTB BIT(2)
126 #define PCIE_CRSTB BIT(3)
127 #define PCIE_PERSTB BIT(8)
128 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
129 #define PCIE_LINK_STATUS_V2 0x804
130 #define PCIE_PORT_LINKUP_V2 BIT(10)
132 struct mtk_pcie_port;
135 * struct mtk_pcie_soc - differentiate between host generations
136 * @has_msi: whether this host supports MSI interrupts or not
137 * @ops: pointer to configuration access functions
138 * @startup: pointer to controller setting functions
139 * @setup_irq: pointer to initialize IRQ functions
141 struct mtk_pcie_soc {
144 int (*startup)(struct mtk_pcie_port *port);
145 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
149 * struct mtk_pcie_port - PCIe port information
150 * @base: IO mapped register base
152 * @pcie: pointer to PCIe host info
153 * @reset: pointer to port reset control
154 * @sys_ck: pointer to transaction/data link layer clock
155 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
156 * and RC initiated MMIO access
157 * @axi_ck: pointer to application layer MMIO channel operating clock
158 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
159 * when pcie_mac_ck/pcie_pipe_ck is turned off
160 * @obff_ck: pointer to OBFF functional block operating clock
161 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
162 * @phy: pointer to PHY control block
165 * @irq_domain: legacy INTx IRQ domain
166 * @msi_domain: MSI IRQ domain
167 * @msi_irq_in_use: bit map for assigned MSI IRQ
169 struct mtk_pcie_port {
171 struct list_head list;
172 struct mtk_pcie *pcie;
173 struct reset_control *reset;
183 struct irq_domain *irq_domain;
184 struct irq_domain *msi_domain;
185 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
189 * struct mtk_pcie - PCIe host information
190 * @dev: pointer to PCIe device
191 * @base: IO mapped register base
192 * @free_ck: free-run reference clock
195 * @mem: non-prefetchable memory resource
197 * @offset: IO / Memory offset
198 * @ports: pointer to PCIe port information
199 * @soc: pointer to SoC-dependent operations
209 struct resource busn;
214 struct list_head ports;
215 const struct mtk_pcie_soc *soc;
218 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
220 struct device *dev = pcie->dev;
222 clk_disable_unprepare(pcie->free_ck);
224 if (dev->pm_domain) {
225 pm_runtime_put_sync(dev);
226 pm_runtime_disable(dev);
230 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
232 struct mtk_pcie *pcie = port->pcie;
233 struct device *dev = pcie->dev;
235 devm_iounmap(dev, port->base);
236 list_del(&port->list);
237 devm_kfree(dev, port);
240 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
242 struct mtk_pcie_port *port, *tmp;
244 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
245 phy_power_off(port->phy);
247 clk_disable_unprepare(port->pipe_ck);
248 clk_disable_unprepare(port->obff_ck);
249 clk_disable_unprepare(port->axi_ck);
250 clk_disable_unprepare(port->aux_ck);
251 clk_disable_unprepare(port->ahb_ck);
252 clk_disable_unprepare(port->sys_ck);
253 mtk_pcie_port_free(port);
256 mtk_pcie_subsys_powerdown(pcie);
259 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
264 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
265 !(val & APP_CFG_REQ), 10,
266 100 * USEC_PER_MSEC);
268 return PCIBIOS_SET_FAILED;
270 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
271 return PCIBIOS_SET_FAILED;
273 return PCIBIOS_SUCCESSFUL;
276 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
277 int where, int size, u32 *val)
281 /* Write PCIe configuration transaction header for Cfgrd */
282 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
283 port->base + PCIE_CFG_HEADER0);
284 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
285 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
286 port->base + PCIE_CFG_HEADER2);
288 /* Trigger h/w to transmit Cfgrd TLP */
289 tmp = readl(port->base + PCIE_APP_TLP_REQ);
291 writel(tmp, port->base + PCIE_APP_TLP_REQ);
293 /* Check completion status */
294 if (mtk_pcie_check_cfg_cpld(port))
295 return PCIBIOS_SET_FAILED;
297 /* Read cpld payload of Cfgrd */
298 *val = readl(port->base + PCIE_CFG_RDATA);
301 *val = (*val >> (8 * (where & 3))) & 0xff;
303 *val = (*val >> (8 * (where & 3))) & 0xffff;
305 return PCIBIOS_SUCCESSFUL;
308 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
309 int where, int size, u32 val)
311 /* Write PCIe configuration transaction header for Cfgwr */
312 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
313 port->base + PCIE_CFG_HEADER0);
314 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
315 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
316 port->base + PCIE_CFG_HEADER2);
318 /* Write Cfgwr data */
319 val = val << 8 * (where & 3);
320 writel(val, port->base + PCIE_CFG_WDATA);
322 /* Trigger h/w to transmit Cfgwr TLP */
323 val = readl(port->base + PCIE_APP_TLP_REQ);
325 writel(val, port->base + PCIE_APP_TLP_REQ);
327 /* Check completion status */
328 return mtk_pcie_check_cfg_cpld(port);
331 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
334 struct mtk_pcie *pcie = bus->sysdata;
335 struct mtk_pcie_port *port;
336 struct pci_dev *dev = NULL;
339 * Walk the bus hierarchy to get the devfn value
340 * of the port in the root bus.
342 while (bus && bus->number) {
348 list_for_each_entry(port, &pcie->ports, list)
349 if (port->slot == PCI_SLOT(devfn))
355 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
356 int where, int size, u32 *val)
358 struct mtk_pcie_port *port;
359 u32 bn = bus->number;
362 port = mtk_pcie_find_port(bus, devfn);
365 return PCIBIOS_DEVICE_NOT_FOUND;
368 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
375 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
376 int where, int size, u32 val)
378 struct mtk_pcie_port *port;
379 u32 bn = bus->number;
381 port = mtk_pcie_find_port(bus, devfn);
383 return PCIBIOS_DEVICE_NOT_FOUND;
385 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
388 static struct pci_ops mtk_pcie_ops_v2 = {
389 .read = mtk_pcie_config_read,
390 .write = mtk_pcie_config_write,
393 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
395 struct mtk_pcie *pcie = port->pcie;
396 struct resource *mem = &pcie->mem;
401 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
403 val = readl(pcie->base + PCIE_SYS_CFG_V2);
404 val |= PCIE_CSR_LTSSM_EN(port->slot) |
405 PCIE_CSR_ASPM_L1_EN(port->slot);
406 writel(val, pcie->base + PCIE_SYS_CFG_V2);
409 /* Assert all reset signals */
410 writel(0, port->base + PCIE_RST_CTRL);
413 * Enable PCIe link down reset, if link status changed from link up to
414 * link down, this will reset MAC control registers and configuration
417 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
419 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
420 val = readl(port->base + PCIE_RST_CTRL);
421 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
422 PCIE_MAC_SRSTB | PCIE_CRSTB;
423 writel(val, port->base + PCIE_RST_CTRL);
425 /* 100ms timeout value should be enough for Gen1/2 training */
426 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
427 !!(val & PCIE_PORT_LINKUP_V2), 20,
428 100 * USEC_PER_MSEC);
433 val = readl(port->base + PCIE_INT_MASK);
435 writel(val, port->base + PCIE_INT_MASK);
437 /* Set AHB to PCIe translation windows */
438 size = mem->end - mem->start;
439 val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
440 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
442 val = upper_32_bits(mem->start);
443 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
445 /* Set PCIe to AXI translation memory space.*/
446 val = fls(0xffffffff) | WIN_ENABLE;
447 writel(val, port->base + PCIE_AXI_WINDOW0);
452 static int mtk_pcie_msi_alloc(struct mtk_pcie_port *port)
456 msi = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
457 if (msi < MTK_MSI_IRQS_NUM)
458 set_bit(msi, port->msi_irq_in_use);
465 static void mtk_pcie_msi_free(struct mtk_pcie_port *port, unsigned long hwirq)
467 clear_bit(hwirq, port->msi_irq_in_use);
470 static int mtk_pcie_msi_setup_irq(struct msi_controller *chip,
471 struct pci_dev *pdev, struct msi_desc *desc)
473 struct mtk_pcie_port *port;
477 phys_addr_t msg_addr;
479 port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
483 hwirq = mtk_pcie_msi_alloc(port);
487 irq = irq_create_mapping(port->msi_domain, hwirq);
489 mtk_pcie_msi_free(port, hwirq);
493 chip->dev = &pdev->dev;
495 irq_set_msi_desc(irq, desc);
497 /* MT2712/MT7622 only support 32-bit MSI addresses */
498 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
500 msg.address_lo = lower_32_bits(msg_addr);
503 pci_write_msi_msg(irq, &msg);
508 static void mtk_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
510 struct pci_dev *pdev = to_pci_dev(chip->dev);
511 struct irq_data *d = irq_get_irq_data(irq);
512 irq_hw_number_t hwirq = irqd_to_hwirq(d);
513 struct mtk_pcie_port *port;
515 port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
519 irq_dispose_mapping(irq);
520 mtk_pcie_msi_free(port, hwirq);
523 static struct msi_controller mtk_pcie_msi_chip = {
524 .setup_irq = mtk_pcie_msi_setup_irq,
525 .teardown_irq = mtk_msi_teardown_irq,
528 static struct irq_chip mtk_msi_irq_chip = {
529 .name = "MTK PCIe MSI",
530 .irq_enable = pci_msi_unmask_irq,
531 .irq_disable = pci_msi_mask_irq,
532 .irq_mask = pci_msi_mask_irq,
533 .irq_unmask = pci_msi_unmask_irq,
536 static int mtk_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
537 irq_hw_number_t hwirq)
539 irq_set_chip_and_handler(irq, &mtk_msi_irq_chip, handle_simple_irq);
540 irq_set_chip_data(irq, domain->host_data);
545 static const struct irq_domain_ops msi_domain_ops = {
546 .map = mtk_pcie_msi_map,
549 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
552 phys_addr_t msg_addr;
554 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
555 val = lower_32_bits(msg_addr);
556 writel(val, port->base + PCIE_IMSI_ADDR);
558 val = readl(port->base + PCIE_INT_MASK);
560 writel(val, port->base + PCIE_INT_MASK);
563 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
564 irq_hw_number_t hwirq)
566 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
567 irq_set_chip_data(irq, domain->host_data);
572 static const struct irq_domain_ops intx_domain_ops = {
573 .map = mtk_pcie_intx_map,
576 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
577 struct device_node *node)
579 struct device *dev = port->pcie->dev;
580 struct device_node *pcie_intc_node;
583 pcie_intc_node = of_get_next_child(node, NULL);
584 if (!pcie_intc_node) {
585 dev_err(dev, "no PCIe Intc node found\n");
589 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
590 &intx_domain_ops, port);
591 if (!port->irq_domain) {
592 dev_err(dev, "failed to get INTx IRQ domain\n");
596 if (IS_ENABLED(CONFIG_PCI_MSI)) {
597 port->msi_domain = irq_domain_add_linear(node, MTK_MSI_IRQS_NUM,
600 if (!port->msi_domain) {
601 dev_err(dev, "failed to create MSI IRQ domain\n");
604 mtk_pcie_enable_msi(port);
610 static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
612 struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
613 unsigned long status;
615 u32 bit = INTX_SHIFT;
617 while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
618 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
620 writel(1 << bit, port->base + PCIE_INT_STATUS);
621 virq = irq_find_mapping(port->irq_domain,
623 generic_handle_irq(virq);
627 if (IS_ENABLED(CONFIG_PCI_MSI)) {
628 while ((status = readl(port->base + PCIE_INT_STATUS)) & MSI_STATUS) {
629 unsigned long imsi_status;
631 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
632 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
634 writel(1 << bit, port->base + PCIE_IMSI_STATUS);
635 virq = irq_find_mapping(port->msi_domain, bit);
636 generic_handle_irq(virq);
639 /* Clear MSI interrupt status */
640 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
647 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
648 struct device_node *node)
650 struct mtk_pcie *pcie = port->pcie;
651 struct device *dev = pcie->dev;
652 struct platform_device *pdev = to_platform_device(dev);
655 irq = platform_get_irq(pdev, port->slot);
656 err = devm_request_irq(dev, irq, mtk_pcie_intr_handler,
657 IRQF_SHARED, "mtk-pcie", port);
659 dev_err(dev, "unable to request IRQ %d\n", irq);
663 err = mtk_pcie_init_irq_domain(port, node);
665 dev_err(dev, "failed to init PCIe IRQ domain\n");
672 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
673 unsigned int devfn, int where)
675 struct mtk_pcie *pcie = bus->sysdata;
677 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
678 bus->number), pcie->base + PCIE_CFG_ADDR);
680 return pcie->base + PCIE_CFG_DATA + (where & 3);
683 static struct pci_ops mtk_pcie_ops = {
684 .map_bus = mtk_pcie_map_bus,
685 .read = pci_generic_config_read,
686 .write = pci_generic_config_write,
689 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
691 struct mtk_pcie *pcie = port->pcie;
692 u32 func = PCI_FUNC(port->slot << 3);
693 u32 slot = PCI_SLOT(port->slot << 3);
697 /* assert port PERST_N */
698 val = readl(pcie->base + PCIE_SYS_CFG);
699 val |= PCIE_PORT_PERST(port->slot);
700 writel(val, pcie->base + PCIE_SYS_CFG);
702 /* de-assert port PERST_N */
703 val = readl(pcie->base + PCIE_SYS_CFG);
704 val &= ~PCIE_PORT_PERST(port->slot);
705 writel(val, pcie->base + PCIE_SYS_CFG);
707 /* 100ms timeout value should be enough for Gen1/2 training */
708 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
709 !!(val & PCIE_PORT_LINKUP), 20,
710 100 * USEC_PER_MSEC);
714 /* enable interrupt */
715 val = readl(pcie->base + PCIE_INT_ENABLE);
716 val |= PCIE_PORT_INT_EN(port->slot);
717 writel(val, pcie->base + PCIE_INT_ENABLE);
719 /* map to all DDR region. We need to set it before cfg operation. */
720 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
721 port->base + PCIE_BAR0_SETUP);
723 /* configure class code and revision ID */
724 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
726 /* configure FC credit */
727 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
728 pcie->base + PCIE_CFG_ADDR);
729 val = readl(pcie->base + PCIE_CFG_DATA);
730 val &= ~PCIE_FC_CREDIT_MASK;
731 val |= PCIE_FC_CREDIT_VAL(0x806c);
732 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
733 pcie->base + PCIE_CFG_ADDR);
734 writel(val, pcie->base + PCIE_CFG_DATA);
736 /* configure RC FTS number to 250 when it leaves L0s */
737 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
738 pcie->base + PCIE_CFG_ADDR);
739 val = readl(pcie->base + PCIE_CFG_DATA);
740 val &= ~PCIE_FTS_NUM_MASK;
741 val |= PCIE_FTS_NUM_L0(0x50);
742 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
743 pcie->base + PCIE_CFG_ADDR);
744 writel(val, pcie->base + PCIE_CFG_DATA);
749 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
751 struct mtk_pcie *pcie = port->pcie;
752 struct device *dev = pcie->dev;
755 err = clk_prepare_enable(port->sys_ck);
757 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
761 err = clk_prepare_enable(port->ahb_ck);
763 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
767 err = clk_prepare_enable(port->aux_ck);
769 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
773 err = clk_prepare_enable(port->axi_ck);
775 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
779 err = clk_prepare_enable(port->obff_ck);
781 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
785 err = clk_prepare_enable(port->pipe_ck);
787 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
791 reset_control_assert(port->reset);
792 reset_control_deassert(port->reset);
794 err = phy_init(port->phy);
796 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
800 err = phy_power_on(port->phy);
802 dev_err(dev, "failed to power on port%d phy\n", port->slot);
806 if (!pcie->soc->startup(port))
809 dev_info(dev, "Port%d link down\n", port->slot);
811 phy_power_off(port->phy);
815 clk_disable_unprepare(port->pipe_ck);
817 clk_disable_unprepare(port->obff_ck);
819 clk_disable_unprepare(port->axi_ck);
821 clk_disable_unprepare(port->aux_ck);
823 clk_disable_unprepare(port->ahb_ck);
825 clk_disable_unprepare(port->sys_ck);
827 mtk_pcie_port_free(port);
830 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
831 struct device_node *node,
834 struct mtk_pcie_port *port;
835 struct resource *regs;
836 struct device *dev = pcie->dev;
837 struct platform_device *pdev = to_platform_device(dev);
841 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
845 err = of_property_read_u32(node, "num-lanes", &port->lane);
847 dev_err(dev, "missing num-lanes property\n");
851 snprintf(name, sizeof(name), "port%d", slot);
852 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
853 port->base = devm_ioremap_resource(dev, regs);
854 if (IS_ERR(port->base)) {
855 dev_err(dev, "failed to map port%d base\n", slot);
856 return PTR_ERR(port->base);
859 snprintf(name, sizeof(name), "sys_ck%d", slot);
860 port->sys_ck = devm_clk_get(dev, name);
861 if (IS_ERR(port->sys_ck)) {
862 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
863 return PTR_ERR(port->sys_ck);
866 /* sys_ck might be divided into the following parts in some chips */
867 snprintf(name, sizeof(name), "ahb_ck%d", slot);
868 port->ahb_ck = devm_clk_get(dev, name);
869 if (IS_ERR(port->ahb_ck)) {
870 if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
871 return -EPROBE_DEFER;
876 snprintf(name, sizeof(name), "axi_ck%d", slot);
877 port->axi_ck = devm_clk_get(dev, name);
878 if (IS_ERR(port->axi_ck)) {
879 if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
880 return -EPROBE_DEFER;
885 snprintf(name, sizeof(name), "aux_ck%d", slot);
886 port->aux_ck = devm_clk_get(dev, name);
887 if (IS_ERR(port->aux_ck)) {
888 if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
889 return -EPROBE_DEFER;
894 snprintf(name, sizeof(name), "obff_ck%d", slot);
895 port->obff_ck = devm_clk_get(dev, name);
896 if (IS_ERR(port->obff_ck)) {
897 if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
898 return -EPROBE_DEFER;
900 port->obff_ck = NULL;
903 snprintf(name, sizeof(name), "pipe_ck%d", slot);
904 port->pipe_ck = devm_clk_get(dev, name);
905 if (IS_ERR(port->pipe_ck)) {
906 if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
907 return -EPROBE_DEFER;
909 port->pipe_ck = NULL;
912 snprintf(name, sizeof(name), "pcie-rst%d", slot);
913 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
914 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
915 return PTR_ERR(port->reset);
917 /* some platforms may use default PHY setting */
918 snprintf(name, sizeof(name), "pcie-phy%d", slot);
919 port->phy = devm_phy_optional_get(dev, name);
920 if (IS_ERR(port->phy))
921 return PTR_ERR(port->phy);
926 if (pcie->soc->setup_irq) {
927 err = pcie->soc->setup_irq(port, node);
932 INIT_LIST_HEAD(&port->list);
933 list_add_tail(&port->list, &pcie->ports);
938 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
940 struct device *dev = pcie->dev;
941 struct platform_device *pdev = to_platform_device(dev);
942 struct resource *regs;
945 /* get shared registers, which are optional */
946 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
948 pcie->base = devm_ioremap_resource(dev, regs);
949 if (IS_ERR(pcie->base)) {
950 dev_err(dev, "failed to map shared register\n");
951 return PTR_ERR(pcie->base);
955 pcie->free_ck = devm_clk_get(dev, "free_ck");
956 if (IS_ERR(pcie->free_ck)) {
957 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
958 return -EPROBE_DEFER;
960 pcie->free_ck = NULL;
963 if (dev->pm_domain) {
964 pm_runtime_enable(dev);
965 pm_runtime_get_sync(dev);
968 /* enable top level clock */
969 err = clk_prepare_enable(pcie->free_ck);
971 dev_err(dev, "failed to enable free_ck\n");
978 if (dev->pm_domain) {
979 pm_runtime_put_sync(dev);
980 pm_runtime_disable(dev);
986 static int mtk_pcie_setup(struct mtk_pcie *pcie)
988 struct device *dev = pcie->dev;
989 struct device_node *node = dev->of_node, *child;
990 struct of_pci_range_parser parser;
991 struct of_pci_range range;
993 struct mtk_pcie_port *port, *tmp;
996 if (of_pci_range_parser_init(&parser, node)) {
997 dev_err(dev, "missing \"ranges\" property\n");
1001 for_each_of_pci_range(&parser, &range) {
1002 err = of_pci_range_to_resource(&range, node, &res);
1006 switch (res.flags & IORESOURCE_TYPE_BITS) {
1008 pcie->offset.io = res.start - range.pci_addr;
1010 memcpy(&pcie->pio, &res, sizeof(res));
1011 pcie->pio.name = node->full_name;
1013 pcie->io.start = range.cpu_addr;
1014 pcie->io.end = range.cpu_addr + range.size - 1;
1015 pcie->io.flags = IORESOURCE_MEM;
1016 pcie->io.name = "I/O";
1018 memcpy(&res, &pcie->io, sizeof(res));
1021 case IORESOURCE_MEM:
1022 pcie->offset.mem = res.start - range.pci_addr;
1024 memcpy(&pcie->mem, &res, sizeof(res));
1025 pcie->mem.name = "non-prefetchable";
1030 err = of_pci_parse_bus_range(node, &pcie->busn);
1032 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
1033 pcie->busn.name = node->name;
1034 pcie->busn.start = 0;
1035 pcie->busn.end = 0xff;
1036 pcie->busn.flags = IORESOURCE_BUS;
1039 for_each_available_child_of_node(node, child) {
1042 err = of_pci_get_devfn(child);
1044 dev_err(dev, "failed to parse devfn: %d\n", err);
1045 goto error_put_node;
1048 slot = PCI_SLOT(err);
1050 err = mtk_pcie_parse_port(pcie, child, slot);
1052 goto error_put_node;
1055 err = mtk_pcie_subsys_powerup(pcie);
1059 /* enable each port, and then check link status */
1060 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1061 mtk_pcie_enable_port(port);
1063 /* power down PCIe subsys if slots are all empty (link down) */
1064 if (list_empty(&pcie->ports))
1065 mtk_pcie_subsys_powerdown(pcie);
1073 static int mtk_pcie_request_resources(struct mtk_pcie *pcie)
1075 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1076 struct list_head *windows = &host->windows;
1077 struct device *dev = pcie->dev;
1080 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
1081 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
1082 pci_add_resource(windows, &pcie->busn);
1084 err = devm_request_pci_bus_resources(dev, windows);
1088 pci_remap_iospace(&pcie->pio, pcie->io.start);
1093 static int mtk_pcie_register_host(struct pci_host_bridge *host)
1095 struct mtk_pcie *pcie = pci_host_bridge_priv(host);
1096 struct pci_bus *child;
1099 host->busnr = pcie->busn.start;
1100 host->dev.parent = pcie->dev;
1101 host->ops = pcie->soc->ops;
1102 host->map_irq = of_irq_parse_and_map_pci;
1103 host->swizzle_irq = pci_common_swizzle;
1104 host->sysdata = pcie;
1105 if (IS_ENABLED(CONFIG_PCI_MSI) && pcie->soc->has_msi)
1106 host->msi = &mtk_pcie_msi_chip;
1108 err = pci_scan_root_bus_bridge(host);
1112 pci_bus_size_bridges(host->bus);
1113 pci_bus_assign_resources(host->bus);
1115 list_for_each_entry(child, &host->bus->children, node)
1116 pcie_bus_configure_settings(child);
1118 pci_bus_add_devices(host->bus);
1123 static int mtk_pcie_probe(struct platform_device *pdev)
1125 struct device *dev = &pdev->dev;
1126 struct mtk_pcie *pcie;
1127 struct pci_host_bridge *host;
1130 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1134 pcie = pci_host_bridge_priv(host);
1137 pcie->soc = of_device_get_match_data(dev);
1138 platform_set_drvdata(pdev, pcie);
1139 INIT_LIST_HEAD(&pcie->ports);
1141 err = mtk_pcie_setup(pcie);
1145 err = mtk_pcie_request_resources(pcie);
1149 err = mtk_pcie_register_host(host);
1156 if (!list_empty(&pcie->ports))
1157 mtk_pcie_put_resources(pcie);
1162 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1163 .ops = &mtk_pcie_ops,
1164 .startup = mtk_pcie_startup_port,
1167 static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {
1169 .ops = &mtk_pcie_ops_v2,
1170 .startup = mtk_pcie_startup_port_v2,
1171 .setup_irq = mtk_pcie_setup_irq,
1174 static const struct of_device_id mtk_pcie_ids[] = {
1175 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1176 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1177 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 },
1178 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 },
1182 static struct platform_driver mtk_pcie_driver = {
1183 .probe = mtk_pcie_probe,
1186 .of_match_table = mtk_pcie_ids,
1187 .suppress_bind_attrs = true,
1190 builtin_platform_driver(mtk_pcie_driver);