2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
14 * Copyright (C) 2015 - 2016 Cavium, Inc.
17 #include <linux/bitfield.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of_address.h>
21 #include <linux/of_pci.h>
22 #include <linux/pci-acpi.h>
23 #include <linux/pci-ecam.h>
24 #include <linux/platform_device.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
28 #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
30 #define PEM_CFG_WR 0x28
31 #define PEM_CFG_RD 0x30
33 struct thunder_pem_pci {
35 void __iomem *pem_reg_base;
38 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
39 int where, int size, u32 *val)
41 u64 read_val, tmp_val;
42 struct pci_config_window *cfg = bus->sysdata;
43 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
45 if (devfn != 0 || where >= 2048) {
47 return PCIBIOS_DEVICE_NOT_FOUND;
51 * 32-bit accesses only. Write the address to the low order
52 * bits of PEM_CFG_RD, then trigger the read by reading back.
53 * The config data lands in the upper 32-bits of PEM_CFG_RD.
55 read_val = where & ~3ull;
56 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
57 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
61 * The config space contains some garbage, fix it up. Also
62 * synthesize an EA capability for the BAR used by MSI-X.
66 read_val &= 0xffff00ff;
67 read_val |= 0x00007000; /* Skip MSI CAP */
69 case 0x70: /* Express Cap */
71 * Change PME interrupt to vector 2 on T88 where it
72 * reads as 0, else leave it alone.
74 if (!(read_val & (0x1f << 25)))
75 read_val |= (2u << 25);
77 case 0xb0: /* MSI-X Cap */
78 /* TableSize=2 or 4, Next Cap is EA */
79 read_val &= 0xc00000ff;
81 * If Express Cap(0x70) raw PME vector reads as 0 we are on
82 * T88 and TableSize is reported as 4, else TableSize
85 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
86 tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
88 if (!(tmp_val & (0x1f << 25)))
89 read_val |= 0x0003bc00;
91 read_val |= 0x0001bc00;
94 /* Table offset=0, BIR=0 */
95 read_val = 0x00000000;
98 /* BPA offset=0xf0000, BIR=0 */
99 read_val = 0x000f0000;
102 /* EA, 1 entry, no next Cap */
103 read_val = 0x00010014;
107 read_val = 0x00000000;
110 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
111 read_val = 0x80ff0003;
114 read_val = pem_pci->ea_entry[0];
117 read_val = pem_pci->ea_entry[1];
120 read_val = pem_pci->ea_entry[2];
125 read_val >>= (8 * (where & 3));
137 return PCIBIOS_SUCCESSFUL;
140 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 *val)
143 struct pci_config_window *cfg = bus->sysdata;
145 if (bus->number < cfg->busr.start ||
146 bus->number > cfg->busr.end)
147 return PCIBIOS_DEVICE_NOT_FOUND;
150 * The first device on the bus is the PEM PCIe bridge.
151 * Special case its config access.
153 if (bus->number == cfg->busr.start)
154 return thunder_pem_bridge_read(bus, devfn, where, size, val);
156 return pci_generic_config_read(bus, devfn, where, size, val);
160 * Some of the w1c_bits below also include read-only or non-writable
161 * reserved bits, this makes the code simpler and is OK as the bits
162 * are not affected by writing zeros to them.
164 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
168 switch (where_aligned) {
169 case 0x04: /* Command/Status */
170 case 0x1c: /* Base and I/O Limit/Secondary Status */
171 w1c_bits = 0xff000000;
173 case 0x44: /* Power Management Control and Status */
174 w1c_bits = 0xfffffe00;
176 case 0x78: /* Device Control/Device Status */
177 case 0x80: /* Link Control/Link Status */
178 case 0x88: /* Slot Control/Slot Status */
179 case 0x90: /* Root Status */
180 case 0xa0: /* Link Control 2 Registers/Link Status 2 */
181 w1c_bits = 0xffff0000;
183 case 0x104: /* Uncorrectable Error Status */
184 case 0x110: /* Correctable Error Status */
185 case 0x130: /* Error Status */
186 case 0x160: /* Link Control 4 */
187 w1c_bits = 0xffffffff;
195 /* Some bits must be written to one so they appear to be read-only. */
196 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
200 switch (where_aligned) {
201 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
202 /* Force 32-bit I/O addressing. */
205 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
206 /* Force 64-bit addressing */
207 w1_bits = 0x00010001;
216 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
217 int where, int size, u32 val)
219 struct pci_config_window *cfg = bus->sysdata;
220 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
221 u64 write_val, read_val;
222 u64 where_aligned = where & ~3ull;
226 if (devfn != 0 || where >= 2048)
227 return PCIBIOS_DEVICE_NOT_FOUND;
230 * 32-bit accesses only. If the write is for a size smaller
231 * than 32-bits, we must first read the 32-bit value and merge
232 * in the desired bits and then write the whole 32-bits back
237 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
238 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
240 mask = ~(0xff << (8 * (where & 3)));
242 val = (val & 0xff) << (8 * (where & 3));
243 val |= (u32)read_val;
246 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
247 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
249 mask = ~(0xffff << (8 * (where & 3)));
251 val = (val & 0xffff) << (8 * (where & 3));
252 val |= (u32)read_val;
259 * By expanding the write width to 32 bits, we may
260 * inadvertently hit some W1C bits that were not intended to
261 * be written. Calculate the mask that must be applied to the
262 * data to be written to avoid these cases.
265 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
274 * Some bits must be read-only with value of one. Since the
275 * access method allows these to be cleared if a zero is
276 * written, force them to one before writing.
278 val |= thunder_pem_bridge_w1_bits(where_aligned);
281 * Low order bits are the config address, the high order 32
282 * bits are the data to be written.
284 write_val = (((u64)val) << 32) | where_aligned;
285 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
286 return PCIBIOS_SUCCESSFUL;
289 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
290 int where, int size, u32 val)
292 struct pci_config_window *cfg = bus->sysdata;
294 if (bus->number < cfg->busr.start ||
295 bus->number > cfg->busr.end)
296 return PCIBIOS_DEVICE_NOT_FOUND;
298 * The first device on the bus is the PEM PCIe bridge.
299 * Special case its config access.
301 if (bus->number == cfg->busr.start)
302 return thunder_pem_bridge_write(bus, devfn, where, size, val);
305 return pci_generic_config_write(bus, devfn, where, size, val);
308 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
309 struct resource *res_pem)
311 struct thunder_pem_pci *pem_pci;
312 resource_size_t bar4_start;
314 pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
318 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
319 if (!pem_pci->pem_reg_base)
323 * The MSI-X BAR for the PEM and AER interrupts is located at
324 * a fixed offset from the PEM register base. Generate a
325 * fragment of the synthesized Enhanced Allocation capability
326 * structure here for the BAR.
328 bar4_start = res_pem->start + 0xf00000;
329 pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
330 pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
331 pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
337 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
339 #define PEM_RES_BASE 0x87e0c0000000ULL
340 #define PEM_NODE_MASK GENMASK_ULL(45, 44)
341 #define PEM_INDX_MASK GENMASK_ULL(26, 24)
342 #define PEM_MIN_DOM_IN_NODE 4
343 #define PEM_MAX_DOM_IN_NODE 10
345 static void thunder_pem_reserve_range(struct device *dev, int seg,
348 resource_size_t start = r->start, end = r->end;
349 struct resource *res;
350 const char *regionid;
352 regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
356 res = request_mem_region(start, end - start + 1, regionid);
358 res->flags &= ~IORESOURCE_BUSY;
362 dev_info(dev, "%pR %s reserved\n", r,
363 res ? "has been" : "could not be");
366 static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
367 struct resource *res_pem)
369 int node = acpi_get_node(root->device->handle);
372 if (node == NUMA_NO_NODE)
375 index = root->segment - PEM_MIN_DOM_IN_NODE;
376 index -= node * PEM_MAX_DOM_IN_NODE;
377 res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
378 FIELD_PREP(PEM_INDX_MASK, index);
379 res_pem->flags = IORESOURCE_MEM;
382 static int thunder_pem_acpi_init(struct pci_config_window *cfg)
384 struct device *dev = cfg->parent;
385 struct acpi_device *adev = to_acpi_device(dev);
386 struct acpi_pci_root *root = acpi_driver_data(adev);
387 struct resource *res_pem;
390 res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
394 ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
397 * If we fail to gather resources it means that we run with old
398 * FW where we need to calculate PEM-specific resources manually.
401 thunder_pem_legacy_fw(root, res_pem);
403 * Reserve 64K size PEM specific resources. The full 16M range
404 * size is required for thunder_pem_init() call.
406 res_pem->end = res_pem->start + SZ_64K - 1;
407 thunder_pem_reserve_range(dev, root->segment, res_pem);
408 res_pem->end = res_pem->start + SZ_16M - 1;
410 /* Reserve PCI configuration space as well. */
411 thunder_pem_reserve_range(dev, root->segment, &cfg->res);
414 return thunder_pem_init(dev, cfg, res_pem);
417 struct pci_ecam_ops thunder_pem_ecam_ops = {
419 .init = thunder_pem_acpi_init,
421 .map_bus = pci_ecam_map_bus,
422 .read = thunder_pem_config_read,
423 .write = thunder_pem_config_write,
429 #ifdef CONFIG_PCI_HOST_THUNDER_PEM
431 static int thunder_pem_platform_init(struct pci_config_window *cfg)
433 struct device *dev = cfg->parent;
434 struct platform_device *pdev = to_platform_device(dev);
435 struct resource *res_pem;
441 * The second register range is the PEM bridge to the PCIe
442 * bus. It has a different config access method than those
443 * devices behind the bridge.
445 res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
447 dev_err(dev, "missing \"reg[1]\"property\n");
451 return thunder_pem_init(dev, cfg, res_pem);
454 static struct pci_ecam_ops pci_thunder_pem_ops = {
456 .init = thunder_pem_platform_init,
458 .map_bus = pci_ecam_map_bus,
459 .read = thunder_pem_config_read,
460 .write = thunder_pem_config_write,
464 static const struct of_device_id thunder_pem_of_match[] = {
465 { .compatible = "cavium,pci-host-thunder-pem" },
469 static int thunder_pem_probe(struct platform_device *pdev)
471 return pci_host_common_probe(pdev, &pci_thunder_pem_ops);
474 static struct platform_driver thunder_pem_driver = {
476 .name = KBUILD_MODNAME,
477 .of_match_table = thunder_pem_of_match,
478 .suppress_bind_attrs = true,
480 .probe = thunder_pem_probe,
482 builtin_platform_driver(thunder_pem_driver);