2 * PCIe host controller driver for Tegra SoCs
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
10 * Bits taken from arch/arm/mach-dove/pcie.c
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 #include <linux/clk.h>
28 #include <linux/debugfs.h>
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/irqdomain.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/msi.h>
37 #include <linux/of_address.h>
38 #include <linux/of_pci.h>
39 #include <linux/of_platform.h>
40 #include <linux/pci.h>
41 #include <linux/phy/phy.h>
42 #include <linux/platform_device.h>
43 #include <linux/reset.h>
44 #include <linux/sizes.h>
45 #include <linux/slab.h>
46 #include <linux/vmalloc.h>
47 #include <linux/regulator/consumer.h>
49 #include <soc/tegra/cpuidle.h>
50 #include <soc/tegra/pmc.h>
52 #include <asm/mach/irq.h>
53 #include <asm/mach/map.h>
54 #include <asm/mach/pci.h>
56 #define INT_PCI_MSI_NR (8 * 32)
58 /* register definitions */
60 #define AFI_AXI_BAR0_SZ 0x00
61 #define AFI_AXI_BAR1_SZ 0x04
62 #define AFI_AXI_BAR2_SZ 0x08
63 #define AFI_AXI_BAR3_SZ 0x0c
64 #define AFI_AXI_BAR4_SZ 0x10
65 #define AFI_AXI_BAR5_SZ 0x14
67 #define AFI_AXI_BAR0_START 0x18
68 #define AFI_AXI_BAR1_START 0x1c
69 #define AFI_AXI_BAR2_START 0x20
70 #define AFI_AXI_BAR3_START 0x24
71 #define AFI_AXI_BAR4_START 0x28
72 #define AFI_AXI_BAR5_START 0x2c
74 #define AFI_FPCI_BAR0 0x30
75 #define AFI_FPCI_BAR1 0x34
76 #define AFI_FPCI_BAR2 0x38
77 #define AFI_FPCI_BAR3 0x3c
78 #define AFI_FPCI_BAR4 0x40
79 #define AFI_FPCI_BAR5 0x44
81 #define AFI_CACHE_BAR0_SZ 0x48
82 #define AFI_CACHE_BAR0_ST 0x4c
83 #define AFI_CACHE_BAR1_SZ 0x50
84 #define AFI_CACHE_BAR1_ST 0x54
86 #define AFI_MSI_BAR_SZ 0x60
87 #define AFI_MSI_FPCI_BAR_ST 0x64
88 #define AFI_MSI_AXI_BAR_ST 0x68
90 #define AFI_MSI_VEC0 0x6c
91 #define AFI_MSI_VEC1 0x70
92 #define AFI_MSI_VEC2 0x74
93 #define AFI_MSI_VEC3 0x78
94 #define AFI_MSI_VEC4 0x7c
95 #define AFI_MSI_VEC5 0x80
96 #define AFI_MSI_VEC6 0x84
97 #define AFI_MSI_VEC7 0x88
99 #define AFI_MSI_EN_VEC0 0x8c
100 #define AFI_MSI_EN_VEC1 0x90
101 #define AFI_MSI_EN_VEC2 0x94
102 #define AFI_MSI_EN_VEC3 0x98
103 #define AFI_MSI_EN_VEC4 0x9c
104 #define AFI_MSI_EN_VEC5 0xa0
105 #define AFI_MSI_EN_VEC6 0xa4
106 #define AFI_MSI_EN_VEC7 0xa8
108 #define AFI_CONFIGURATION 0xac
109 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
111 #define AFI_FPCI_ERROR_MASKS 0xb0
113 #define AFI_INTR_MASK 0xb4
114 #define AFI_INTR_MASK_INT_MASK (1 << 0)
115 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
117 #define AFI_INTR_CODE 0xb8
118 #define AFI_INTR_CODE_MASK 0xf
119 #define AFI_INTR_INI_SLAVE_ERROR 1
120 #define AFI_INTR_INI_DECODE_ERROR 2
121 #define AFI_INTR_TARGET_ABORT 3
122 #define AFI_INTR_MASTER_ABORT 4
123 #define AFI_INTR_INVALID_WRITE 5
124 #define AFI_INTR_LEGACY 6
125 #define AFI_INTR_FPCI_DECODE_ERROR 7
126 #define AFI_INTR_AXI_DECODE_ERROR 8
127 #define AFI_INTR_FPCI_TIMEOUT 9
128 #define AFI_INTR_PE_PRSNT_SENSE 10
129 #define AFI_INTR_PE_CLKREQ_SENSE 11
130 #define AFI_INTR_CLKCLAMP_SENSE 12
131 #define AFI_INTR_RDY4PD_SENSE 13
132 #define AFI_INTR_P2P_ERROR 14
134 #define AFI_INTR_SIGNATURE 0xbc
135 #define AFI_UPPER_FPCI_ADDRESS 0xc0
136 #define AFI_SM_INTR_ENABLE 0xc4
137 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
138 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
139 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
140 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
141 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
142 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
143 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
144 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
146 #define AFI_AFI_INTR_ENABLE 0xc8
147 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
148 #define AFI_INTR_EN_INI_DECERR (1 << 1)
149 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
150 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
151 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
152 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
153 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
154 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
155 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
157 #define AFI_PCIE_CONFIG 0x0f8
158 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
159 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
160 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
161 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
162 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
163 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
164 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
165 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
166 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
167 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
169 #define AFI_FUSE 0x104
170 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
172 #define AFI_PEX0_CTRL 0x110
173 #define AFI_PEX1_CTRL 0x118
174 #define AFI_PEX2_CTRL 0x128
175 #define AFI_PEX_CTRL_RST (1 << 0)
176 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
177 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
178 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
180 #define AFI_PLLE_CONTROL 0x160
181 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
182 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
184 #define AFI_PEXBIAS_CTRL_0 0x168
186 #define RP_VEND_XP 0x00000F00
187 #define RP_VEND_XP_DL_UP (1 << 30)
189 #define RP_PRIV_MISC 0x00000FE0
190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
193 #define RP_LINK_CONTROL_STATUS 0x00000090
194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
197 #define PADS_CTL_SEL 0x0000009C
199 #define PADS_CTL 0x000000A0
200 #define PADS_CTL_IDDQ_1L (1 << 0)
201 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
202 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
204 #define PADS_PLL_CTL_TEGRA20 0x000000B8
205 #define PADS_PLL_CTL_TEGRA30 0x000000B4
206 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
207 #define PADS_PLL_CTL_LOCKDET (1 << 8)
208 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
209 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
210 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
211 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
212 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
213 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
214 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
215 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
217 #define PADS_REFCLK_CFG0 0x000000C8
218 #define PADS_REFCLK_CFG1 0x000000CC
219 #define PADS_REFCLK_BIAS 0x000000D0
222 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
223 * entries, one entry per PCIe port. These field definitions and desired
224 * values aren't in the TRM, but do come from NVIDIA.
226 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
227 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
228 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
229 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
231 /* Default value provided by HW engineering is 0xfa5c */
232 #define PADS_REFCLK_CFG_VALUE \
234 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
235 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
236 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
237 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
241 struct msi_controller chip;
242 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
243 struct irq_domain *domain;
249 /* used to differentiate between Tegra SoC generations */
250 struct tegra_pcie_soc_data {
251 unsigned int num_ports;
252 unsigned int msi_base_shift;
255 bool has_pex_clkreq_en;
256 bool has_pex_bias_ctrl;
257 bool has_intr_prsnt_sense;
262 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
264 return container_of(chip, struct tegra_msi, chip);
274 struct list_head buses;
281 struct resource prefetch;
282 struct resource busn;
289 struct reset_control *pex_rst;
290 struct reset_control *afi_rst;
291 struct reset_control *pcie_xrst;
295 struct tegra_msi msi;
297 struct list_head ports;
298 unsigned int num_ports;
301 struct regulator_bulk_data *supplies;
302 unsigned int num_supplies;
304 const struct tegra_pcie_soc_data *soc_data;
305 struct dentry *debugfs;
308 struct tegra_pcie_port {
309 struct tegra_pcie *pcie;
310 struct list_head list;
311 struct resource regs;
317 struct tegra_pcie_bus {
318 struct vm_struct *area;
319 struct list_head list;
323 static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
325 return sys->private_data;
328 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
329 unsigned long offset)
331 writel(value, pcie->afi + offset);
334 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
336 return readl(pcie->afi + offset);
339 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
340 unsigned long offset)
342 writel(value, pcie->pads + offset);
345 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
347 return readl(pcie->pads + offset);
351 * The configuration space mapping on Tegra is somewhat similar to the ECAM
352 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
353 * register accesses are mapped:
355 * [27:24] extended register number
357 * [15:11] device number
358 * [10: 8] function number
359 * [ 7: 0] register number
361 * Mapping the whole extended configuration space would require 256 MiB of
362 * virtual address space, only a small part of which will actually be used.
363 * To work around this, a 1 MiB of virtual addresses are allocated per bus
364 * when the bus is first accessed. When the physical range is mapped, the
365 * the bus number bits are hidden so that the extended register number bits
366 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
368 * [19:16] extended register number
369 * [15:11] device number
370 * [10: 8] function number
371 * [ 7: 0] register number
373 * This is achieved by stitching together 16 chunks of 64 KiB of physical
374 * address space via the MMU.
376 static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
378 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
379 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
382 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
385 pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
386 L_PTE_XN | L_PTE_MT_DEV_SHARED | L_PTE_SHARED);
387 phys_addr_t cs = pcie->cs->start;
388 struct tegra_pcie_bus *bus;
392 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
394 return ERR_PTR(-ENOMEM);
396 INIT_LIST_HEAD(&bus->list);
399 /* allocate 1 MiB of virtual addresses */
400 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
406 /* map each of the 16 chunks of 64 KiB each */
407 for (i = 0; i < 16; i++) {
408 unsigned long virt = (unsigned long)bus->area->addr +
410 phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
412 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
414 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
423 vunmap(bus->area->addr);
430 * Look up a virtual address mapping for the specified bus number. If no such
431 * mapping exists, try to create one.
433 static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
436 struct tegra_pcie_bus *bus;
438 list_for_each_entry(bus, &pcie->buses, list)
439 if (bus->nr == busnr)
440 return (void __iomem *)bus->area->addr;
442 bus = tegra_pcie_bus_alloc(pcie, busnr);
446 list_add_tail(&bus->list, &pcie->buses);
448 return (void __iomem *)bus->area->addr;
451 static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
455 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
456 void __iomem *addr = NULL;
458 if (bus->number == 0) {
459 unsigned int slot = PCI_SLOT(devfn);
460 struct tegra_pcie_port *port;
462 list_for_each_entry(port, &pcie->ports, list) {
463 if (port->index + 1 == slot) {
464 addr = port->base + (where & ~3);
469 addr = tegra_pcie_bus_map(pcie, bus->number);
472 "failed to map cfg. space for bus %u\n",
477 addr += tegra_pcie_conf_offset(devfn, where);
483 static struct pci_ops tegra_pcie_ops = {
484 .map_bus = tegra_pcie_conf_address,
485 .read = pci_generic_config_read32,
486 .write = pci_generic_config_write32,
489 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
491 unsigned long ret = 0;
493 switch (port->index) {
510 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
512 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
515 /* pulse reset signal */
516 value = afi_readl(port->pcie, ctrl);
517 value &= ~AFI_PEX_CTRL_RST;
518 afi_writel(port->pcie, value, ctrl);
520 usleep_range(1000, 2000);
522 value = afi_readl(port->pcie, ctrl);
523 value |= AFI_PEX_CTRL_RST;
524 afi_writel(port->pcie, value, ctrl);
527 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
529 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
530 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
533 /* enable reference clock */
534 value = afi_readl(port->pcie, ctrl);
535 value |= AFI_PEX_CTRL_REFCLK_EN;
537 if (soc->has_pex_clkreq_en)
538 value |= AFI_PEX_CTRL_CLKREQ_EN;
540 value |= AFI_PEX_CTRL_OVERRIDE_EN;
542 afi_writel(port->pcie, value, ctrl);
544 tegra_pcie_port_reset(port);
547 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
549 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
550 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
553 /* assert port reset */
554 value = afi_readl(port->pcie, ctrl);
555 value &= ~AFI_PEX_CTRL_RST;
556 afi_writel(port->pcie, value, ctrl);
558 /* disable reference clock */
559 value = afi_readl(port->pcie, ctrl);
561 if (soc->has_pex_clkreq_en)
562 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
564 value &= ~AFI_PEX_CTRL_REFCLK_EN;
565 afi_writel(port->pcie, value, ctrl);
568 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
570 struct tegra_pcie *pcie = port->pcie;
572 devm_iounmap(pcie->dev, port->base);
573 devm_release_mem_region(pcie->dev, port->regs.start,
574 resource_size(&port->regs));
575 list_del(&port->list);
576 devm_kfree(pcie->dev, port);
579 /* Tegra PCIE root complex wrongly reports device class */
580 static void tegra_pcie_fixup_class(struct pci_dev *dev)
582 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
589 /* Tegra20 and Tegra30 PCIE requires relaxed ordering */
590 static void tegra_pcie_relax_enable(struct pci_dev *dev)
592 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_relax_enable);
595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_relax_enable);
596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_relax_enable);
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_relax_enable);
599 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
601 struct tegra_pcie *pcie = sys_to_pcie(sys);
604 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem);
608 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch);
612 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
613 pci_add_resource_offset(&sys->resources, &pcie->prefetch,
615 pci_add_resource(&sys->resources, &pcie->busn);
617 pci_ioremap_io(pcie->pio.start, pcie->io.start);
622 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
624 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
627 tegra_cpuidle_pcie_irqs_in_use();
629 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
636 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
638 const char *err_msg[] = {
646 "Response decoding error",
647 "AXI response decoding error",
648 "Transaction timeout",
649 "Slot present pin change",
650 "Slot clock request change",
651 "TMS clock ramp change",
652 "TMS ready for power down",
655 struct tegra_pcie *pcie = arg;
658 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
659 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
660 afi_writel(pcie, 0, AFI_INTR_CODE);
662 if (code == AFI_INTR_LEGACY)
665 if (code >= ARRAY_SIZE(err_msg))
669 * do not pollute kernel log with master abort reports since they
670 * happen a lot during enumeration
672 if (code == AFI_INTR_MASTER_ABORT)
673 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
676 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
679 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
680 code == AFI_INTR_FPCI_DECODE_ERROR) {
681 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
682 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
684 if (code == AFI_INTR_MASTER_ABORT)
685 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address);
687 dev_err(pcie->dev, " FPCI address: %10llx\n", address);
694 * FPCI map is as follows:
695 * - 0xfdfc000000: I/O space
696 * - 0xfdfe000000: type 0 configuration space
697 * - 0xfdff000000: type 1 configuration space
698 * - 0xfe00000000: type 0 extended configuration space
699 * - 0xfe10000000: type 1 extended configuration space
701 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
703 u32 fpci_bar, size, axi_address;
705 /* Bar 0: type 1 extended configuration space */
706 fpci_bar = 0xfe100000;
707 size = resource_size(pcie->cs);
708 axi_address = pcie->cs->start;
709 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
710 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
711 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
713 /* Bar 1: downstream IO bar */
714 fpci_bar = 0xfdfc0000;
715 size = resource_size(&pcie->io);
716 axi_address = pcie->io.start;
717 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
718 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
719 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
721 /* Bar 2: prefetchable memory BAR */
722 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
723 size = resource_size(&pcie->prefetch);
724 axi_address = pcie->prefetch.start;
725 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
726 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
727 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
729 /* Bar 3: non prefetchable memory BAR */
730 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
731 size = resource_size(&pcie->mem);
732 axi_address = pcie->mem.start;
733 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
734 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
735 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
737 /* NULL out the remaining BARs as they are not used */
738 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
739 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
740 afi_writel(pcie, 0, AFI_FPCI_BAR4);
742 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
743 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
744 afi_writel(pcie, 0, AFI_FPCI_BAR5);
746 /* map all upstream transactions as uncached */
747 afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST);
748 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
749 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
750 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
752 /* MSI translations are setup only when needed */
753 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
754 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
755 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
756 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
759 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
761 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
764 timeout = jiffies + msecs_to_jiffies(timeout);
766 while (time_before(jiffies, timeout)) {
767 value = pads_readl(pcie, soc->pads_pll_ctl);
768 if (value & PADS_PLL_CTL_LOCKDET)
775 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
777 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
781 /* initialize internal PHY, enable up to 16 PCIE lanes */
782 pads_writel(pcie, 0x0, PADS_CTL_SEL);
784 /* override IDDQ to 1 on all 4 lanes */
785 value = pads_readl(pcie, PADS_CTL);
786 value |= PADS_CTL_IDDQ_1L;
787 pads_writel(pcie, value, PADS_CTL);
790 * Set up PHY PLL inputs select PLLE output as refclock,
791 * set TX ref sel to div10 (not div5).
793 value = pads_readl(pcie, soc->pads_pll_ctl);
794 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
795 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
796 pads_writel(pcie, value, soc->pads_pll_ctl);
799 value = pads_readl(pcie, soc->pads_pll_ctl);
800 value &= ~PADS_PLL_CTL_RST_B4SM;
801 pads_writel(pcie, value, soc->pads_pll_ctl);
803 usleep_range(20, 100);
805 /* take PLL out of reset */
806 value = pads_readl(pcie, soc->pads_pll_ctl);
807 value |= PADS_PLL_CTL_RST_B4SM;
808 pads_writel(pcie, value, soc->pads_pll_ctl);
810 /* Configure the reference clock driver */
811 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
812 pads_writel(pcie, value, PADS_REFCLK_CFG0);
813 if (soc->num_ports > 2)
814 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
816 /* wait for the PLL to lock */
817 err = tegra_pcie_pll_wait(pcie, 500);
819 dev_err(pcie->dev, "PLL failed to lock: %d\n", err);
823 /* turn off IDDQ override */
824 value = pads_readl(pcie, PADS_CTL);
825 value &= ~PADS_CTL_IDDQ_1L;
826 pads_writel(pcie, value, PADS_CTL);
828 /* enable TX/RX data */
829 value = pads_readl(pcie, PADS_CTL);
830 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
831 pads_writel(pcie, value, PADS_CTL);
836 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
838 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
839 struct tegra_pcie_port *port;
843 /* enable PLL power down */
845 value = afi_readl(pcie, AFI_PLLE_CONTROL);
846 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
847 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
848 afi_writel(pcie, value, AFI_PLLE_CONTROL);
851 /* power down PCIe slot clock bias pad */
852 if (soc->has_pex_bias_ctrl)
853 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
855 /* configure mode and disable all ports */
856 value = afi_readl(pcie, AFI_PCIE_CONFIG);
857 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
858 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
860 list_for_each_entry(port, &pcie->ports, list)
861 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
863 afi_writel(pcie, value, AFI_PCIE_CONFIG);
866 value = afi_readl(pcie, AFI_FUSE);
867 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
868 afi_writel(pcie, value, AFI_FUSE);
870 value = afi_readl(pcie, AFI_FUSE);
871 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
872 afi_writel(pcie, value, AFI_FUSE);
876 err = tegra_pcie_phy_enable(pcie);
878 err = phy_power_on(pcie->phy);
881 dev_err(pcie->dev, "failed to power on PHY: %d\n", err);
885 /* take the PCIe interface module out of reset */
886 reset_control_deassert(pcie->pcie_xrst);
888 /* finally enable PCIe */
889 value = afi_readl(pcie, AFI_CONFIGURATION);
890 value |= AFI_CONFIGURATION_EN_FPCI;
891 afi_writel(pcie, value, AFI_CONFIGURATION);
893 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
894 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
895 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
897 if (soc->has_intr_prsnt_sense)
898 value |= AFI_INTR_EN_PRSNT_SENSE;
900 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
901 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
903 /* don't enable MSI for now, only when needed */
904 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
906 /* disable all exceptions */
907 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
912 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
916 /* TODO: disable and unprepare clocks? */
918 err = phy_power_off(pcie->phy);
920 dev_warn(pcie->dev, "failed to power off PHY: %d\n", err);
922 reset_control_assert(pcie->pcie_xrst);
923 reset_control_assert(pcie->afi_rst);
924 reset_control_assert(pcie->pex_rst);
926 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
928 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
930 dev_warn(pcie->dev, "failed to disable regulators: %d\n", err);
933 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
935 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
938 reset_control_assert(pcie->pcie_xrst);
939 reset_control_assert(pcie->afi_rst);
940 reset_control_assert(pcie->pex_rst);
942 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
944 /* enable regulators */
945 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
947 dev_err(pcie->dev, "failed to enable regulators: %d\n", err);
949 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
953 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
957 reset_control_deassert(pcie->afi_rst);
959 err = clk_prepare_enable(pcie->afi_clk);
961 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
965 if (soc->has_cml_clk) {
966 err = clk_prepare_enable(pcie->cml_clk);
968 dev_err(pcie->dev, "failed to enable CML clock: %d\n",
974 err = clk_prepare_enable(pcie->pll_e);
976 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
983 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
985 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
987 pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
988 if (IS_ERR(pcie->pex_clk))
989 return PTR_ERR(pcie->pex_clk);
991 pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
992 if (IS_ERR(pcie->afi_clk))
993 return PTR_ERR(pcie->afi_clk);
995 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
996 if (IS_ERR(pcie->pll_e))
997 return PTR_ERR(pcie->pll_e);
999 if (soc->has_cml_clk) {
1000 pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
1001 if (IS_ERR(pcie->cml_clk))
1002 return PTR_ERR(pcie->cml_clk);
1008 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1010 pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
1011 if (IS_ERR(pcie->pex_rst))
1012 return PTR_ERR(pcie->pex_rst);
1014 pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
1015 if (IS_ERR(pcie->afi_rst))
1016 return PTR_ERR(pcie->afi_rst);
1018 pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
1019 if (IS_ERR(pcie->pcie_xrst))
1020 return PTR_ERR(pcie->pcie_xrst);
1025 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1027 struct platform_device *pdev = to_platform_device(pcie->dev);
1028 struct resource *pads, *afi, *res;
1031 err = tegra_pcie_clocks_get(pcie);
1033 dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
1037 err = tegra_pcie_resets_get(pcie);
1039 dev_err(&pdev->dev, "failed to get resets: %d\n", err);
1043 pcie->phy = devm_phy_optional_get(pcie->dev, "pcie");
1044 if (IS_ERR(pcie->phy)) {
1045 err = PTR_ERR(pcie->phy);
1046 dev_err(&pdev->dev, "failed to get PHY: %d\n", err);
1050 err = phy_init(pcie->phy);
1052 dev_err(&pdev->dev, "failed to initialize PHY: %d\n", err);
1056 err = tegra_pcie_power_on(pcie);
1058 dev_err(&pdev->dev, "failed to power up: %d\n", err);
1062 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1063 pcie->pads = devm_ioremap_resource(&pdev->dev, pads);
1064 if (IS_ERR(pcie->pads)) {
1065 err = PTR_ERR(pcie->pads);
1069 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1070 pcie->afi = devm_ioremap_resource(&pdev->dev, afi);
1071 if (IS_ERR(pcie->afi)) {
1072 err = PTR_ERR(pcie->afi);
1076 /* request configuration space, but remap later, on demand */
1077 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1079 err = -EADDRNOTAVAIL;
1083 pcie->cs = devm_request_mem_region(pcie->dev, res->start,
1084 resource_size(res), res->name);
1086 err = -EADDRNOTAVAIL;
1090 /* request interrupt */
1091 err = platform_get_irq_byname(pdev, "intr");
1093 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1099 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1101 dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
1108 tegra_pcie_power_off(pcie);
1112 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1117 free_irq(pcie->irq, pcie);
1119 tegra_pcie_power_off(pcie);
1121 err = phy_exit(pcie->phy);
1123 dev_err(pcie->dev, "failed to teardown PHY: %d\n", err);
1128 static int tegra_msi_alloc(struct tegra_msi *chip)
1132 mutex_lock(&chip->lock);
1134 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1135 if (msi < INT_PCI_MSI_NR)
1136 set_bit(msi, chip->used);
1140 mutex_unlock(&chip->lock);
1145 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1147 struct device *dev = chip->chip.dev;
1149 mutex_lock(&chip->lock);
1151 if (!test_bit(irq, chip->used))
1152 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1154 clear_bit(irq, chip->used);
1156 mutex_unlock(&chip->lock);
1159 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1161 struct tegra_pcie *pcie = data;
1162 struct tegra_msi *msi = &pcie->msi;
1163 unsigned int i, processed = 0;
1165 for (i = 0; i < 8; i++) {
1166 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1169 unsigned int offset = find_first_bit(®, 32);
1170 unsigned int index = i * 32 + offset;
1173 /* clear the interrupt */
1174 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1176 irq = irq_find_mapping(msi->domain, index);
1178 if (test_bit(index, msi->used))
1179 generic_handle_irq(irq);
1181 dev_info(pcie->dev, "unhandled MSI\n");
1184 * that's weird who triggered this?
1187 dev_info(pcie->dev, "unexpected MSI\n");
1190 /* see if there's any more pending in this vector */
1191 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1197 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1200 static int tegra_msi_setup_irq(struct msi_controller *chip,
1201 struct pci_dev *pdev, struct msi_desc *desc)
1203 struct tegra_msi *msi = to_tegra_msi(chip);
1208 hwirq = tegra_msi_alloc(msi);
1212 irq = irq_create_mapping(msi->domain, hwirq);
1214 tegra_msi_free(msi, hwirq);
1218 irq_set_msi_desc(irq, desc);
1220 msg.address_lo = virt_to_phys((void *)msi->pages);
1221 /* 32 bit address only */
1225 pci_write_msi_msg(irq, &msg);
1230 static void tegra_msi_teardown_irq(struct msi_controller *chip,
1233 struct tegra_msi *msi = to_tegra_msi(chip);
1234 struct irq_data *d = irq_get_irq_data(irq);
1235 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1237 irq_dispose_mapping(irq);
1238 tegra_msi_free(msi, hwirq);
1241 static struct irq_chip tegra_msi_irq_chip = {
1242 .name = "Tegra PCIe MSI",
1243 .irq_enable = pci_msi_unmask_irq,
1244 .irq_disable = pci_msi_mask_irq,
1245 .irq_mask = pci_msi_mask_irq,
1246 .irq_unmask = pci_msi_unmask_irq,
1249 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1250 irq_hw_number_t hwirq)
1252 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1253 irq_set_chip_data(irq, domain->host_data);
1255 tegra_cpuidle_pcie_irqs_in_use();
1260 static const struct irq_domain_ops msi_domain_ops = {
1261 .map = tegra_msi_map,
1264 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1266 struct platform_device *pdev = to_platform_device(pcie->dev);
1267 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1268 struct tegra_msi *msi = &pcie->msi;
1273 mutex_init(&msi->lock);
1275 msi->chip.dev = pcie->dev;
1276 msi->chip.setup_irq = tegra_msi_setup_irq;
1277 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1279 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
1280 &msi_domain_ops, &msi->chip);
1282 dev_err(&pdev->dev, "failed to create IRQ domain\n");
1286 err = platform_get_irq_byname(pdev, "msi");
1288 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1294 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
1295 tegra_msi_irq_chip.name, pcie);
1297 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1301 /* setup AFI/FPCI range */
1302 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1303 base = virt_to_phys((void *)msi->pages);
1305 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1306 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1307 /* this register is in 4K increments */
1308 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1310 /* enable all MSI vectors */
1311 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1312 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1313 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1314 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1315 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1316 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1317 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1318 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1320 /* and unmask the MSI interrupt */
1321 reg = afi_readl(pcie, AFI_INTR_MASK);
1322 reg |= AFI_INTR_MASK_MSI_MASK;
1323 afi_writel(pcie, reg, AFI_INTR_MASK);
1328 irq_domain_remove(msi->domain);
1332 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1334 struct tegra_msi *msi = &pcie->msi;
1335 unsigned int i, irq;
1338 /* mask the MSI interrupt */
1339 value = afi_readl(pcie, AFI_INTR_MASK);
1340 value &= ~AFI_INTR_MASK_MSI_MASK;
1341 afi_writel(pcie, value, AFI_INTR_MASK);
1343 /* disable all MSI vectors */
1344 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1345 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1346 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1347 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1348 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1349 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1350 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1351 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1353 free_pages(msi->pages, 0);
1356 free_irq(msi->irq, pcie);
1358 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1359 irq = irq_find_mapping(msi->domain, i);
1361 irq_dispose_mapping(irq);
1364 irq_domain_remove(msi->domain);
1369 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1372 struct device_node *np = pcie->dev->of_node;
1374 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1377 dev_info(pcie->dev, "4x1, 1x1 configuration\n");
1378 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
1382 dev_info(pcie->dev, "2x1, 1x1 configuration\n");
1383 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
1386 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1389 dev_info(pcie->dev, "4x1, 2x1 configuration\n");
1390 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1394 dev_info(pcie->dev, "2x3 configuration\n");
1395 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1399 dev_info(pcie->dev, "4x1, 1x2 configuration\n");
1400 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1403 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1406 dev_info(pcie->dev, "single-mode configuration\n");
1407 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1411 dev_info(pcie->dev, "dual-mode configuration\n");
1412 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1421 * Check whether a given set of supplies is available in a device tree node.
1422 * This is used to check whether the new or the legacy device tree bindings
1425 static bool of_regulator_bulk_available(struct device_node *np,
1426 struct regulator_bulk_data *supplies,
1427 unsigned int num_supplies)
1432 for (i = 0; i < num_supplies; i++) {
1433 snprintf(property, 32, "%s-supply", supplies[i].supply);
1435 if (of_find_property(np, property, NULL) == NULL)
1443 * Old versions of the device tree binding for this device used a set of power
1444 * supplies that didn't match the hardware inputs. This happened to work for a
1445 * number of cases but is not future proof. However to preserve backwards-
1446 * compatibility with old device trees, this function will try to use the old
1449 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1451 struct device_node *np = pcie->dev->of_node;
1453 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1454 pcie->num_supplies = 3;
1455 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1456 pcie->num_supplies = 2;
1458 if (pcie->num_supplies == 0) {
1459 dev_err(pcie->dev, "device %s not supported in legacy mode\n",
1464 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1465 sizeof(*pcie->supplies),
1467 if (!pcie->supplies)
1470 pcie->supplies[0].supply = "pex-clk";
1471 pcie->supplies[1].supply = "vdd";
1473 if (pcie->num_supplies > 2)
1474 pcie->supplies[2].supply = "avdd";
1476 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1481 * Obtains the list of regulators required for a particular generation of the
1484 * This would've been nice to do simply by providing static tables for use
1485 * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
1486 * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
1487 * and either seems to be optional depending on which ports are being used.
1489 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1491 struct device_node *np = pcie->dev->of_node;
1494 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1495 pcie->num_supplies = 7;
1497 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1498 sizeof(*pcie->supplies),
1500 if (!pcie->supplies)
1503 pcie->supplies[i++].supply = "avddio-pex";
1504 pcie->supplies[i++].supply = "dvddio-pex";
1505 pcie->supplies[i++].supply = "avdd-pex-pll";
1506 pcie->supplies[i++].supply = "hvdd-pex";
1507 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1508 pcie->supplies[i++].supply = "vddio-pex-ctl";
1509 pcie->supplies[i++].supply = "avdd-pll-erefe";
1510 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1511 bool need_pexa = false, need_pexb = false;
1513 /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
1514 if (lane_mask & 0x0f)
1517 /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
1518 if (lane_mask & 0x30)
1521 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
1522 (need_pexb ? 2 : 0);
1524 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1525 sizeof(*pcie->supplies),
1527 if (!pcie->supplies)
1530 pcie->supplies[i++].supply = "avdd-pex-pll";
1531 pcie->supplies[i++].supply = "hvdd-pex";
1532 pcie->supplies[i++].supply = "vddio-pex-ctl";
1533 pcie->supplies[i++].supply = "avdd-plle";
1536 pcie->supplies[i++].supply = "avdd-pexa";
1537 pcie->supplies[i++].supply = "vdd-pexa";
1541 pcie->supplies[i++].supply = "avdd-pexb";
1542 pcie->supplies[i++].supply = "vdd-pexb";
1544 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1545 pcie->num_supplies = 5;
1547 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1548 sizeof(*pcie->supplies),
1550 if (!pcie->supplies)
1553 pcie->supplies[0].supply = "avdd-pex";
1554 pcie->supplies[1].supply = "vdd-pex";
1555 pcie->supplies[2].supply = "avdd-pex-pll";
1556 pcie->supplies[3].supply = "avdd-plle";
1557 pcie->supplies[4].supply = "vddio-pex-clk";
1560 if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies,
1561 pcie->num_supplies))
1562 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1566 * If not all regulators are available for this new scheme, assume
1567 * that the device tree complies with an older version of the device
1570 dev_info(pcie->dev, "using legacy DT binding for power supplies\n");
1572 devm_kfree(pcie->dev, pcie->supplies);
1573 pcie->num_supplies = 0;
1575 return tegra_pcie_get_legacy_regulators(pcie);
1578 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1580 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1581 struct device_node *np = pcie->dev->of_node, *port;
1582 struct of_pci_range_parser parser;
1583 struct of_pci_range range;
1584 u32 lanes = 0, mask = 0;
1585 unsigned int lane = 0;
1586 struct resource res;
1589 memset(&pcie->all, 0, sizeof(pcie->all));
1590 pcie->all.flags = IORESOURCE_MEM;
1591 pcie->all.name = np->full_name;
1592 pcie->all.start = ~0;
1595 if (of_pci_range_parser_init(&parser, np)) {
1596 dev_err(pcie->dev, "missing \"ranges\" property\n");
1600 for_each_of_pci_range(&parser, &range) {
1601 err = of_pci_range_to_resource(&range, np, &res);
1605 switch (res.flags & IORESOURCE_TYPE_BITS) {
1607 memcpy(&pcie->pio, &res, sizeof(res));
1608 pcie->pio.name = np->full_name;
1611 * The Tegra PCIe host bridge uses this to program the
1612 * mapping of the I/O space to the physical address,
1613 * so we override the .start and .end fields here that
1614 * of_pci_range_to_resource() converted to I/O space.
1615 * We also set the IORESOURCE_MEM type to clarify that
1616 * the resource is in the physical memory space.
1618 pcie->io.start = range.cpu_addr;
1619 pcie->io.end = range.cpu_addr + range.size - 1;
1620 pcie->io.flags = IORESOURCE_MEM;
1621 pcie->io.name = "I/O";
1623 memcpy(&res, &pcie->io, sizeof(res));
1626 case IORESOURCE_MEM:
1627 if (res.flags & IORESOURCE_PREFETCH) {
1628 memcpy(&pcie->prefetch, &res, sizeof(res));
1629 pcie->prefetch.name = "prefetchable";
1631 memcpy(&pcie->mem, &res, sizeof(res));
1632 pcie->mem.name = "non-prefetchable";
1637 if (res.start <= pcie->all.start)
1638 pcie->all.start = res.start;
1640 if (res.end >= pcie->all.end)
1641 pcie->all.end = res.end;
1644 err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all);
1648 err = of_pci_parse_bus_range(np, &pcie->busn);
1650 dev_err(pcie->dev, "failed to parse ranges property: %d\n",
1652 pcie->busn.name = np->name;
1653 pcie->busn.start = 0;
1654 pcie->busn.end = 0xff;
1655 pcie->busn.flags = IORESOURCE_BUS;
1658 /* parse root ports */
1659 for_each_child_of_node(np, port) {
1660 struct tegra_pcie_port *rp;
1664 err = of_pci_get_devfn(port);
1666 dev_err(pcie->dev, "failed to parse address: %d\n",
1671 index = PCI_SLOT(err);
1673 if (index < 1 || index > soc->num_ports) {
1674 dev_err(pcie->dev, "invalid port number: %d\n", index);
1680 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1682 dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
1688 dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
1692 lanes |= value << (index << 3);
1694 if (!of_device_is_available(port)) {
1699 mask |= ((1 << value) - 1) << lane;
1702 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
1706 err = of_address_to_resource(port, 0, &rp->regs);
1708 dev_err(pcie->dev, "failed to parse address: %d\n",
1713 INIT_LIST_HEAD(&rp->list);
1718 rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
1719 if (IS_ERR(rp->base))
1720 return PTR_ERR(rp->base);
1722 list_add_tail(&rp->list, &pcie->ports);
1725 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1727 dev_err(pcie->dev, "invalid lane configuration\n");
1731 err = tegra_pcie_get_regulators(pcie, mask);
1739 * FIXME: If there are no PCIe cards attached, then calling this function
1740 * can result in the increase of the bootup time as there are big timeout
1743 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1744 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1746 unsigned int retries = 3;
1747 unsigned long value;
1749 /* override presence detection */
1750 value = readl(port->base + RP_PRIV_MISC);
1751 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
1752 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
1753 writel(value, port->base + RP_PRIV_MISC);
1756 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1759 value = readl(port->base + RP_VEND_XP);
1761 if (value & RP_VEND_XP_DL_UP)
1764 usleep_range(1000, 2000);
1765 } while (--timeout);
1768 dev_err(port->pcie->dev, "link %u down, retrying\n",
1773 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1776 value = readl(port->base + RP_LINK_CONTROL_STATUS);
1778 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1781 usleep_range(1000, 2000);
1782 } while (--timeout);
1785 tegra_pcie_port_reset(port);
1786 } while (--retries);
1791 static int tegra_pcie_enable(struct tegra_pcie *pcie)
1793 struct tegra_pcie_port *port, *tmp;
1796 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1797 dev_info(pcie->dev, "probing port %u, using %u lanes\n",
1798 port->index, port->lanes);
1800 tegra_pcie_port_enable(port);
1802 if (tegra_pcie_port_check_link(port))
1805 dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
1807 tegra_pcie_port_disable(port);
1808 tegra_pcie_port_free(port);
1811 memset(&hw, 0, sizeof(hw));
1813 #ifdef CONFIG_PCI_MSI
1814 hw.msi_ctrl = &pcie->msi.chip;
1817 hw.nr_controllers = 1;
1818 hw.private_data = (void **)&pcie;
1819 hw.setup = tegra_pcie_setup;
1820 hw.map_irq = tegra_pcie_map_irq;
1821 hw.ops = &tegra_pcie_ops;
1823 pci_common_init_dev(pcie->dev, &hw);
1828 static const struct tegra_pcie_soc_data tegra20_pcie_data = {
1830 .msi_base_shift = 0,
1831 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1832 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1833 .has_pex_clkreq_en = false,
1834 .has_pex_bias_ctrl = false,
1835 .has_intr_prsnt_sense = false,
1836 .has_cml_clk = false,
1840 static const struct tegra_pcie_soc_data tegra30_pcie_data = {
1842 .msi_base_shift = 8,
1843 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1844 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1845 .has_pex_clkreq_en = true,
1846 .has_pex_bias_ctrl = true,
1847 .has_intr_prsnt_sense = true,
1848 .has_cml_clk = true,
1852 static const struct tegra_pcie_soc_data tegra124_pcie_data = {
1854 .msi_base_shift = 8,
1855 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1856 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1857 .has_pex_clkreq_en = true,
1858 .has_pex_bias_ctrl = true,
1859 .has_intr_prsnt_sense = true,
1860 .has_cml_clk = true,
1864 static const struct of_device_id tegra_pcie_of_match[] = {
1865 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data },
1866 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
1867 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
1870 MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
1872 static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos)
1874 struct tegra_pcie *pcie = s->private;
1876 if (list_empty(&pcie->ports))
1879 seq_printf(s, "Index Status\n");
1881 return seq_list_start(&pcie->ports, *pos);
1884 static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
1886 struct tegra_pcie *pcie = s->private;
1888 return seq_list_next(v, &pcie->ports, pos);
1891 static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
1895 static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
1897 bool up = false, active = false;
1898 struct tegra_pcie_port *port;
1901 port = list_entry(v, struct tegra_pcie_port, list);
1903 value = readl(port->base + RP_VEND_XP);
1905 if (value & RP_VEND_XP_DL_UP)
1908 value = readl(port->base + RP_LINK_CONTROL_STATUS);
1910 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1913 seq_printf(s, "%2u ", port->index);
1916 seq_printf(s, "up");
1920 seq_printf(s, ", ");
1922 seq_printf(s, "active");
1925 seq_printf(s, "\n");
1929 static const struct seq_operations tegra_pcie_ports_seq_ops = {
1930 .start = tegra_pcie_ports_seq_start,
1931 .next = tegra_pcie_ports_seq_next,
1932 .stop = tegra_pcie_ports_seq_stop,
1933 .show = tegra_pcie_ports_seq_show,
1936 static int tegra_pcie_ports_open(struct inode *inode, struct file *file)
1938 struct tegra_pcie *pcie = inode->i_private;
1942 err = seq_open(file, &tegra_pcie_ports_seq_ops);
1946 s = file->private_data;
1952 static const struct file_operations tegra_pcie_ports_ops = {
1953 .owner = THIS_MODULE,
1954 .open = tegra_pcie_ports_open,
1956 .llseek = seq_lseek,
1957 .release = seq_release,
1960 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
1962 struct dentry *file;
1964 pcie->debugfs = debugfs_create_dir("pcie", NULL);
1968 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs,
1969 pcie, &tegra_pcie_ports_ops);
1976 debugfs_remove_recursive(pcie->debugfs);
1977 pcie->debugfs = NULL;
1981 static int tegra_pcie_probe(struct platform_device *pdev)
1983 const struct of_device_id *match;
1984 struct tegra_pcie *pcie;
1987 match = of_match_device(tegra_pcie_of_match, &pdev->dev);
1991 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1995 INIT_LIST_HEAD(&pcie->buses);
1996 INIT_LIST_HEAD(&pcie->ports);
1997 pcie->soc_data = match->data;
1998 pcie->dev = &pdev->dev;
2000 err = tegra_pcie_parse_dt(pcie);
2004 pcibios_min_mem = 0;
2006 err = tegra_pcie_get_resources(pcie);
2008 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
2012 err = tegra_pcie_enable_controller(pcie);
2016 /* setup the AFI address translations */
2017 tegra_pcie_setup_translations(pcie);
2019 if (IS_ENABLED(CONFIG_PCI_MSI)) {
2020 err = tegra_pcie_enable_msi(pcie);
2023 "failed to enable MSI support: %d\n",
2029 err = tegra_pcie_enable(pcie);
2031 dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
2035 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2036 err = tegra_pcie_debugfs_init(pcie);
2038 dev_err(&pdev->dev, "failed to setup debugfs: %d\n",
2042 platform_set_drvdata(pdev, pcie);
2046 if (IS_ENABLED(CONFIG_PCI_MSI))
2047 tegra_pcie_disable_msi(pcie);
2049 tegra_pcie_put_resources(pcie);
2053 static struct platform_driver tegra_pcie_driver = {
2055 .name = "tegra-pcie",
2056 .of_match_table = tegra_pcie_of_match,
2057 .suppress_bind_attrs = true,
2059 .probe = tegra_pcie_probe,
2061 module_platform_driver(tegra_pcie_driver);
2063 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2064 MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
2065 MODULE_LICENSE("GPL v2");