2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
26 * PCIe unit register offsets.
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_CAP_PCIEXP 0x0060
34 #define PCIE_HEADER_LOG_4_OFF 0x0128
35 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
36 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
37 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
38 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
39 #define PCIE_WIN5_CTRL_OFF 0x1880
40 #define PCIE_WIN5_BASE_OFF 0x1884
41 #define PCIE_WIN5_REMAP_OFF 0x188c
42 #define PCIE_CONF_ADDR_OFF 0x18f8
43 #define PCIE_CONF_ADDR_EN 0x80000000
44 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
45 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
46 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
47 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
48 #define PCIE_CONF_ADDR(bus, devfn, where) \
49 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
50 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
52 #define PCIE_CONF_DATA_OFF 0x18fc
53 #define PCIE_MASK_OFF 0x1910
54 #define PCIE_MASK_ENABLE_INTS 0x0f000000
55 #define PCIE_CTRL_OFF 0x1a00
56 #define PCIE_CTRL_X1_MODE 0x0001
57 #define PCIE_STAT_OFF 0x1a04
58 #define PCIE_STAT_BUS 0xff00
59 #define PCIE_STAT_DEV 0x1f0000
60 #define PCIE_STAT_LINK_DOWN BIT(0)
61 #define PCIE_RC_RTSTA 0x1a14
62 #define PCIE_DEBUG_CTRL 0x1a60
63 #define PCIE_DEBUG_SOFT_RESET BIT(20)
66 PCISWCAP = PCI_BRIDGE_CONTROL + 2,
67 PCISWCAP_EXP_LIST_ID = PCISWCAP + PCI_CAP_LIST_ID,
68 PCISWCAP_EXP_DEVCAP = PCISWCAP + PCI_EXP_DEVCAP,
69 PCISWCAP_EXP_DEVCTL = PCISWCAP + PCI_EXP_DEVCTL,
70 PCISWCAP_EXP_LNKCAP = PCISWCAP + PCI_EXP_LNKCAP,
71 PCISWCAP_EXP_LNKCTL = PCISWCAP + PCI_EXP_LNKCTL,
72 PCISWCAP_EXP_SLTCAP = PCISWCAP + PCI_EXP_SLTCAP,
73 PCISWCAP_EXP_SLTCTL = PCISWCAP + PCI_EXP_SLTCTL,
74 PCISWCAP_EXP_RTCTL = PCISWCAP + PCI_EXP_RTCTL,
75 PCISWCAP_EXP_RTSTA = PCISWCAP + PCI_EXP_RTSTA,
76 PCISWCAP_EXP_DEVCAP2 = PCISWCAP + PCI_EXP_DEVCAP2,
77 PCISWCAP_EXP_DEVCTL2 = PCISWCAP + PCI_EXP_DEVCTL2,
78 PCISWCAP_EXP_LNKCAP2 = PCISWCAP + PCI_EXP_LNKCAP2,
79 PCISWCAP_EXP_LNKCTL2 = PCISWCAP + PCI_EXP_LNKCTL2,
80 PCISWCAP_EXP_SLTCAP2 = PCISWCAP + PCI_EXP_SLTCAP2,
81 PCISWCAP_EXP_SLTCTL2 = PCISWCAP + PCI_EXP_SLTCTL2,
84 /* PCI configuration space of a PCI-to-PCI bridge */
85 struct mvebu_sw_pci_bridge {
101 u8 secondary_latency_timer;
104 u16 secondary_status;
114 /* PCI express capability */
120 struct mvebu_pcie_port;
122 /* Structure representing all PCIe interfaces */
124 struct platform_device *pdev;
125 struct mvebu_pcie_port *ports;
126 struct msi_controller *msi;
128 struct resource realio;
130 struct resource busn;
134 struct mvebu_pcie_window {
140 /* Structure representing one PCIe interface */
141 struct mvebu_pcie_port {
147 unsigned int mem_target;
148 unsigned int mem_attr;
149 unsigned int io_target;
150 unsigned int io_attr;
152 struct gpio_desc *reset_gpio;
154 struct mvebu_sw_pci_bridge bridge;
155 struct device_node *dn;
156 struct mvebu_pcie *pcie;
157 struct mvebu_pcie_window memwin;
158 struct mvebu_pcie_window iowin;
162 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
164 writel(val, port->base + reg);
167 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
169 return readl(port->base + reg);
172 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
174 return port->io_target != -1 && port->io_attr != -1;
177 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
179 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
182 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
186 stat = mvebu_readl(port, PCIE_STAT_OFF);
187 stat &= ~PCIE_STAT_BUS;
189 mvebu_writel(port, stat, PCIE_STAT_OFF);
192 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
196 stat = mvebu_readl(port, PCIE_STAT_OFF);
197 stat &= ~PCIE_STAT_DEV;
199 mvebu_writel(port, stat, PCIE_STAT_OFF);
203 * Setup PCIE BARs and Address Decode Wins:
204 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
205 * WIN[0-3] -> DRAM bank[0-3]
207 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
209 const struct mbus_dram_target_info *dram;
213 dram = mv_mbus_dram_info();
215 /* First, disable and clear BARs and windows. */
216 for (i = 1; i < 3; i++) {
217 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
218 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
219 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
222 for (i = 0; i < 5; i++) {
223 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
224 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
225 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
228 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
229 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
230 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
232 /* Setup windows for DDR banks. Count total DDR size on the fly. */
234 for (i = 0; i < dram->num_cs; i++) {
235 const struct mbus_dram_window *cs = dram->cs + i;
237 mvebu_writel(port, cs->base & 0xffff0000,
238 PCIE_WIN04_BASE_OFF(i));
239 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
241 ((cs->size - 1) & 0xffff0000) |
242 (cs->mbus_attr << 8) |
243 (dram->mbus_dram_target_id << 4) | 1,
244 PCIE_WIN04_CTRL_OFF(i));
249 /* Round up 'size' to the nearest power of two. */
250 if ((size & (size - 1)) != 0)
251 size = 1 << fls(size);
253 /* Setup BAR[1] to all DRAM banks. */
254 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
255 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
256 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
257 PCIE_BAR_CTRL_OFF(1));
260 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
264 /* Point PCIe unit MBUS decode windows to DRAM space. */
265 mvebu_pcie_setup_wins(port);
267 /* Master + slave enable. */
268 cmd = mvebu_readl(port, PCIE_CMD_OFF);
269 cmd |= PCI_COMMAND_IO;
270 cmd |= PCI_COMMAND_MEMORY;
271 cmd |= PCI_COMMAND_MASTER;
272 mvebu_writel(port, cmd, PCIE_CMD_OFF);
274 /* Enable interrupt lines A-D. */
275 mask = mvebu_readl(port, PCIE_MASK_OFF);
276 mask |= PCIE_MASK_ENABLE_INTS;
277 mvebu_writel(port, mask, PCIE_MASK_OFF);
280 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
282 u32 devfn, int where, int size, u32 *val)
284 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
286 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
291 *val = readb_relaxed(conf_data + (where & 3));
294 *val = readw_relaxed(conf_data + (where & 2));
297 *val = readl_relaxed(conf_data);
301 return PCIBIOS_SUCCESSFUL;
304 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
306 u32 devfn, int where, int size, u32 val)
308 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
310 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
315 writeb(val, conf_data + (where & 3));
318 writew(val, conf_data + (where & 2));
321 writel(val, conf_data);
324 return PCIBIOS_BAD_REGISTER_NUMBER;
327 return PCIBIOS_SUCCESSFUL;
331 * Remove windows, starting from the largest ones to the smallest
334 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
335 phys_addr_t base, size_t size)
338 size_t sz = 1 << (fls(size) - 1);
340 mvebu_mbus_del_window(base, sz);
347 * MBus windows can only have a power of two size, but PCI BARs do not
348 * have this constraint. Therefore, we have to split the PCI BAR into
349 * areas each having a power of two size. We start from the largest
350 * one (i.e highest order bit set in the size).
352 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
353 unsigned int target, unsigned int attribute,
354 phys_addr_t base, size_t size,
357 size_t size_mapped = 0;
360 size_t sz = 1 << (fls(size) - 1);
363 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
366 phys_addr_t end = base + sz - 1;
368 dev_err(&port->pcie->pdev->dev,
369 "Could not create MBus window at [mem %pa-%pa]: %d\n",
371 mvebu_pcie_del_windows(port, base - size_mapped,
379 if (remap != MVEBU_MBUS_NO_REMAP)
384 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
385 unsigned int target, unsigned int attribute,
386 const struct mvebu_pcie_window *desired,
387 struct mvebu_pcie_window *cur)
389 if (desired->base == cur->base && desired->remap == cur->remap &&
390 desired->size == cur->size)
393 if (cur->size != 0) {
394 mvebu_pcie_del_windows(port, cur->base, cur->size);
399 * If something tries to change the window while it is enabled
400 * the change will not be done atomically. That would be
401 * difficult to do in the general case.
405 if (desired->size == 0)
408 mvebu_pcie_add_windows(port, target, attribute, desired->base,
409 desired->size, desired->remap);
413 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
415 struct mvebu_pcie_window desired = {};
417 /* Are the new iobase/iolimit values invalid? */
418 if (port->bridge.iolimit < port->bridge.iobase ||
419 port->bridge.iolimitupper < port->bridge.iobaseupper ||
420 !(port->bridge.command & PCI_COMMAND_IO)) {
421 mvebu_pcie_set_window(port, port->io_target, port->io_attr,
422 &desired, &port->iowin);
426 if (!mvebu_has_ioport(port)) {
427 dev_WARN(&port->pcie->pdev->dev,
428 "Attempt to set IO when IO is disabled\n");
433 * We read the PCI-to-PCI bridge emulated registers, and
434 * calculate the base address and size of the address decoding
435 * window to setup, according to the PCI-to-PCI bridge
436 * specifications. iobase is the bus address, port->iowin_base
437 * is the CPU address.
439 desired.remap = ((port->bridge.iobase & 0xF0) << 8) |
440 (port->bridge.iobaseupper << 16);
441 desired.base = port->pcie->io.start + desired.remap;
442 desired.size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
443 (port->bridge.iolimitupper << 16)) -
447 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
451 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
453 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
455 /* Are the new membase/memlimit values invalid? */
456 if (port->bridge.memlimit < port->bridge.membase ||
457 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
458 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
459 &desired, &port->memwin);
464 * We read the PCI-to-PCI bridge emulated registers, and
465 * calculate the base address and size of the address decoding
466 * window to setup, according to the PCI-to-PCI bridge
469 desired.base = ((port->bridge.membase & 0xFFF0) << 16);
470 desired.size = (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
473 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
478 * Initialize the configuration space of the PCI-to-PCI bridge
479 * associated with the given PCIe interface.
481 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
483 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
485 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
487 bridge->class = PCI_CLASS_BRIDGE_PCI;
488 bridge->vendor = PCI_VENDOR_ID_MARVELL;
489 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
490 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
491 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
492 bridge->cache_line_size = 0x10;
494 /* We support 32 bits I/O addressing */
495 bridge->iobase = PCI_IO_RANGE_TYPE_32;
496 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
498 /* Add capabilities */
499 bridge->status = PCI_STATUS_CAP_LIST;
503 * Read the configuration space of the PCI-to-PCI bridge associated to
504 * the given PCIe interface.
506 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
507 unsigned int where, int size, u32 *value)
509 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
511 switch (where & ~3) {
513 *value = bridge->device << 16 | bridge->vendor;
517 *value = bridge->command | bridge->status << 16;
520 case PCI_CLASS_REVISION:
521 *value = bridge->class << 16 | bridge->interface << 8 |
525 case PCI_CACHE_LINE_SIZE:
526 *value = bridge->bist << 24 | bridge->header_type << 16 |
527 bridge->latency_timer << 8 | bridge->cache_line_size;
530 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
531 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
534 case PCI_PRIMARY_BUS:
535 *value = (bridge->secondary_latency_timer << 24 |
536 bridge->subordinate_bus << 16 |
537 bridge->secondary_bus << 8 |
538 bridge->primary_bus);
542 if (!mvebu_has_ioport(port))
543 *value = bridge->secondary_status << 16;
545 *value = (bridge->secondary_status << 16 |
546 bridge->iolimit << 8 |
550 case PCI_MEMORY_BASE:
551 *value = (bridge->memlimit << 16 | bridge->membase);
554 case PCI_PREF_MEMORY_BASE:
558 case PCI_IO_BASE_UPPER16:
559 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
562 case PCI_CAPABILITY_LIST:
566 case PCI_ROM_ADDRESS1:
570 case PCI_INTERRUPT_LINE:
571 /* LINE PIN MIN_GNT MAX_LAT */
575 case PCISWCAP_EXP_LIST_ID:
576 /* Set PCIe v2, root port, slot support */
577 *value = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
578 PCI_EXP_FLAGS_SLOT) << 16 | PCI_CAP_ID_EXP;
581 case PCISWCAP_EXP_DEVCAP:
582 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
585 case PCISWCAP_EXP_DEVCTL:
586 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
587 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
588 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
589 *value |= bridge->pcie_devctl;
592 case PCISWCAP_EXP_LNKCAP:
594 * PCIe requires the clock power management capability to be
595 * hard-wired to zero for downstream ports
597 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
598 ~PCI_EXP_LNKCAP_CLKPM;
601 case PCISWCAP_EXP_LNKCTL:
602 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
605 case PCISWCAP_EXP_SLTCAP:
606 *value = bridge->pcie_sltcap;
609 case PCISWCAP_EXP_SLTCTL:
610 *value = PCI_EXP_SLTSTA_PDS << 16;
613 case PCISWCAP_EXP_RTCTL:
614 *value = bridge->pcie_rtctl;
617 case PCISWCAP_EXP_RTSTA:
618 *value = mvebu_readl(port, PCIE_RC_RTSTA);
621 /* PCIe requires the v2 fields to be hard-wired to zero */
622 case PCISWCAP_EXP_DEVCAP2:
623 case PCISWCAP_EXP_DEVCTL2:
624 case PCISWCAP_EXP_LNKCAP2:
625 case PCISWCAP_EXP_LNKCTL2:
626 case PCISWCAP_EXP_SLTCAP2:
627 case PCISWCAP_EXP_SLTCTL2:
630 * PCI defines configuration read accesses to reserved or
631 * unimplemented registers to read as zero and complete
635 return PCIBIOS_SUCCESSFUL;
639 *value = (*value >> (8 * (where & 3))) & 0xffff;
641 *value = (*value >> (8 * (where & 3))) & 0xff;
643 return PCIBIOS_SUCCESSFUL;
646 /* Write to the PCI-to-PCI bridge configuration space */
647 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
648 unsigned int where, int size, u32 value)
650 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
657 mask = ~(0xffff << ((where & 3) * 8));
659 mask = ~(0xff << ((where & 3) * 8));
661 return PCIBIOS_BAD_REGISTER_NUMBER;
663 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
667 value = (reg & mask) | value << ((where & 3) * 8);
669 switch (where & ~3) {
672 u32 old = bridge->command;
674 if (!mvebu_has_ioport(port))
675 value &= ~PCI_COMMAND_IO;
677 bridge->command = value & 0xffff;
678 if ((old ^ bridge->command) & PCI_COMMAND_IO)
679 mvebu_pcie_handle_iobase_change(port);
680 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
681 mvebu_pcie_handle_membase_change(port);
685 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
686 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
691 * We also keep bit 1 set, it is a read-only bit that
692 * indicates we support 32 bits addressing for the
695 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
696 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
697 mvebu_pcie_handle_iobase_change(port);
700 case PCI_MEMORY_BASE:
701 bridge->membase = value & 0xffff;
702 bridge->memlimit = value >> 16;
703 mvebu_pcie_handle_membase_change(port);
706 case PCI_IO_BASE_UPPER16:
707 bridge->iobaseupper = value & 0xffff;
708 bridge->iolimitupper = value >> 16;
709 mvebu_pcie_handle_iobase_change(port);
712 case PCI_PRIMARY_BUS:
713 bridge->primary_bus = value & 0xff;
714 bridge->secondary_bus = (value >> 8) & 0xff;
715 bridge->subordinate_bus = (value >> 16) & 0xff;
716 bridge->secondary_latency_timer = (value >> 24) & 0xff;
717 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
720 case PCISWCAP_EXP_DEVCTL:
722 * Armada370 data says these bits must always
723 * be zero when in root complex mode.
725 value &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
726 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
729 * If the mask is 0xffff0000, then we only want to write
730 * the device control register, rather than clearing the
731 * RW1C bits in the device status register. Mask out the
732 * status register bits.
734 if (mask == 0xffff0000)
737 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
740 case PCISWCAP_EXP_LNKCTL:
742 * If we don't support CLKREQ, we must ensure that the
743 * CLKREQ enable bit always reads zero. Since we haven't
744 * had this capability, and it's dependent on board wiring,
745 * disable it for the time being.
747 value &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
750 * If the mask is 0xffff0000, then we only want to write
751 * the link control register, rather than clearing the
752 * RW1C bits in the link status register. Mask out the
753 * status register bits.
755 if (mask == 0xffff0000)
758 mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
761 case PCISWCAP_EXP_RTSTA:
762 mvebu_writel(port, value, PCIE_RC_RTSTA);
769 return PCIBIOS_SUCCESSFUL;
772 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
774 return sys->private_data;
777 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
783 for (i = 0; i < pcie->nports; i++) {
784 struct mvebu_pcie_port *port = &pcie->ports[i];
786 if (bus->number == 0 && port->devfn == devfn)
788 if (bus->number != 0 &&
789 bus->number >= port->bridge.secondary_bus &&
790 bus->number <= port->bridge.subordinate_bus)
797 /* PCI configuration space write function */
798 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
799 int where, int size, u32 val)
801 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
802 struct mvebu_pcie_port *port;
805 port = mvebu_pcie_find_port(pcie, bus, devfn);
807 return PCIBIOS_DEVICE_NOT_FOUND;
809 /* Access the emulated PCI-to-PCI bridge */
810 if (bus->number == 0)
811 return mvebu_sw_pci_bridge_write(port, where, size, val);
813 if (!mvebu_pcie_link_up(port))
814 return PCIBIOS_DEVICE_NOT_FOUND;
816 /* Access the real PCIe interface */
817 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
823 /* PCI configuration space read function */
824 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
827 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
828 struct mvebu_pcie_port *port;
831 port = mvebu_pcie_find_port(pcie, bus, devfn);
834 return PCIBIOS_DEVICE_NOT_FOUND;
837 /* Access the emulated PCI-to-PCI bridge */
838 if (bus->number == 0)
839 return mvebu_sw_pci_bridge_read(port, where, size, val);
841 if (!mvebu_pcie_link_up(port)) {
843 return PCIBIOS_DEVICE_NOT_FOUND;
846 /* Access the real PCIe interface */
847 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
853 static struct pci_ops mvebu_pcie_ops = {
854 .read = mvebu_pcie_rd_conf,
855 .write = mvebu_pcie_wr_conf,
858 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
860 struct mvebu_pcie *pcie = sys_to_pcie(sys);
863 pcie->mem.name = "PCI MEM";
864 pcie->realio.name = "PCI I/O";
866 if (request_resource(&iomem_resource, &pcie->mem))
869 if (resource_size(&pcie->realio) != 0) {
870 if (request_resource(&ioport_resource, &pcie->realio)) {
871 release_resource(&pcie->mem);
874 pci_add_resource_offset(&sys->resources, &pcie->realio,
877 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
878 pci_add_resource(&sys->resources, &pcie->busn);
880 for (i = 0; i < pcie->nports; i++) {
881 struct mvebu_pcie_port *port = &pcie->ports[i];
885 mvebu_pcie_setup_hw(port);
891 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
892 const struct resource *res,
893 resource_size_t start,
894 resource_size_t size,
895 resource_size_t align)
897 if (dev->bus->number != 0)
901 * On the PCI-to-PCI bridge side, the I/O windows must have at
902 * least a 64 KB size and the memory windows must have at
903 * least a 1 MB size. Moreover, MBus windows need to have a
904 * base address aligned on their size, and their size must be
905 * a power of two. This means that if the BAR doesn't have a
906 * power of two size, several MBus windows will actually be
907 * created. We need to ensure that the biggest MBus window
908 * (which will be the first one) is aligned on its size, which
909 * explains the rounddown_pow_of_two() being done here.
911 if (res->flags & IORESOURCE_IO)
912 return round_up(start, max_t(resource_size_t, SZ_64K,
913 rounddown_pow_of_two(size)));
914 else if (res->flags & IORESOURCE_MEM)
915 return round_up(start, max_t(resource_size_t, SZ_1M,
916 rounddown_pow_of_two(size)));
921 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
925 memset(&hw, 0, sizeof(hw));
927 #ifdef CONFIG_PCI_MSI
928 hw.msi_ctrl = pcie->msi;
931 hw.nr_controllers = 1;
932 hw.private_data = (void **)&pcie;
933 hw.setup = mvebu_pcie_setup;
934 hw.map_irq = of_irq_parse_and_map_pci;
935 hw.ops = &mvebu_pcie_ops;
936 hw.align_resource = mvebu_pcie_align_resource;
938 pci_common_init_dev(&pcie->pdev->dev, &hw);
942 * Looks up the list of register addresses encoded into the reg =
943 * <...> property for one that matches the given port/lane. Once
946 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
947 struct device_node *np,
948 struct mvebu_pcie_port *port)
950 struct resource regs;
953 ret = of_address_to_resource(np, 0, ®s);
957 return devm_ioremap_resource(&pdev->dev, ®s);
960 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
961 #define DT_TYPE_IO 0x1
962 #define DT_TYPE_MEM32 0x2
963 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
964 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
966 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
971 const int na = 3, ns = 2;
973 int rlen, nranges, rangesz, pna, i;
978 range = of_get_property(np, "ranges", &rlen);
982 pna = of_n_addr_cells(np);
983 rangesz = pna + na + ns;
984 nranges = rlen / sizeof(__be32) / rangesz;
986 for (i = 0; i < nranges; i++, range += rangesz) {
987 u32 flags = of_read_number(range, 1);
988 u32 slot = of_read_number(range + 1, 1);
989 u64 cpuaddr = of_read_number(range + na, pna);
992 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
993 rtype = IORESOURCE_IO;
994 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
995 rtype = IORESOURCE_MEM;
999 if (slot == PCI_SLOT(devfn) && type == rtype) {
1000 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
1001 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
1009 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
1011 struct device_node *msi_node;
1013 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
1018 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
1019 of_node_put(msi_node);
1022 pcie->msi->dev = &pcie->pdev->dev;
1025 static int mvebu_pcie_suspend(struct device *dev)
1027 struct mvebu_pcie *pcie;
1030 pcie = dev_get_drvdata(dev);
1031 for (i = 0; i < pcie->nports; i++) {
1032 struct mvebu_pcie_port *port = pcie->ports + i;
1033 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
1039 static int mvebu_pcie_resume(struct device *dev)
1041 struct mvebu_pcie *pcie;
1044 pcie = dev_get_drvdata(dev);
1045 for (i = 0; i < pcie->nports; i++) {
1046 struct mvebu_pcie_port *port = pcie->ports + i;
1047 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
1048 mvebu_pcie_setup_hw(port);
1054 static void mvebu_pcie_port_clk_put(void *data)
1056 struct mvebu_pcie_port *port = data;
1061 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
1062 struct mvebu_pcie_port *port, struct device_node *child)
1064 struct device *dev = &pcie->pdev->dev;
1065 enum of_gpio_flags flags;
1066 int reset_gpio, ret;
1070 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
1071 dev_warn(dev, "ignoring %s, missing pcie-port property\n",
1072 of_node_full_name(child));
1076 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
1079 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
1086 port->devfn = of_pci_get_devfn(child);
1087 if (port->devfn < 0)
1090 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
1091 &port->mem_target, &port->mem_attr);
1093 dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
1098 if (resource_size(&pcie->io) != 0) {
1099 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
1100 &port->io_target, &port->io_attr);
1102 port->io_target = -1;
1106 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
1107 if (reset_gpio == -EPROBE_DEFER) {
1112 if (gpio_is_valid(reset_gpio)) {
1113 unsigned long gpio_flags;
1115 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
1117 if (!port->reset_name) {
1122 if (flags & OF_GPIO_ACTIVE_LOW) {
1123 dev_info(dev, "%s: reset gpio is active low\n",
1124 of_node_full_name(child));
1125 gpio_flags = GPIOF_ACTIVE_LOW |
1128 gpio_flags = GPIOF_OUT_INIT_HIGH;
1131 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
1134 if (ret == -EPROBE_DEFER)
1139 port->reset_gpio = gpio_to_desc(reset_gpio);
1142 port->clk = of_clk_get_by_name(child, NULL);
1143 if (IS_ERR(port->clk)) {
1144 dev_err(dev, "%s: cannot get clock\n", port->name);
1148 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
1159 /* In the case of skipping, we need to free these */
1160 devm_kfree(dev, port->reset_name);
1161 port->reset_name = NULL;
1162 devm_kfree(dev, port->name);
1170 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
1171 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
1172 * of the PCI Express Card Electromechanical Specification, 1.1.
1174 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
1178 ret = clk_prepare_enable(port->clk);
1182 if (port->reset_gpio) {
1183 u32 reset_udelay = 20000;
1185 of_property_read_u32(port->dn, "reset-delay-us",
1190 gpiod_set_value_cansleep(port->reset_gpio, 0);
1191 msleep(reset_udelay / 1000);
1198 * Power down a PCIe port. Strictly, PCIe requires us to place the card
1199 * in D3hot state before asserting PERST#.
1201 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
1203 if (port->reset_gpio)
1204 gpiod_set_value_cansleep(port->reset_gpio, 1);
1206 clk_disable_unprepare(port->clk);
1209 static int mvebu_pcie_probe(struct platform_device *pdev)
1211 struct mvebu_pcie *pcie;
1212 struct device_node *np = pdev->dev.of_node;
1213 struct device_node *child;
1216 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
1222 platform_set_drvdata(pdev, pcie);
1224 /* Get the PCIe memory and I/O aperture */
1225 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
1226 if (resource_size(&pcie->mem) == 0) {
1227 dev_err(&pdev->dev, "invalid memory aperture size\n");
1231 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
1233 if (resource_size(&pcie->io) != 0) {
1234 pcie->realio.flags = pcie->io.flags;
1235 pcie->realio.start = PCIBIOS_MIN_IO;
1236 pcie->realio.end = min_t(resource_size_t,
1238 resource_size(&pcie->io) - 1);
1240 pcie->realio = pcie->io;
1242 /* Get the bus range */
1243 ret = of_pci_parse_bus_range(np, &pcie->busn);
1245 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
1250 num = of_get_available_child_count(pdev->dev.of_node);
1252 pcie->ports = devm_kcalloc(&pdev->dev, num, sizeof(*pcie->ports),
1258 for_each_available_child_of_node(pdev->dev.of_node, child) {
1259 struct mvebu_pcie_port *port = &pcie->ports[i];
1261 ret = mvebu_pcie_parse_port(pcie, port, child);
1265 } else if (ret == 0) {
1274 for (i = 0; i < pcie->nports; i++) {
1275 struct mvebu_pcie_port *port = &pcie->ports[i];
1281 ret = mvebu_pcie_powerup(port);
1285 port->base = mvebu_pcie_map_registers(pdev, child, port);
1286 if (IS_ERR(port->base)) {
1287 dev_err(&pdev->dev, "%s: cannot map registers\n",
1290 mvebu_pcie_powerdown(port);
1294 mvebu_pcie_set_local_dev_nr(port, 1);
1295 mvebu_sw_pci_bridge_init(port);
1300 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
1301 pci_ioremap_io(i, pcie->io.start + i);
1303 mvebu_pcie_msi_enable(pcie);
1304 mvebu_pcie_enable(pcie);
1306 platform_set_drvdata(pdev, pcie);
1311 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1312 { .compatible = "marvell,armada-xp-pcie", },
1313 { .compatible = "marvell,armada-370-pcie", },
1314 { .compatible = "marvell,dove-pcie", },
1315 { .compatible = "marvell,kirkwood-pcie", },
1318 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1320 static struct dev_pm_ops mvebu_pcie_pm_ops = {
1321 .suspend_noirq = mvebu_pcie_suspend,
1322 .resume_noirq = mvebu_pcie_resume,
1325 static struct platform_driver mvebu_pcie_driver = {
1327 .name = "mvebu-pcie",
1328 .of_match_table = mvebu_pcie_of_match_table,
1329 /* driver unloading/unbinding currently not supported */
1330 .suppress_bind_attrs = true,
1331 .pm = &mvebu_pcie_pm_ops,
1333 .probe = mvebu_pcie_probe,
1335 module_platform_driver(mvebu_pcie_driver);
1337 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1338 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1339 MODULE_LICENSE("GPL v2");