2 * Driver for the Aardvark PCIe controller, used on Marvell Armada
5 * Copyright (C) 2016 Marvell
7 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/of_address.h>
24 #include <linux/of_gpio.h>
25 #include <linux/of_pci.h>
27 /* PCIe core registers */
28 #define PCIE_CORE_CMD_STATUS_REG 0x4
29 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
30 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
31 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
32 #define PCIE_CORE_PCIEXP_CAP 0xc0
33 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
34 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
35 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
36 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
39 /* PIO registers base address and register offsets */
40 #define PIO_BASE_ADDR 0x4000
41 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
42 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
43 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
44 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
45 #define PIO_COMPLETION_STATUS_SHIFT 7
46 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
47 #define PIO_COMPLETION_STATUS_OK 0
48 #define PIO_COMPLETION_STATUS_UR 1
49 #define PIO_COMPLETION_STATUS_CRS 2
50 #define PIO_COMPLETION_STATUS_CA 4
51 #define PIO_NON_POSTED_REQ BIT(10)
52 #define PIO_ERR_STATUS BIT(11)
53 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
54 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
55 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
56 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
57 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
58 #define PIO_START (PIO_BASE_ADDR + 0x1c)
59 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
60 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
62 /* Aardvark Control registers */
63 #define CONTROL_BASE_ADDR 0x4800
64 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
65 #define PCIE_GEN_SEL_MSK 0x3
66 #define PCIE_GEN_SEL_SHIFT 0x0
72 #define LANE_CNT_MSK 0x18
73 #define LANE_CNT_SHIFT 0x3
74 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
75 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
76 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
77 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
78 #define LINK_TRAINING_EN BIT(6)
79 #define LEGACY_INTA BIT(28)
80 #define LEGACY_INTB BIT(29)
81 #define LEGACY_INTC BIT(30)
82 #define LEGACY_INTD BIT(31)
83 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
84 #define HOT_RESET_GEN BIT(0)
85 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
86 #define PCIE_CORE_CTRL2_RESERVED 0x7
87 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
88 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
89 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
90 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
91 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
92 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
93 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
94 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
95 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
96 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
97 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
98 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
99 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
100 #define PCIE_ISR1_FLUSH BIT(5)
101 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
102 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
103 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
104 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
105 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
106 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
107 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
108 #define PCIE_MSI_DATA_MASK GENMASK(15, 0)
110 /* PCIe window configuration */
111 #define OB_WIN_BASE_ADDR 0x4c00
112 #define OB_WIN_BLOCK_SIZE 0x20
113 #define OB_WIN_COUNT 8
114 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
115 OB_WIN_BLOCK_SIZE * (win) + \
117 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
118 #define OB_WIN_ENABLE BIT(0)
119 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
120 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
121 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
122 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
123 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
124 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
125 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
126 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
127 #define OB_WIN_FUNC_NUM_SHIFT 24
128 #define OB_WIN_FUNC_NUM_ENABLE BIT(23)
129 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
130 #define OB_WIN_BUS_NUM_BITS_SHIFT 20
131 #define OB_WIN_MSG_CODE_ENABLE BIT(22)
132 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
133 #define OB_WIN_MSG_CODE_SHIFT 14
134 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
135 #define OB_WIN_ATTR_ENABLE BIT(11)
136 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
137 #define OB_WIN_ATTR_TC_SHIFT 8
138 #define OB_WIN_ATTR_RELAXED BIT(7)
139 #define OB_WIN_ATTR_NOSNOOP BIT(6)
140 #define OB_WIN_ATTR_POISON BIT(5)
141 #define OB_WIN_ATTR_IDO BIT(4)
142 #define OB_WIN_TYPE_MASK GENMASK(3, 0)
143 #define OB_WIN_TYPE_SHIFT 0
144 #define OB_WIN_TYPE_MEM 0x0
145 #define OB_WIN_TYPE_IO 0x4
146 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
147 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
148 #define OB_WIN_TYPE_MSG 0xc
150 /* LMI registers base address and register offsets */
151 #define LMI_BASE_ADDR 0x6000
152 #define CFG_REG (LMI_BASE_ADDR + 0x0)
153 #define LTSSM_SHIFT 24
154 #define LTSSM_MASK 0x3f
155 #define RC_BAR_CONFIG 0x300
157 /* LTSSM values in CFG_REG */
159 LTSSM_DETECT_QUIET = 0x0,
160 LTSSM_DETECT_ACTIVE = 0x1,
161 LTSSM_POLLING_ACTIVE = 0x2,
162 LTSSM_POLLING_COMPLIANCE = 0x3,
163 LTSSM_POLLING_CONFIGURATION = 0x4,
164 LTSSM_CONFIG_LINKWIDTH_START = 0x5,
165 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
166 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
167 LTSSM_CONFIG_LANENUM_WAIT = 0x8,
168 LTSSM_CONFIG_COMPLETE = 0x9,
169 LTSSM_CONFIG_IDLE = 0xa,
170 LTSSM_RECOVERY_RCVR_LOCK = 0xb,
171 LTSSM_RECOVERY_SPEED = 0xc,
172 LTSSM_RECOVERY_RCVR_CFG = 0xd,
173 LTSSM_RECOVERY_IDLE = 0xe,
175 LTSSM_RX_L0S_ENTRY = 0x11,
176 LTSSM_RX_L0S_IDLE = 0x12,
177 LTSSM_RX_L0S_FTS = 0x13,
178 LTSSM_TX_L0S_ENTRY = 0x14,
179 LTSSM_TX_L0S_IDLE = 0x15,
180 LTSSM_TX_L0S_FTS = 0x16,
181 LTSSM_L1_ENTRY = 0x17,
182 LTSSM_L1_IDLE = 0x18,
183 LTSSM_L2_IDLE = 0x19,
184 LTSSM_L2_TRANSMIT_WAKE = 0x1a,
185 LTSSM_DISABLED = 0x20,
186 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
187 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
188 LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
189 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
190 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
191 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
192 LTSSM_HOT_RESET = 0x27,
193 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
194 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
195 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
196 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
199 /* PCIe core controller registers */
200 #define CTRL_CORE_BASE_ADDR 0x18000
201 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
202 #define CTRL_MODE_SHIFT 0x0
203 #define CTRL_MODE_MASK 0x1
204 #define PCIE_CORE_MODE_DIRECT 0x0
205 #define PCIE_CORE_MODE_COMMAND 0x1
207 /* PCIe Central Interrupts Registers */
208 #define CENTRAL_INT_BASE_ADDR 0x1b000
209 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
210 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
211 #define PCIE_IRQ_CMDQ_INT BIT(0)
212 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
213 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
214 #define PCIE_IRQ_DMA_INT BIT(4)
215 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
216 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
217 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
218 #define PCIE_IRQ_COMPQ_INT BIT(12)
219 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
220 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
221 #define PCIE_IRQ_CORE_INT BIT(16)
222 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
223 #define PCIE_IRQ_DPMU_INT BIT(18)
224 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
225 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
226 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
227 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
228 #define PCIE_IRQ_EP_STATUS BIT(23)
229 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
230 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
232 /* Transaction types */
233 #define PCIE_CONFIG_RD_TYPE0 0x8
234 #define PCIE_CONFIG_RD_TYPE1 0x9
235 #define PCIE_CONFIG_WR_TYPE0 0xa
236 #define PCIE_CONFIG_WR_TYPE1 0xb
238 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
239 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
240 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
241 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
242 #define PCIE_CONF_ADDR(bus, devfn, where) \
243 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
244 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
246 #define PIO_RETRY_CNT 750000 /* 1.5 s */
247 #define PIO_RETRY_DELAY 2 /* 2 us*/
249 #define LINK_WAIT_MAX_RETRIES 10
250 #define LINK_WAIT_USLEEP_MIN 90000
251 #define LINK_WAIT_USLEEP_MAX 100000
253 #define MSI_IRQ_NUM 32
256 struct platform_device *pdev;
258 struct list_head resources;
264 } wins[OB_WIN_COUNT];
266 struct irq_domain *irq_domain;
267 struct irq_chip irq_chip;
268 raw_spinlock_t irq_lock;
269 struct irq_domain *msi_domain;
270 struct irq_domain *msi_inner_domain;
271 struct irq_chip msi_bottom_irq_chip;
272 struct irq_chip msi_irq_chip;
273 struct msi_domain_info msi_domain_info;
274 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
275 struct mutex msi_used_lock;
279 struct gpio_desc *reset_gpio;
282 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
284 writel(val, pcie->base + reg);
287 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
289 return readl(pcie->base + reg);
292 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
297 val = advk_readl(pcie, CFG_REG);
298 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
302 static inline bool advk_pcie_link_up(struct advk_pcie *pcie)
304 /* check if LTSSM is in normal operation - some L* state */
305 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
306 return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
309 static inline bool advk_pcie_link_training(struct advk_pcie *pcie)
312 * According to PCIe Base specification 3.0, Table 4-14: Link
313 * Status Mapped to the LTSSM is Link Training mapped to LTSSM
314 * Configuration and Recovery states.
316 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
317 return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START &&
318 ltssm_state < LTSSM_L0) ||
319 (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 &&
320 ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3));
323 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
327 /* check if the link is up or not */
328 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
329 if (advk_pcie_link_up(pcie))
332 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
338 static void advk_pcie_issue_perst(struct advk_pcie *pcie)
340 if (!pcie->reset_gpio)
343 /* 10ms delay is needed for some cards */
344 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
345 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
346 usleep_range(10000, 11000);
347 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
350 static void advk_pcie_train_link(struct advk_pcie *pcie)
352 struct device *dev = &pcie->pdev->dev;
357 * Setup PCIe rev / gen compliance based on device tree property
358 * 'max-link-speed' which also forces maximal link speed.
360 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
361 reg &= ~PCIE_GEN_SEL_MSK;
362 if (pcie->link_gen == 3)
364 else if (pcie->link_gen == 2)
368 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
371 * Set maximal link speed value also into PCIe Link Control 2 register.
372 * Armada 3700 Functional Specification says that default value is based
373 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s.
375 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
376 reg &= ~PCI_EXP_LNKCTL2_TLS;
377 if (pcie->link_gen == 3)
378 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;
379 else if (pcie->link_gen == 2)
380 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;
382 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;
383 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
385 /* Enable link training after selecting PCIe generation */
386 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
387 reg |= LINK_TRAINING_EN;
388 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
391 * Reset PCIe card via PERST# signal. Some cards are not detected
392 * during link training when they are in some non-initial state.
394 advk_pcie_issue_perst(pcie);
397 * PERST# signal could have been asserted by pinctrl subsystem before
398 * probe() callback has been called or issued explicitly by reset gpio
399 * function advk_pcie_issue_perst(), making the endpoint going into
400 * fundamental reset. As required by PCI Express spec (PCI Express
401 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1
402 * Conventional Reset) a delay for at least 100ms after such a reset
403 * before sending a Configuration Request to the device is needed.
404 * So wait until PCIe link is up. Function advk_pcie_wait_for_link()
405 * waits for link at least 900ms.
407 ret = advk_pcie_wait_for_link(pcie);
409 dev_err(dev, "link never came up\n");
411 dev_info(dev, "link up\n");
415 * Set PCIe address window register which could be used for memory
418 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num,
419 phys_addr_t match, phys_addr_t remap,
420 phys_addr_t mask, u32 actions)
422 advk_writel(pcie, OB_WIN_ENABLE |
423 lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
424 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
425 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
426 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
427 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
428 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
429 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
432 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num)
434 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
435 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
436 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
437 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
438 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
439 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
440 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
443 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
448 /* Set to Direct mode */
449 reg = advk_readl(pcie, CTRL_CONFIG_REG);
450 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
451 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
452 advk_writel(pcie, reg, CTRL_CONFIG_REG);
454 /* Set PCI global control register to RC mode */
455 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
456 reg |= (IS_RC_MSK << IS_RC_SHIFT);
457 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
459 /* Set Advanced Error Capabilities and Control PF0 register */
460 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
461 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
462 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
463 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
464 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
466 /* Set PCIe Device Control register */
467 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
468 reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
469 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
470 reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
471 reg &= ~PCI_EXP_DEVCTL_READRQ;
472 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
473 reg |= PCI_EXP_DEVCTL_READRQ_512B;
474 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
476 /* Program PCIe Control 2 to disable strict ordering */
477 reg = PCIE_CORE_CTRL2_RESERVED |
478 PCIE_CORE_CTRL2_TD_ENABLE;
479 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
482 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
483 reg &= ~LANE_CNT_MSK;
485 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
488 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
489 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
490 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
492 /* Clear all interrupts */
493 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
494 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
495 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
497 /* Disable All ISR0/1 Sources */
498 reg = PCIE_ISR0_ALL_MASK;
499 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
500 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
502 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
504 /* Unmask all MSI's */
505 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
507 /* Enable summary interrupt for GIC SPI source */
508 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
509 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
512 * Enable AXI address window location generation:
513 * When it is enabled, the default outbound window
514 * configurations (Default User Field: 0xD0074CFC)
515 * are used to transparent address translation for
516 * the outbound transactions. Thus, PCIe address
517 * windows are not required for transparent memory
518 * access when default outbound window configuration
519 * is set for memory access.
521 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
522 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
523 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
526 * Set memory access in Default User Field so it
527 * is not required to configure PCIe address for
528 * transparent memory access.
530 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
533 * Bypass the address window mapping for PIO:
534 * Since PIO access already contains all required
535 * info over AXI interface by PIO registers, the
536 * address window is not required.
538 reg = advk_readl(pcie, PIO_CTRL);
539 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
540 advk_writel(pcie, reg, PIO_CTRL);
543 * Configure PCIe address windows for non-memory or
544 * non-transparent access as by default PCIe uses
545 * transparent memory access.
547 for (i = 0; i < pcie->wins_count; i++)
548 advk_pcie_set_ob_win(pcie, i,
549 pcie->wins[i].match, pcie->wins[i].remap,
550 pcie->wins[i].mask, pcie->wins[i].actions);
552 /* Disable remaining PCIe outbound windows */
553 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
554 advk_pcie_disable_ob_win(pcie, i);
556 advk_pcie_train_link(pcie);
558 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
559 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
560 PCIE_CORE_CMD_IO_ACCESS_EN |
561 PCIE_CORE_CMD_MEM_IO_REQ_EN;
562 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
565 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, u32 *val)
567 struct device *dev = &pcie->pdev->dev;
570 char *strcomp_status, *str_posted;
572 reg = advk_readl(pcie, PIO_STAT);
573 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
574 PIO_COMPLETION_STATUS_SHIFT;
577 * According to HW spec, the PIO status check sequence as below:
578 * 1) even if COMPLETION_STATUS(bit9:7) indicates successful,
579 * it still needs to check Error Status(bit11), only when this bit
580 * indicates no error happen, the operation is successful.
581 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only
582 * means a PIO write error, and for PIO read it is successful with
583 * a read value of 0xFFFFFFFF.
584 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7)
585 * only means a PIO write error, and for PIO read it is successful
586 * with a read value of 0xFFFF0001.
587 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means
588 * error for both PIO read and PIO write operation.
589 * 5) other errors are indicated as 'unknown'.
592 case PIO_COMPLETION_STATUS_OK:
593 if (reg & PIO_ERR_STATUS) {
594 strcomp_status = "COMP_ERR";
597 /* Get the read result */
599 *val = advk_readl(pcie, PIO_RD_DATA);
601 strcomp_status = NULL;
603 case PIO_COMPLETION_STATUS_UR:
604 strcomp_status = "UR";
606 case PIO_COMPLETION_STATUS_CRS:
607 /* PCIe r4.0, sec 2.3.2, says:
608 * If CRS Software Visibility is not enabled, the Root Complex
609 * must re-issue the Configuration Request as a new Request.
610 * A Root Complex implementation may choose to limit the number
611 * of Configuration Request/CRS Completion Status loops before
612 * determining that something is wrong with the target of the
613 * Request and taking appropriate action, e.g., complete the
614 * Request to the host as a failed transaction.
616 * To simplify implementation do not re-issue the Configuration
617 * Request and complete the Request as a failed transaction.
619 strcomp_status = "CRS";
621 case PIO_COMPLETION_STATUS_CA:
622 strcomp_status = "CA";
625 strcomp_status = "Unknown";
632 if (reg & PIO_NON_POSTED_REQ)
633 str_posted = "Non-posted";
635 str_posted = "Posted";
637 dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
638 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
643 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
645 struct device *dev = &pcie->pdev->dev;
648 for (i = 0; i < PIO_RETRY_CNT; i++) {
651 start = advk_readl(pcie, PIO_START);
652 isr = advk_readl(pcie, PIO_ISR);
655 udelay(PIO_RETRY_DELAY);
658 dev_err(dev, "PIO read/write transfer time out\n");
662 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
664 struct device *dev = &pcie->pdev->dev;
667 * Trying to start a new PIO transfer when previous has not completed
668 * cause External Abort on CPU which results in kernel panic:
670 * SError Interrupt on CPU0, code 0xbf000002 -- SError
671 * Kernel panic - not syncing: Asynchronous SError Interrupt
673 * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected
674 * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent
675 * concurrent calls at the same time. But because PIO transfer may take
676 * about 1.5s when link is down or card is disconnected, it means that
677 * advk_pcie_wait_pio() does not always have to wait for completion.
679 * Some versions of ARM Trusted Firmware handles this External Abort at
680 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:
681 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
683 if (advk_readl(pcie, PIO_START)) {
684 dev_err(dev, "Previous PIO read/write transfer is still running\n");
691 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
694 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
698 * If the link goes down after we check for link-up, nothing bad
699 * happens but the config access times out.
701 if (bus->number != pcie->root_bus_nr && !advk_pcie_link_up(pcie))
707 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
708 int where, int size, u32 *val)
710 struct advk_pcie *pcie = bus->sysdata;
714 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
716 return PCIBIOS_DEVICE_NOT_FOUND;
719 if (advk_pcie_pio_is_running(pcie)) {
721 return PCIBIOS_SET_FAILED;
724 /* Program the control register */
725 reg = advk_readl(pcie, PIO_CTRL);
726 reg &= ~PIO_CTRL_TYPE_MASK;
727 if (bus->number == pcie->root_bus_nr)
728 reg |= PCIE_CONFIG_RD_TYPE0;
730 reg |= PCIE_CONFIG_RD_TYPE1;
731 advk_writel(pcie, reg, PIO_CTRL);
733 /* Program the address registers */
734 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
735 advk_writel(pcie, reg, PIO_ADDR_LS);
736 advk_writel(pcie, 0, PIO_ADDR_MS);
738 /* Program the data strobe */
739 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
741 /* Clear PIO DONE ISR and start the transfer */
742 advk_writel(pcie, 1, PIO_ISR);
743 advk_writel(pcie, 1, PIO_START);
745 ret = advk_pcie_wait_pio(pcie);
748 return PCIBIOS_SET_FAILED;
751 /* Check PIO status and get the read result */
752 ret = advk_pcie_check_pio_status(pcie, val);
755 return PCIBIOS_SET_FAILED;
759 *val = (*val >> (8 * (where & 3))) & 0xff;
761 *val = (*val >> (8 * (where & 3))) & 0xffff;
763 return PCIBIOS_SUCCESSFUL;
766 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
767 int where, int size, u32 val)
769 struct advk_pcie *pcie = bus->sysdata;
771 u32 data_strobe = 0x0;
775 if (!advk_pcie_valid_device(pcie, bus, devfn))
776 return PCIBIOS_DEVICE_NOT_FOUND;
779 return PCIBIOS_SET_FAILED;
781 if (advk_pcie_pio_is_running(pcie))
782 return PCIBIOS_SET_FAILED;
784 /* Program the control register */
785 reg = advk_readl(pcie, PIO_CTRL);
786 reg &= ~PIO_CTRL_TYPE_MASK;
787 if (bus->number == pcie->root_bus_nr)
788 reg |= PCIE_CONFIG_WR_TYPE0;
790 reg |= PCIE_CONFIG_WR_TYPE1;
791 advk_writel(pcie, reg, PIO_CTRL);
793 /* Program the address registers */
794 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
795 advk_writel(pcie, reg, PIO_ADDR_LS);
796 advk_writel(pcie, 0, PIO_ADDR_MS);
798 /* Calculate the write strobe */
799 offset = where & 0x3;
800 reg = val << (8 * offset);
801 data_strobe = GENMASK(size - 1, 0) << offset;
803 /* Program the data register */
804 advk_writel(pcie, reg, PIO_WR_DATA);
806 /* Program the data strobe */
807 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
809 /* Clear PIO DONE ISR and start the transfer */
810 advk_writel(pcie, 1, PIO_ISR);
811 advk_writel(pcie, 1, PIO_START);
813 ret = advk_pcie_wait_pio(pcie);
815 return PCIBIOS_SET_FAILED;
817 ret = advk_pcie_check_pio_status(pcie, NULL);
819 return PCIBIOS_SET_FAILED;
821 return PCIBIOS_SUCCESSFUL;
824 static struct pci_ops advk_pcie_ops = {
825 .read = advk_pcie_rd_conf,
826 .write = advk_pcie_wr_conf,
829 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
832 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
833 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
835 msg->address_lo = lower_32_bits(msi_msg);
836 msg->address_hi = upper_32_bits(msi_msg);
837 msg->data = data->irq;
840 static int advk_msi_set_affinity(struct irq_data *irq_data,
841 const struct cpumask *mask, bool force)
846 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
848 unsigned int nr_irqs, void *args)
850 struct advk_pcie *pcie = domain->host_data;
853 mutex_lock(&pcie->msi_used_lock);
854 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
856 if (hwirq >= MSI_IRQ_NUM) {
857 mutex_unlock(&pcie->msi_used_lock);
861 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
862 mutex_unlock(&pcie->msi_used_lock);
864 for (i = 0; i < nr_irqs; i++)
865 irq_domain_set_info(domain, virq + i, hwirq + i,
866 &pcie->msi_bottom_irq_chip,
867 domain->host_data, handle_simple_irq,
873 static void advk_msi_irq_domain_free(struct irq_domain *domain,
874 unsigned int virq, unsigned int nr_irqs)
876 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
877 struct advk_pcie *pcie = domain->host_data;
879 mutex_lock(&pcie->msi_used_lock);
880 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
881 mutex_unlock(&pcie->msi_used_lock);
884 static const struct irq_domain_ops advk_msi_domain_ops = {
885 .alloc = advk_msi_irq_domain_alloc,
886 .free = advk_msi_irq_domain_free,
889 static void advk_pcie_irq_mask(struct irq_data *d)
891 struct advk_pcie *pcie = d->domain->host_data;
892 irq_hw_number_t hwirq = irqd_to_hwirq(d);
896 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
897 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
898 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
899 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
900 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
903 static void advk_pcie_irq_unmask(struct irq_data *d)
905 struct advk_pcie *pcie = d->domain->host_data;
906 irq_hw_number_t hwirq = irqd_to_hwirq(d);
910 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
911 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
912 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
913 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
914 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
917 static int advk_pcie_irq_map(struct irq_domain *h,
918 unsigned int virq, irq_hw_number_t hwirq)
920 struct advk_pcie *pcie = h->host_data;
922 advk_pcie_irq_mask(irq_get_irq_data(virq));
923 irq_set_status_flags(virq, IRQ_LEVEL);
924 irq_set_chip_and_handler(virq, &pcie->irq_chip,
926 irq_set_chip_data(virq, pcie);
931 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
932 .map = advk_pcie_irq_map,
933 .xlate = irq_domain_xlate_onecell,
936 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
938 struct device *dev = &pcie->pdev->dev;
939 struct device_node *node = dev->of_node;
940 struct irq_chip *bottom_ic, *msi_ic;
941 struct msi_domain_info *msi_di;
942 phys_addr_t msi_msg_phys;
944 mutex_init(&pcie->msi_used_lock);
946 bottom_ic = &pcie->msi_bottom_irq_chip;
948 bottom_ic->name = "MSI";
949 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
950 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
952 msi_ic = &pcie->msi_irq_chip;
953 msi_ic->name = "advk-MSI";
955 msi_di = &pcie->msi_domain_info;
956 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
957 MSI_FLAG_MULTI_PCI_MSI;
958 msi_di->chip = msi_ic;
960 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
962 advk_writel(pcie, lower_32_bits(msi_msg_phys),
963 PCIE_MSI_ADDR_LOW_REG);
964 advk_writel(pcie, upper_32_bits(msi_msg_phys),
965 PCIE_MSI_ADDR_HIGH_REG);
967 pcie->msi_inner_domain =
968 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
969 &advk_msi_domain_ops, pcie);
970 if (!pcie->msi_inner_domain)
974 pci_msi_create_irq_domain(of_node_to_fwnode(node),
975 msi_di, pcie->msi_inner_domain);
976 if (!pcie->msi_domain) {
977 irq_domain_remove(pcie->msi_inner_domain);
984 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
986 irq_domain_remove(pcie->msi_domain);
987 irq_domain_remove(pcie->msi_inner_domain);
990 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
992 struct device *dev = &pcie->pdev->dev;
993 struct device_node *node = dev->of_node;
994 struct device_node *pcie_intc_node;
995 struct irq_chip *irq_chip;
998 raw_spin_lock_init(&pcie->irq_lock);
1000 pcie_intc_node = of_get_next_child(node, NULL);
1001 if (!pcie_intc_node) {
1002 dev_err(dev, "No PCIe Intc node found\n");
1006 irq_chip = &pcie->irq_chip;
1008 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
1010 if (!irq_chip->name) {
1015 irq_chip->irq_mask = advk_pcie_irq_mask;
1016 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
1017 irq_chip->irq_unmask = advk_pcie_irq_unmask;
1020 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
1021 &advk_pcie_irq_domain_ops, pcie);
1022 if (!pcie->irq_domain) {
1023 dev_err(dev, "Failed to get a INTx IRQ domain\n");
1029 of_node_put(pcie_intc_node);
1033 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
1035 irq_domain_remove(pcie->irq_domain);
1038 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
1040 u32 msi_val, msi_mask, msi_status, msi_idx;
1043 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1044 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
1045 msi_status = msi_val & ~msi_mask;
1047 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
1048 if (!(BIT(msi_idx) & msi_status))
1052 * msi_idx contains bits [4:0] of the msi_data and msi_data
1053 * contains 16bit MSI interrupt number
1055 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
1056 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
1057 generic_handle_irq(msi_data);
1060 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
1064 static void advk_pcie_handle_int(struct advk_pcie *pcie)
1066 u32 isr0_val, isr0_mask, isr0_status;
1067 u32 isr1_val, isr1_mask, isr1_status;
1070 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1071 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1072 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
1074 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1075 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1076 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
1078 /* Process MSI interrupts */
1079 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1080 advk_pcie_handle_msi(pcie);
1082 /* Process legacy interrupts */
1083 for (i = 0; i < PCI_NUM_INTX; i++) {
1084 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1087 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1090 virq = irq_find_mapping(pcie->irq_domain, i);
1091 generic_handle_irq(virq);
1095 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
1097 struct advk_pcie *pcie = arg;
1100 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1101 if (!(status & PCIE_IRQ_CORE_INT))
1104 advk_pcie_handle_int(pcie);
1106 /* Clear interrupt */
1107 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1112 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
1114 int err, res_valid = 0;
1115 struct device *dev = &pcie->pdev->dev;
1116 struct device_node *np = dev->of_node;
1117 struct resource_entry *win, *tmp;
1118 resource_size_t iobase;
1120 INIT_LIST_HEAD(&pcie->resources);
1122 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
1127 err = devm_request_pci_bus_resources(dev, &pcie->resources);
1129 goto out_release_res;
1131 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
1132 struct resource *res = win->res;
1134 switch (resource_type(res)) {
1136 err = devm_pci_remap_iospace(dev, res, iobase);
1138 dev_warn(dev, "error %d: failed to map resource %pR\n",
1140 resource_list_destroy_entry(win);
1143 case IORESOURCE_MEM:
1144 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
1146 case IORESOURCE_BUS:
1147 pcie->root_bus_nr = res->start;
1153 dev_err(dev, "non-prefetchable memory resource required\n");
1155 goto out_release_res;
1161 pci_free_resource_list(&pcie->resources);
1165 static int advk_pcie_probe(struct platform_device *pdev)
1167 struct device *dev = &pdev->dev;
1168 struct advk_pcie *pcie;
1169 struct resource *res;
1170 struct pci_bus *bus, *child;
1171 struct pci_host_bridge *bridge;
1172 struct resource_entry *entry;
1175 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1179 pcie = pci_host_bridge_priv(bridge);
1182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 pcie->base = devm_ioremap_resource(dev, res);
1184 if (IS_ERR(pcie->base))
1185 return PTR_ERR(pcie->base);
1187 irq = platform_get_irq(pdev, 0);
1188 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
1189 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1192 dev_err(dev, "Failed to register interrupt\n");
1196 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
1198 dev_err(dev, "Failed to parse resources\n");
1202 resource_list_for_each_entry(entry, &pcie->resources) {
1203 resource_size_t start = entry->res->start;
1204 resource_size_t size = resource_size(entry->res);
1205 unsigned long type = resource_type(entry->res);
1209 * Aardvark hardware allows to configure also PCIe window
1210 * for config type 0 and type 1 mapping, but driver uses
1211 * only PIO for issuing configuration transfers which does
1212 * not use PCIe window configuration.
1214 if (type != IORESOURCE_MEM && type != IORESOURCE_MEM_64 &&
1215 type != IORESOURCE_IO)
1219 * Skip transparent memory resources. Default outbound access
1220 * configuration is set to transparent memory access so it
1221 * does not need window configuration.
1223 if ((type == IORESOURCE_MEM || type == IORESOURCE_MEM_64) &&
1228 * The n-th PCIe window is configured by tuple (match, remap, mask)
1229 * and an access to address A uses this window if A matches the
1230 * match with given mask.
1231 * So every PCIe window size must be a power of two and every start
1232 * address must be aligned to window size. Minimal size is 64 KiB
1233 * because lower 16 bits of mask must be zero. Remapped address
1234 * may have set only bits from the mask.
1236 while (pcie->wins_count < OB_WIN_COUNT && size > 0) {
1237 /* Calculate the largest aligned window size */
1238 win_size = (1ULL << (fls64(size)-1)) |
1239 (start ? (1ULL << __ffs64(start)) : 0);
1240 win_size = 1ULL << __ffs64(win_size);
1241 if (win_size < 0x10000)
1245 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n",
1246 pcie->wins_count, (unsigned long long)start,
1247 (unsigned long long)start + win_size, type);
1249 if (type == IORESOURCE_IO) {
1250 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO;
1251 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start);
1253 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM;
1254 pcie->wins[pcie->wins_count].match = start;
1256 pcie->wins[pcie->wins_count].remap = start - entry->offset;
1257 pcie->wins[pcie->wins_count].mask = ~(win_size - 1);
1259 if (pcie->wins[pcie->wins_count].remap & (win_size - 1))
1268 dev_err(&pcie->pdev->dev,
1269 "Invalid PCIe region [0x%llx-0x%llx]\n",
1270 (unsigned long long)entry->res->start,
1271 (unsigned long long)entry->res->end + 1);
1276 pcie->reset_gpio = devm_fwnode_get_index_gpiod_from_child(dev, "reset",
1281 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1283 if (ret == -ENOENT) {
1284 pcie->reset_gpio = NULL;
1286 if (ret != -EPROBE_DEFER)
1287 dev_err(dev, "Failed to get reset-gpio: %i\n",
1293 ret = of_pci_get_max_link_speed(dev->of_node);
1294 if (ret <= 0 || ret > 3)
1297 pcie->link_gen = ret;
1299 advk_pcie_setup_hw(pcie);
1301 ret = advk_pcie_init_irq_domain(pcie);
1303 dev_err(dev, "Failed to initialize irq\n");
1307 ret = advk_pcie_init_msi_irq_domain(pcie);
1309 dev_err(dev, "Failed to initialize irq\n");
1310 advk_pcie_remove_irq_domain(pcie);
1314 list_splice_init(&pcie->resources, &bridge->windows);
1315 bridge->dev.parent = dev;
1316 bridge->sysdata = pcie;
1318 bridge->ops = &advk_pcie_ops;
1319 bridge->map_irq = of_irq_parse_and_map_pci;
1320 bridge->swizzle_irq = pci_common_swizzle;
1322 ret = pci_scan_root_bus_bridge(bridge);
1324 advk_pcie_remove_msi_irq_domain(pcie);
1325 advk_pcie_remove_irq_domain(pcie);
1331 pci_bus_size_bridges(bus);
1332 pci_bus_assign_resources(bus);
1334 list_for_each_entry(child, &bus->children, node)
1335 pcie_bus_configure_settings(child);
1337 pci_bus_add_devices(bus);
1341 static const struct of_device_id advk_pcie_of_match_table[] = {
1342 { .compatible = "marvell,armada-3700-pcie", },
1346 static struct platform_driver advk_pcie_driver = {
1348 .name = "advk-pcie",
1349 .of_match_table = advk_pcie_of_match_table,
1350 /* Driver unloading/unbinding currently not supported */
1351 .suppress_bind_attrs = true,
1353 .probe = advk_pcie_probe,
1355 builtin_platform_driver(advk_pcie_driver);