2 * Synopsys DesignWare PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/delay.h>
16 #include <linux/types.h>
18 #include "pcie-designware.h"
20 /* PCIe Port Logic registers */
21 #define PLR_OFFSET 0x700
22 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
23 #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
24 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
26 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
28 if ((uintptr_t)addr & (size - 1)) {
30 return PCIBIOS_BAD_REGISTER_NUMBER;
35 } else if (size == 2) {
37 } else if (size == 1) {
41 return PCIBIOS_BAD_REGISTER_NUMBER;
44 return PCIBIOS_SUCCESSFUL;
47 int dw_pcie_write(void __iomem *addr, int size, u32 val)
49 if ((uintptr_t)addr & (size - 1))
50 return PCIBIOS_BAD_REGISTER_NUMBER;
59 return PCIBIOS_BAD_REGISTER_NUMBER;
61 return PCIBIOS_SUCCESSFUL;
64 u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
70 if (pci->ops->read_dbi)
71 return pci->ops->read_dbi(pci, base, reg, size);
73 ret = dw_pcie_read(base + reg, size, &val);
75 dev_err(pci->dev, "read DBI address failed\n");
80 void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
85 if (pci->ops->write_dbi) {
86 pci->ops->write_dbi(pci, base, reg, size, val);
90 ret = dw_pcie_write(base + reg, size, val);
92 dev_err(pci->dev, "write DBI address failed\n");
95 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
97 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
99 return dw_pcie_readl_dbi(pci, offset + reg);
102 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
105 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
107 dw_pcie_writel_dbi(pci, offset + reg, val);
110 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
111 int type, u64 cpu_addr,
112 u64 pci_addr, u32 size)
116 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
117 lower_32_bits(cpu_addr));
118 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
119 upper_32_bits(cpu_addr));
120 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
121 lower_32_bits(cpu_addr + size - 1));
122 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
123 lower_32_bits(pci_addr));
124 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
125 upper_32_bits(pci_addr));
126 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
128 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
132 * Make sure ATU enable takes effect before any subsequent config
135 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
136 val = dw_pcie_readl_ob_unroll(pci, index,
137 PCIE_ATU_UNR_REGION_CTRL2);
138 if (val & PCIE_ATU_ENABLE)
141 mdelay(LINK_WAIT_IATU);
143 dev_err(pci->dev, "outbound iATU is not being enabled\n");
146 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
147 u64 cpu_addr, u64 pci_addr, u32 size)
151 if (pci->ops->cpu_addr_fixup)
152 cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
154 if (pci->iatu_unroll_enabled) {
155 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
160 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
161 PCIE_ATU_REGION_OUTBOUND | index);
162 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
163 lower_32_bits(cpu_addr));
164 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
165 upper_32_bits(cpu_addr));
166 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
167 lower_32_bits(cpu_addr + size - 1));
168 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
169 lower_32_bits(pci_addr));
170 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
171 upper_32_bits(pci_addr));
172 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
173 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
176 * Make sure ATU enable takes effect before any subsequent config
179 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
180 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
181 if (val & PCIE_ATU_ENABLE)
184 mdelay(LINK_WAIT_IATU);
186 dev_err(pci->dev, "outbound iATU is not being enabled\n");
189 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
191 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
193 return dw_pcie_readl_dbi(pci, offset + reg);
196 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
199 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
201 dw_pcie_writel_dbi(pci, offset + reg, val);
204 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
205 int bar, u64 cpu_addr,
206 enum dw_pcie_as_type as_type)
211 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
212 lower_32_bits(cpu_addr));
213 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
214 upper_32_bits(cpu_addr));
218 type = PCIE_ATU_TYPE_MEM;
221 type = PCIE_ATU_TYPE_IO;
227 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
228 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
230 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
233 * Make sure ATU enable takes effect before any subsequent config
236 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
237 val = dw_pcie_readl_ib_unroll(pci, index,
238 PCIE_ATU_UNR_REGION_CTRL2);
239 if (val & PCIE_ATU_ENABLE)
242 mdelay(LINK_WAIT_IATU);
244 dev_err(pci->dev, "inbound iATU is not being enabled\n");
249 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
250 u64 cpu_addr, enum dw_pcie_as_type as_type)
255 if (pci->iatu_unroll_enabled)
256 return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
259 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
261 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
262 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
266 type = PCIE_ATU_TYPE_MEM;
269 type = PCIE_ATU_TYPE_IO;
275 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
276 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
277 | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
280 * Make sure ATU enable takes effect before any subsequent config
283 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
284 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
285 if (val & PCIE_ATU_ENABLE)
288 mdelay(LINK_WAIT_IATU);
290 dev_err(pci->dev, "inbound iATU is not being enabled\n");
295 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
296 enum dw_pcie_region_type type)
301 case DW_PCIE_REGION_INBOUND:
302 region = PCIE_ATU_REGION_INBOUND;
304 case DW_PCIE_REGION_OUTBOUND:
305 region = PCIE_ATU_REGION_OUTBOUND;
311 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
312 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
315 int dw_pcie_wait_for_link(struct dw_pcie *pci)
319 /* check if the link is up or not */
320 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
321 if (dw_pcie_link_up(pci)) {
322 dev_info(pci->dev, "link up\n");
325 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
328 dev_err(pci->dev, "phy link never came up\n");
333 int dw_pcie_link_up(struct dw_pcie *pci)
337 if (pci->ops->link_up)
338 return pci->ops->link_up(pci);
340 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
341 return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
342 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
345 void dw_pcie_setup(struct dw_pcie *pci)
350 struct device *dev = pci->dev;
351 struct device_node *np = dev->of_node;
353 ret = of_property_read_u32(np, "num-lanes", &lanes);
357 /* set the number of lanes */
358 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
359 val &= ~PORT_LINK_MODE_MASK;
362 val |= PORT_LINK_MODE_1_LANES;
365 val |= PORT_LINK_MODE_2_LANES;
368 val |= PORT_LINK_MODE_4_LANES;
371 val |= PORT_LINK_MODE_8_LANES;
374 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
377 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
379 /* set link width speed control register */
380 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
381 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
384 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
387 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
390 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
393 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
396 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);