2 * Synopsys DesignWare PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irqdomain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci_regs.h>
18 #include <linux/platform_device.h>
20 #include "pcie-designware.h"
22 static struct pci_ops dw_pcie_ops;
24 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
29 if (pp->ops->rd_own_conf)
30 return pp->ops->rd_own_conf(pp, where, size, val);
32 pci = to_dw_pcie_from_pp(pp);
33 return dw_pcie_read(pci->dbi_base + where, size, val);
36 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
41 if (pp->ops->wr_own_conf)
42 return pp->ops->wr_own_conf(pp, where, size, val);
44 pci = to_dw_pcie_from_pp(pp);
45 return dw_pcie_write(pci->dbi_base + where, size, val);
48 static void dwc_irq_ack(struct irq_data *d)
50 struct msi_desc *msi = irq_data_get_msi_desc(d);
51 struct pcie_port *pp = msi_desc_to_pci_sysdata(msi);
52 int pos = d->hwirq % 32;
53 int i = d->hwirq / 32;
55 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, BIT(pos));
58 static struct irq_chip dw_msi_irq_chip = {
60 .irq_ack = dwc_irq_ack,
61 .irq_enable = pci_msi_unmask_irq,
62 .irq_disable = pci_msi_mask_irq,
63 .irq_mask = pci_msi_mask_irq,
64 .irq_unmask = pci_msi_unmask_irq,
68 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
72 irqreturn_t ret = IRQ_NONE;
74 for (i = 0; i < MAX_MSI_CTRLS; i++) {
75 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
82 while ((pos = find_next_bit((unsigned long *) &val, 32,
84 irq = irq_find_mapping(pp->irq_domain, i * 32 + pos);
85 generic_handle_irq(irq);
93 void dw_pcie_msi_init(struct pcie_port *pp)
97 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
98 msi_target = virt_to_phys((void *)pp->msi_data);
100 /* program the msi_data */
101 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
102 (u32)(msi_target & 0xffffffff));
103 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
104 (u32)(msi_target >> 32 & 0xffffffff));
107 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
109 unsigned int res, bit, val;
111 res = (irq / 32) * 12;
113 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
115 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
118 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
119 unsigned int nvec, unsigned int pos)
123 for (i = 0; i < nvec; i++) {
124 irq_set_msi_desc_off(irq_base, i, NULL);
125 /* Disable corresponding interrupt on MSI controller */
126 if (pp->ops->msi_clear_irq)
127 pp->ops->msi_clear_irq(pp, pos + i);
129 dw_pcie_msi_clear_irq(pp, pos + i);
132 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
135 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
137 unsigned int res, bit, val;
139 res = (irq / 32) * 12;
141 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
143 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
146 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
149 struct pcie_port *pp;
151 pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
152 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
153 order_base_2(no_irqs));
157 irq = irq_find_mapping(pp->irq_domain, pos0);
162 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
163 * descs so there is no need to allocate descs here. We can therefore
164 * assume that if irq_find_mapping above returns non-zero, then the
165 * descs are also successfully allocated.
168 for (i = 0; i < no_irqs; i++) {
169 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
170 clear_irq_range(pp, irq, i, pos0);
173 /*Enable corresponding interrupt in MSI interrupt controller */
174 if (pp->ops->msi_set_irq)
175 pp->ops->msi_set_irq(pp, pos0 + i);
177 dw_pcie_msi_set_irq(pp, pos0 + i);
181 desc->nvec_used = no_irqs;
182 desc->msi_attrib.multiple = order_base_2(no_irqs);
191 static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
196 if (pp->ops->get_msi_addr)
197 msi_target = pp->ops->get_msi_addr(pp);
199 msi_target = virt_to_phys((void *)pp->msi_data);
201 msg.address_lo = (u32)(msi_target & 0xffffffff);
202 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
204 if (pp->ops->get_msi_data)
205 msg.data = pp->ops->get_msi_data(pp, pos);
209 pci_write_msi_msg(irq, &msg);
212 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
213 struct msi_desc *desc)
216 struct pcie_port *pp = pdev->bus->sysdata;
218 if (desc->msi_attrib.is_msix)
221 irq = assign_irq(1, desc, &pos);
225 dw_msi_setup_msg(pp, irq, pos);
230 static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
233 #ifdef CONFIG_PCI_MSI
235 struct msi_desc *desc;
236 struct pcie_port *pp = pdev->bus->sysdata;
238 /* MSI-X interrupts are not supported */
239 if (type == PCI_CAP_ID_MSIX)
242 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
243 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
245 irq = assign_irq(nvec, desc, &pos);
249 dw_msi_setup_msg(pp, irq, pos);
257 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
259 struct irq_data *data = irq_get_irq_data(irq);
260 struct msi_desc *msi = irq_data_get_msi_desc(data);
261 struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
263 clear_irq_range(pp, irq, 1, data->hwirq);
266 static struct msi_controller dw_pcie_msi_chip = {
267 .setup_irq = dw_msi_setup_irq,
268 .setup_irqs = dw_msi_setup_irqs,
269 .teardown_irq = dw_msi_teardown_irq,
272 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
273 irq_hw_number_t hwirq)
275 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_edge_irq);
276 irq_set_chip_data(irq, domain->host_data);
281 static const struct irq_domain_ops msi_domain_ops = {
282 .map = dw_pcie_msi_map,
285 int dw_pcie_host_init(struct pcie_port *pp)
287 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
288 struct device *dev = pci->dev;
289 struct device_node *np = dev->of_node;
290 struct platform_device *pdev = to_platform_device(dev);
291 struct pci_bus *bus, *child;
292 struct pci_host_bridge *bridge;
293 struct resource *cfg_res;
295 struct resource_entry *win, *tmp;
297 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
299 pp->cfg0_size = resource_size(cfg_res) / 2;
300 pp->cfg1_size = resource_size(cfg_res) / 2;
301 pp->cfg0_base = cfg_res->start;
302 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
303 } else if (!pp->va_cfg0_base) {
304 dev_err(dev, "missing *config* reg space\n");
307 bridge = pci_alloc_host_bridge(0);
311 ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
312 &bridge->windows, &pp->io_base);
316 ret = devm_request_pci_bus_resources(dev, &bridge->windows);
320 /* Get the I/O and memory ranges from DT */
321 resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
322 switch (resource_type(win->res)) {
324 ret = pci_remap_iospace(win->res, pp->io_base);
326 dev_warn(dev, "error %d: failed to map resource %pR\n",
328 resource_list_destroy_entry(win);
331 pp->io->name = "I/O";
332 pp->io_size = resource_size(pp->io);
333 pp->io_bus_addr = pp->io->start - win->offset;
338 pp->mem->name = "MEM";
339 pp->mem_size = resource_size(pp->mem);
340 pp->mem_bus_addr = pp->mem->start - win->offset;
344 pp->cfg0_size = resource_size(pp->cfg) / 2;
345 pp->cfg1_size = resource_size(pp->cfg) / 2;
346 pp->cfg0_base = pp->cfg->start;
347 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
355 if (!pci->dbi_base) {
356 pci->dbi_base = devm_pci_remap_cfgspace(dev,
358 resource_size(pp->cfg));
359 if (!pci->dbi_base) {
360 dev_err(dev, "error with ioremap\n");
366 pp->mem_base = pp->mem->start;
368 if (!pp->va_cfg0_base) {
369 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
370 pp->cfg0_base, pp->cfg0_size);
371 if (!pp->va_cfg0_base) {
372 dev_err(dev, "error with ioremap in function\n");
378 if (!pp->va_cfg1_base) {
379 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
382 if (!pp->va_cfg1_base) {
383 dev_err(dev, "error with ioremap\n");
389 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
391 pci->num_viewport = 2;
393 if (IS_ENABLED(CONFIG_PCI_MSI)) {
394 if (!pp->ops->msi_host_init) {
395 pp->irq_domain = irq_domain_add_linear(dev->of_node,
396 MAX_MSI_IRQS, &msi_domain_ops,
398 if (!pp->irq_domain) {
399 dev_err(dev, "irq domain init failed\n");
404 for (i = 0; i < MAX_MSI_IRQS; i++)
405 irq_create_mapping(pp->irq_domain, i);
407 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
413 if (pp->ops->host_init) {
414 ret = pp->ops->host_init(pp);
419 pp->root_bus_nr = pp->busn->start;
421 bridge->dev.parent = dev;
422 bridge->sysdata = pp;
423 bridge->busnr = pp->root_bus_nr;
424 bridge->ops = &dw_pcie_ops;
425 bridge->map_irq = of_irq_parse_and_map_pci;
426 bridge->swizzle_irq = pci_common_swizzle;
427 if (IS_ENABLED(CONFIG_PCI_MSI)) {
428 bridge->msi = &dw_pcie_msi_chip;
429 dw_pcie_msi_chip.dev = dev;
432 ret = pci_scan_root_bus_bridge(bridge);
438 if (pp->ops->scan_bus)
439 pp->ops->scan_bus(pp);
441 pci_bus_size_bridges(bus);
442 pci_bus_assign_resources(bus);
444 list_for_each_entry(child, &bus->children, node)
445 pcie_bus_configure_settings(child);
447 pci_bus_add_devices(bus);
451 pci_free_host_bridge(bridge);
455 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
456 u32 devfn, int where, int size, u32 *val)
459 u32 busdev, cfg_size;
461 void __iomem *va_cfg_base;
462 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
464 if (pp->ops->rd_other_conf)
465 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
467 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
468 PCIE_ATU_FUNC(PCI_FUNC(devfn));
470 if (bus->parent->number == pp->root_bus_nr) {
471 type = PCIE_ATU_TYPE_CFG0;
472 cpu_addr = pp->cfg0_base;
473 cfg_size = pp->cfg0_size;
474 va_cfg_base = pp->va_cfg0_base;
476 type = PCIE_ATU_TYPE_CFG1;
477 cpu_addr = pp->cfg1_base;
478 cfg_size = pp->cfg1_size;
479 va_cfg_base = pp->va_cfg1_base;
482 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
485 ret = dw_pcie_read(va_cfg_base + where, size, val);
486 if (pci->num_viewport <= 2)
487 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
488 PCIE_ATU_TYPE_IO, pp->io_base,
489 pp->io_bus_addr, pp->io_size);
494 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
495 u32 devfn, int where, int size, u32 val)
498 u32 busdev, cfg_size;
500 void __iomem *va_cfg_base;
501 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
503 if (pp->ops->wr_other_conf)
504 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
506 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
507 PCIE_ATU_FUNC(PCI_FUNC(devfn));
509 if (bus->parent->number == pp->root_bus_nr) {
510 type = PCIE_ATU_TYPE_CFG0;
511 cpu_addr = pp->cfg0_base;
512 cfg_size = pp->cfg0_size;
513 va_cfg_base = pp->va_cfg0_base;
515 type = PCIE_ATU_TYPE_CFG1;
516 cpu_addr = pp->cfg1_base;
517 cfg_size = pp->cfg1_size;
518 va_cfg_base = pp->va_cfg1_base;
521 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
524 ret = dw_pcie_write(va_cfg_base + where, size, val);
525 if (pci->num_viewport <= 2)
526 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
527 PCIE_ATU_TYPE_IO, pp->io_base,
528 pp->io_bus_addr, pp->io_size);
533 static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
536 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
538 /* If there is no link, then there is no device */
539 if (bus->number != pp->root_bus_nr) {
540 if (!dw_pcie_link_up(pci))
544 /* access only one slot on each root port */
545 if (bus->number == pp->root_bus_nr && dev > 0)
551 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
554 struct pcie_port *pp = bus->sysdata;
556 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
558 return PCIBIOS_DEVICE_NOT_FOUND;
561 if (bus->number == pp->root_bus_nr)
562 return dw_pcie_rd_own_conf(pp, where, size, val);
564 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
567 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
568 int where, int size, u32 val)
570 struct pcie_port *pp = bus->sysdata;
572 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
573 return PCIBIOS_DEVICE_NOT_FOUND;
575 if (bus->number == pp->root_bus_nr)
576 return dw_pcie_wr_own_conf(pp, where, size, val);
578 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
581 static struct pci_ops dw_pcie_ops = {
582 .read = dw_pcie_rd_conf,
583 .write = dw_pcie_wr_conf,
586 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
590 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
591 if (val == 0xffffffff)
597 void dw_pcie_setup_rc(struct pcie_port *pp)
600 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
605 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
606 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
608 /* setup interrupt pins */
609 dw_pcie_dbi_ro_wr_en(pci);
610 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
613 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
614 dw_pcie_dbi_ro_wr_dis(pci);
616 /* setup bus numbers */
617 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
620 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
622 /* setup command register */
623 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
625 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
626 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
627 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
630 * If the platform provides ->rd_other_conf, it means the platform
631 * uses its own address translation component rather than ATU, so
632 * we should not program the ATU here.
634 if (!pp->ops->rd_other_conf) {
635 /* get iATU unroll support */
636 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
637 dev_dbg(pci->dev, "iATU unroll: %s\n",
638 pci->iatu_unroll_enabled ? "enabled" : "disabled");
640 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
641 PCIE_ATU_TYPE_MEM, pp->mem_base,
642 pp->mem_bus_addr, pp->mem_size);
643 if (pci->num_viewport > 2)
644 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
645 PCIE_ATU_TYPE_IO, pp->io_base,
646 pp->io_bus_addr, pp->io_size);
649 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
651 /* Enable write permission for the DBI read-only register */
652 dw_pcie_dbi_ro_wr_en(pci);
653 /* program correct class for RC */
654 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
655 /* Better disable write permission right after the update */
656 dw_pcie_dbi_ro_wr_dis(pci);
658 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
659 val |= PORT_LOGIC_SPEED_CHANGE;
660 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);