2 * Synopsys DesignWare PCIe Endpoint controller driver
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "pcie-designware.h"
23 #include <linux/pci-epc.h>
24 #include <linux/pci-epf.h>
26 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
28 struct pci_epc *epc = ep->epc;
33 static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
37 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
38 dw_pcie_dbi_ro_wr_en(pci);
39 dw_pcie_writel_dbi2(pci, reg, 0x0);
40 dw_pcie_writel_dbi(pci, reg, 0x0);
41 dw_pcie_dbi_ro_wr_dis(pci);
44 static int dw_pcie_ep_write_header(struct pci_epc *epc,
45 struct pci_epf_header *hdr)
47 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
48 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
50 dw_pcie_dbi_ro_wr_en(pci);
51 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
52 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
53 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
54 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
55 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
56 hdr->subclass_code | hdr->baseclass_code << 8);
57 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
58 hdr->cache_line_size);
59 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
60 hdr->subsys_vendor_id);
61 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
62 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
64 dw_pcie_dbi_ro_wr_dis(pci);
69 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
71 enum dw_pcie_as_type as_type)
75 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
77 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
78 if (free_win >= ep->num_ib_windows) {
79 dev_err(pci->dev, "no free inbound window\n");
83 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
86 dev_err(pci->dev, "Failed to program IB window\n");
90 ep->bar_to_atu[bar] = free_win;
91 set_bit(free_win, ep->ib_window_map);
96 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
97 u64 pci_addr, size_t size)
100 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
102 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
103 if (free_win >= ep->num_ob_windows) {
104 dev_err(pci->dev, "no free outbound window\n");
108 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
109 phys_addr, pci_addr, size);
111 set_bit(free_win, ep->ob_window_map);
112 ep->outbound_addr[free_win] = phys_addr;
117 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
119 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
120 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
121 u32 atu_index = ep->bar_to_atu[bar];
123 dw_pcie_ep_reset_bar(pci, bar);
125 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
126 clear_bit(atu_index, ep->ib_window_map);
129 static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
130 dma_addr_t bar_phys, size_t size, int flags)
133 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
134 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
135 enum dw_pcie_as_type as_type;
136 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
138 if (!(flags & PCI_BASE_ADDRESS_SPACE))
139 as_type = DW_PCIE_AS_MEM;
141 as_type = DW_PCIE_AS_IO;
143 ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
147 dw_pcie_dbi_ro_wr_en(pci);
148 dw_pcie_writel_dbi2(pci, reg, size - 1);
149 dw_pcie_writel_dbi(pci, reg, flags);
150 dw_pcie_dbi_ro_wr_dis(pci);
155 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
160 for (index = 0; index < ep->num_ob_windows; index++) {
161 if (ep->outbound_addr[index] != addr)
170 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
174 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
175 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
177 ret = dw_pcie_find_index(ep, addr, &atu_index);
181 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
182 clear_bit(atu_index, ep->ob_window_map);
185 static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
186 u64 pci_addr, size_t size)
189 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
190 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
192 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
194 dev_err(pci->dev, "failed to enable address\n");
201 static int dw_pcie_ep_get_msi(struct pci_epc *epc)
204 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
205 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
207 val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
208 if (!(val & MSI_CAP_MSI_EN_MASK))
211 val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
215 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
218 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
219 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
221 val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
222 val &= ~MSI_CAP_MMC_MASK;
223 val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
224 dw_pcie_dbi_ro_wr_en(pci);
225 dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
226 dw_pcie_dbi_ro_wr_dis(pci);
231 static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
232 enum pci_epc_irq_type type, u8 interrupt_num)
234 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
236 if (!ep->ops->raise_irq)
239 return ep->ops->raise_irq(ep, type, interrupt_num);
242 static void dw_pcie_ep_stop(struct pci_epc *epc)
244 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
245 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
247 if (!pci->ops->stop_link)
250 pci->ops->stop_link(pci);
253 static int dw_pcie_ep_start(struct pci_epc *epc)
255 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
256 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
258 if (!pci->ops->start_link)
261 return pci->ops->start_link(pci);
264 static const struct pci_epc_ops epc_ops = {
265 .write_header = dw_pcie_ep_write_header,
266 .set_bar = dw_pcie_ep_set_bar,
267 .clear_bar = dw_pcie_ep_clear_bar,
268 .map_addr = dw_pcie_ep_map_addr,
269 .unmap_addr = dw_pcie_ep_unmap_addr,
270 .set_msi = dw_pcie_ep_set_msi,
271 .get_msi = dw_pcie_ep_get_msi,
272 .raise_irq = dw_pcie_ep_raise_irq,
273 .start = dw_pcie_ep_start,
274 .stop = dw_pcie_ep_stop,
277 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
279 struct pci_epc *epc = ep->epc;
281 pci_epc_mem_exit(epc);
284 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
289 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
290 struct device *dev = pci->dev;
291 struct device_node *np = dev->of_node;
293 if (!pci->dbi_base || !pci->dbi_base2) {
294 dev_err(dev, "dbi_base/deb_base2 is not populated\n");
298 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
300 dev_err(dev, "unable to read *num-ib-windows* property\n");
303 if (ep->num_ib_windows > MAX_IATU_IN) {
304 dev_err(dev, "invalid *num-ib-windows*\n");
308 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
310 dev_err(dev, "unable to read *num-ob-windows* property\n");
313 if (ep->num_ob_windows > MAX_IATU_OUT) {
314 dev_err(dev, "invalid *num-ob-windows*\n");
318 ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
319 BITS_TO_LONGS(ep->num_ib_windows),
321 if (!ep->ib_window_map)
324 ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
325 BITS_TO_LONGS(ep->num_ob_windows),
327 if (!ep->ob_window_map)
330 addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
334 ep->outbound_addr = addr;
336 if (ep->ops->ep_init)
337 ep->ops->ep_init(ep);
339 epc = devm_pci_epc_create(dev, &epc_ops);
341 dev_err(dev, "failed to create epc device\n");
345 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
347 epc->max_functions = 1;
349 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
352 dev_err(dev, "Failed to initialize address space\n");
357 epc_set_drvdata(epc, ep);