1 // SPDX-License-Identifier: GPL-2.0
3 * Volume Management Device driver
4 * Copyright (c) 2015, Intel Corporation.
7 #include <linux/device.h>
8 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/msi.h>
13 #include <linux/pci.h>
14 #include <linux/srcu.h>
15 #include <linux/rculist.h>
16 #include <linux/rcupdate.h>
18 #include <asm/irqdomain.h>
19 #include <asm/device.h>
21 #include <asm/msidef.h>
27 #define PCI_REG_VMCAP 0x40
28 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1)
29 #define PCI_REG_VMCONFIG 0x44
30 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3)
31 #define PCI_REG_VMLOCK 0x70
32 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2)
34 #define MB2_SHADOW_OFFSET 0x2000
35 #define MB2_SHADOW_SIZE 16
39 * Device may contain registers which hint the physical location of the
40 * membars, in order to allow proper address translation during
41 * resource assignment to enable guest virtualization
43 VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0),
46 * Device may provide root port configuration information which limits
49 VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1),
53 * Lock for manipulating VMD IRQ lists.
55 static DEFINE_RAW_SPINLOCK(list_lock);
58 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
59 * @node: list item for parent traversal.
60 * @irq: back pointer to parent.
61 * @enabled: true if driver enabled IRQ
62 * @virq: the virtual IRQ value provided to the requesting driver.
64 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
65 * a VMD IRQ using this structure.
68 struct list_head node;
69 struct vmd_irq_list *irq;
75 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
76 * @irq_list: the list of irq's the VMD one demuxes to.
77 * @srcu: SRCU struct for local synchronization.
78 * @count: number of child IRQs assigned to this vector; used to track
82 struct list_head irq_list;
83 struct srcu_struct srcu;
94 struct vmd_irq_list *irqs;
96 struct pci_sysdata sysdata;
97 struct resource resources[3];
98 struct irq_domain *irq_domain;
102 #ifdef CONFIG_X86_DEV_DMA_OPS
103 struct dma_map_ops dma_ops;
104 struct dma_domain dma_domain;
108 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
110 return container_of(bus->sysdata, struct vmd_dev, sysdata);
113 static inline unsigned int index_from_irqs(struct vmd_dev *vmd,
114 struct vmd_irq_list *irqs)
116 return irqs - vmd->irqs;
120 * Drivers managing a device in a VMD domain allocate their own IRQs as before,
121 * but the MSI entry for the hardware it's driving will be programmed with a
122 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
123 * domain into one of its own, and the VMD driver de-muxes these for the
124 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
125 * and irq_chip to set this up.
127 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
129 struct vmd_irq *vmdirq = data->chip_data;
130 struct vmd_irq_list *irq = vmdirq->irq;
131 struct vmd_dev *vmd = irq_data_get_irq_handler_data(data);
133 msg->address_hi = MSI_ADDR_BASE_HI;
134 msg->address_lo = MSI_ADDR_BASE_LO |
135 MSI_ADDR_DEST_ID(index_from_irqs(vmd, irq));
140 * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops.
142 static void vmd_irq_enable(struct irq_data *data)
144 struct vmd_irq *vmdirq = data->chip_data;
147 raw_spin_lock_irqsave(&list_lock, flags);
148 WARN_ON(vmdirq->enabled);
149 list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
150 vmdirq->enabled = true;
151 raw_spin_unlock_irqrestore(&list_lock, flags);
153 data->chip->irq_unmask(data);
156 static void vmd_irq_disable(struct irq_data *data)
158 struct vmd_irq *vmdirq = data->chip_data;
161 data->chip->irq_mask(data);
163 raw_spin_lock_irqsave(&list_lock, flags);
164 if (vmdirq->enabled) {
165 list_del_rcu(&vmdirq->node);
166 vmdirq->enabled = false;
168 raw_spin_unlock_irqrestore(&list_lock, flags);
172 * XXX: Stubbed until we develop acceptable way to not create conflicts with
173 * other devices sharing the same vector.
175 static int vmd_irq_set_affinity(struct irq_data *data,
176 const struct cpumask *dest, bool force)
181 static struct irq_chip vmd_msi_controller = {
183 .irq_enable = vmd_irq_enable,
184 .irq_disable = vmd_irq_disable,
185 .irq_compose_msi_msg = vmd_compose_msi_msg,
186 .irq_set_affinity = vmd_irq_set_affinity,
189 static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
190 msi_alloc_info_t *arg)
196 * XXX: We can be even smarter selecting the best IRQ once we solve the
199 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
204 if (vmd->msix_count == 1)
205 return &vmd->irqs[0];
208 * White list for fast-interrupt handlers. All others will share the
209 * "slow" interrupt vector.
211 switch (msi_desc_to_pci_dev(desc)->class) {
212 case PCI_CLASS_STORAGE_EXPRESS:
215 return &vmd->irqs[0];
218 raw_spin_lock_irqsave(&list_lock, flags);
219 for (i = 1; i < vmd->msix_count; i++)
220 if (vmd->irqs[i].count < vmd->irqs[best].count)
222 vmd->irqs[best].count++;
223 raw_spin_unlock_irqrestore(&list_lock, flags);
225 return &vmd->irqs[best];
228 static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
229 unsigned int virq, irq_hw_number_t hwirq,
230 msi_alloc_info_t *arg)
232 struct msi_desc *desc = arg->desc;
233 struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus);
234 struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
235 unsigned int index, vector;
240 INIT_LIST_HEAD(&vmdirq->node);
241 vmdirq->irq = vmd_next_irq(vmd, desc);
243 index = index_from_irqs(vmd, vmdirq->irq);
244 vector = pci_irq_vector(vmd->dev, index);
246 irq_domain_set_info(domain, virq, vector, info->chip, vmdirq,
247 handle_untracked_irq, vmd, NULL);
251 static void vmd_msi_free(struct irq_domain *domain,
252 struct msi_domain_info *info, unsigned int virq)
254 struct vmd_irq *vmdirq = irq_get_chip_data(virq);
257 synchronize_srcu(&vmdirq->irq->srcu);
259 /* XXX: Potential optimization to rebalance */
260 raw_spin_lock_irqsave(&list_lock, flags);
261 vmdirq->irq->count--;
262 raw_spin_unlock_irqrestore(&list_lock, flags);
267 static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev,
268 int nvec, msi_alloc_info_t *arg)
270 struct pci_dev *pdev = to_pci_dev(dev);
271 struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
273 if (nvec > vmd->msix_count)
274 return vmd->msix_count;
276 memset(arg, 0, sizeof(*arg));
280 static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
285 static struct msi_domain_ops vmd_msi_domain_ops = {
286 .get_hwirq = vmd_get_hwirq,
287 .msi_init = vmd_msi_init,
288 .msi_free = vmd_msi_free,
289 .msi_prepare = vmd_msi_prepare,
290 .set_desc = vmd_set_desc,
293 static struct msi_domain_info vmd_msi_domain_info = {
294 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
296 .ops = &vmd_msi_domain_ops,
297 .chip = &vmd_msi_controller,
300 #ifdef CONFIG_X86_DEV_DMA_OPS
302 * VMD replaces the requester ID with its own. DMA mappings for devices in a
303 * VMD domain need to be mapped for the VMD, not the device requiring
306 static struct device *to_vmd_dev(struct device *dev)
308 struct pci_dev *pdev = to_pci_dev(dev);
309 struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
311 return &vmd->dev->dev;
314 static const struct dma_map_ops *vmd_dma_ops(struct device *dev)
316 return get_dma_ops(to_vmd_dev(dev));
319 static void *vmd_alloc(struct device *dev, size_t size, dma_addr_t *addr,
320 gfp_t flag, unsigned long attrs)
322 return vmd_dma_ops(dev)->alloc(to_vmd_dev(dev), size, addr, flag,
326 static void vmd_free(struct device *dev, size_t size, void *vaddr,
327 dma_addr_t addr, unsigned long attrs)
329 return vmd_dma_ops(dev)->free(to_vmd_dev(dev), size, vaddr, addr,
333 static int vmd_mmap(struct device *dev, struct vm_area_struct *vma,
334 void *cpu_addr, dma_addr_t addr, size_t size,
337 return vmd_dma_ops(dev)->mmap(to_vmd_dev(dev), vma, cpu_addr, addr,
341 static int vmd_get_sgtable(struct device *dev, struct sg_table *sgt,
342 void *cpu_addr, dma_addr_t addr, size_t size,
345 return vmd_dma_ops(dev)->get_sgtable(to_vmd_dev(dev), sgt, cpu_addr,
349 static dma_addr_t vmd_map_page(struct device *dev, struct page *page,
350 unsigned long offset, size_t size,
351 enum dma_data_direction dir,
354 return vmd_dma_ops(dev)->map_page(to_vmd_dev(dev), page, offset, size,
358 static void vmd_unmap_page(struct device *dev, dma_addr_t addr, size_t size,
359 enum dma_data_direction dir, unsigned long attrs)
361 vmd_dma_ops(dev)->unmap_page(to_vmd_dev(dev), addr, size, dir, attrs);
364 static int vmd_map_sg(struct device *dev, struct scatterlist *sg, int nents,
365 enum dma_data_direction dir, unsigned long attrs)
367 return vmd_dma_ops(dev)->map_sg(to_vmd_dev(dev), sg, nents, dir, attrs);
370 static void vmd_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
371 enum dma_data_direction dir, unsigned long attrs)
373 vmd_dma_ops(dev)->unmap_sg(to_vmd_dev(dev), sg, nents, dir, attrs);
376 static void vmd_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
377 size_t size, enum dma_data_direction dir)
379 vmd_dma_ops(dev)->sync_single_for_cpu(to_vmd_dev(dev), addr, size, dir);
382 static void vmd_sync_single_for_device(struct device *dev, dma_addr_t addr,
383 size_t size, enum dma_data_direction dir)
385 vmd_dma_ops(dev)->sync_single_for_device(to_vmd_dev(dev), addr, size,
389 static void vmd_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
390 int nents, enum dma_data_direction dir)
392 vmd_dma_ops(dev)->sync_sg_for_cpu(to_vmd_dev(dev), sg, nents, dir);
395 static void vmd_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
396 int nents, enum dma_data_direction dir)
398 vmd_dma_ops(dev)->sync_sg_for_device(to_vmd_dev(dev), sg, nents, dir);
401 static int vmd_mapping_error(struct device *dev, dma_addr_t addr)
403 return vmd_dma_ops(dev)->mapping_error(to_vmd_dev(dev), addr);
406 static int vmd_dma_supported(struct device *dev, u64 mask)
408 return vmd_dma_ops(dev)->dma_supported(to_vmd_dev(dev), mask);
411 #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
412 static u64 vmd_get_required_mask(struct device *dev)
414 return vmd_dma_ops(dev)->get_required_mask(to_vmd_dev(dev));
418 static void vmd_teardown_dma_ops(struct vmd_dev *vmd)
420 struct dma_domain *domain = &vmd->dma_domain;
422 if (get_dma_ops(&vmd->dev->dev))
423 del_dma_domain(domain);
426 #define ASSIGN_VMD_DMA_OPS(source, dest, fn) \
429 dest->fn = vmd_##fn; \
432 static void vmd_setup_dma_ops(struct vmd_dev *vmd)
434 const struct dma_map_ops *source = get_dma_ops(&vmd->dev->dev);
435 struct dma_map_ops *dest = &vmd->dma_ops;
436 struct dma_domain *domain = &vmd->dma_domain;
438 domain->domain_nr = vmd->sysdata.domain;
439 domain->dma_ops = dest;
443 ASSIGN_VMD_DMA_OPS(source, dest, alloc);
444 ASSIGN_VMD_DMA_OPS(source, dest, free);
445 ASSIGN_VMD_DMA_OPS(source, dest, mmap);
446 ASSIGN_VMD_DMA_OPS(source, dest, get_sgtable);
447 ASSIGN_VMD_DMA_OPS(source, dest, map_page);
448 ASSIGN_VMD_DMA_OPS(source, dest, unmap_page);
449 ASSIGN_VMD_DMA_OPS(source, dest, map_sg);
450 ASSIGN_VMD_DMA_OPS(source, dest, unmap_sg);
451 ASSIGN_VMD_DMA_OPS(source, dest, sync_single_for_cpu);
452 ASSIGN_VMD_DMA_OPS(source, dest, sync_single_for_device);
453 ASSIGN_VMD_DMA_OPS(source, dest, sync_sg_for_cpu);
454 ASSIGN_VMD_DMA_OPS(source, dest, sync_sg_for_device);
455 ASSIGN_VMD_DMA_OPS(source, dest, mapping_error);
456 ASSIGN_VMD_DMA_OPS(source, dest, dma_supported);
457 #ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
458 ASSIGN_VMD_DMA_OPS(source, dest, get_required_mask);
460 add_dma_domain(domain);
462 #undef ASSIGN_VMD_DMA_OPS
464 static void vmd_teardown_dma_ops(struct vmd_dev *vmd) {}
465 static void vmd_setup_dma_ops(struct vmd_dev *vmd) {}
468 static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
469 unsigned int devfn, int reg, int len)
471 char __iomem *addr = vmd->cfgbar +
472 ((bus->number - vmd->busn_start) << 20) +
475 if ((addr - vmd->cfgbar) + len >=
476 resource_size(&vmd->dev->resource[VMD_CFGBAR]))
483 * CPU may deadlock if config space is not serialized on some versions of this
484 * hardware, so all config space access is done under a spinlock.
486 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
489 struct vmd_dev *vmd = vmd_from_bus(bus);
490 char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
497 spin_lock_irqsave(&vmd->cfg_lock, flags);
500 *value = readb(addr);
503 *value = readw(addr);
506 *value = readl(addr);
512 spin_unlock_irqrestore(&vmd->cfg_lock, flags);
517 * VMD h/w converts non-posted config writes to posted memory writes. The
518 * read-back in this function forces the completion so it returns only after
519 * the config space was written, as expected.
521 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
524 struct vmd_dev *vmd = vmd_from_bus(bus);
525 char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
532 spin_lock_irqsave(&vmd->cfg_lock, flags);
550 spin_unlock_irqrestore(&vmd->cfg_lock, flags);
554 static struct pci_ops vmd_ops = {
555 .read = vmd_pci_read,
556 .write = vmd_pci_write,
559 static void vmd_attach_resources(struct vmd_dev *vmd)
561 vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1];
562 vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2];
565 static void vmd_detach_resources(struct vmd_dev *vmd)
567 vmd->dev->resource[VMD_MEMBAR1].child = NULL;
568 vmd->dev->resource[VMD_MEMBAR2].child = NULL;
572 * VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
573 * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
574 * 16 bits are the PCI Segment Group (domain) number. Other bits are
575 * currently reserved.
577 static int vmd_find_free_domain(void)
580 struct pci_bus *bus = NULL;
582 while ((bus = pci_find_next_bus(bus)) != NULL)
583 domain = max_t(int, domain, pci_domain_nr(bus));
587 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
589 struct pci_sysdata *sd = &vmd->sysdata;
590 struct fwnode_handle *fn;
591 struct resource *res;
594 LIST_HEAD(resources);
595 resource_size_t offset[2] = {0};
596 resource_size_t membar2_offset = 0x2000;
599 * Shadow registers may exist in certain VMD device ids which allow
600 * guests to correctly assign host physical addresses to the root ports
601 * and child devices. These registers will either return the host value
602 * or 0, depending on an enable bit in the VMD device.
604 if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) {
608 membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE;
609 ret = pci_read_config_dword(vmd->dev, PCI_REG_VMLOCK, &vmlock);
610 if (ret || vmlock == ~0)
613 if (MB2_SHADOW_EN(vmlock)) {
614 void __iomem *membar2;
616 membar2 = pci_iomap(vmd->dev, VMD_MEMBAR2, 0);
619 offset[0] = vmd->dev->resource[VMD_MEMBAR1].start -
620 (readq(membar2 + MB2_SHADOW_OFFSET) &
621 PCI_BASE_ADDRESS_MEM_MASK);
622 offset[1] = vmd->dev->resource[VMD_MEMBAR2].start -
623 (readq(membar2 + MB2_SHADOW_OFFSET + 8) &
624 PCI_BASE_ADDRESS_MEM_MASK);
625 pci_iounmap(vmd->dev, membar2);
630 * Certain VMD devices may have a root port configuration option which
631 * limits the bus range to between 0-127 or 128-255
633 if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) {
636 pci_read_config_dword(vmd->dev, PCI_REG_VMCAP, &vmcap);
637 pci_read_config_dword(vmd->dev, PCI_REG_VMCONFIG, &vmconfig);
638 if (BUS_RESTRICT_CAP(vmcap) &&
639 (BUS_RESTRICT_CFG(vmconfig) == 0x1))
640 vmd->busn_start = 128;
643 res = &vmd->dev->resource[VMD_CFGBAR];
644 vmd->resources[0] = (struct resource) {
645 .name = "VMD CFGBAR",
646 .start = vmd->busn_start,
647 .end = vmd->busn_start + (resource_size(res) >> 20) - 1,
648 .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
652 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
653 * put 32-bit resources in the window.
655 * There's no hardware reason why a 64-bit window *couldn't*
656 * contain a 32-bit resource, but pbus_size_mem() computes the
657 * bridge window size assuming a 64-bit window will contain no
658 * 32-bit resources. __pci_assign_resource() enforces that
659 * artificial restriction to make sure everything will fit.
661 * The only way we could use a 64-bit non-prefechable MEMBAR is
662 * if its address is <4GB so that we can convert it to a 32-bit
663 * resource. To be visible to the host OS, all VMD endpoints must
664 * be initially configured by platform BIOS, which includes setting
665 * up these resources. We can assume the device is configured
666 * according to the platform needs.
668 res = &vmd->dev->resource[VMD_MEMBAR1];
669 upper_bits = upper_32_bits(res->end);
670 flags = res->flags & ~IORESOURCE_SIZEALIGN;
672 flags &= ~IORESOURCE_MEM_64;
673 vmd->resources[1] = (struct resource) {
674 .name = "VMD MEMBAR1",
681 res = &vmd->dev->resource[VMD_MEMBAR2];
682 upper_bits = upper_32_bits(res->end);
683 flags = res->flags & ~IORESOURCE_SIZEALIGN;
685 flags &= ~IORESOURCE_MEM_64;
686 vmd->resources[2] = (struct resource) {
687 .name = "VMD MEMBAR2",
688 .start = res->start + membar2_offset,
694 sd->vmd_domain = true;
695 sd->domain = vmd_find_free_domain();
699 sd->node = pcibus_to_node(vmd->dev->bus);
701 fn = irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd->sysdata.domain);
705 vmd->irq_domain = pci_msi_create_irq_domain(fn, &vmd_msi_domain_info,
707 if (!vmd->irq_domain) {
708 irq_domain_free_fwnode(fn);
712 pci_add_resource(&resources, &vmd->resources[0]);
713 pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
714 pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
716 vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
717 &vmd_ops, sd, &resources);
719 pci_free_resource_list(&resources);
720 irq_domain_remove(vmd->irq_domain);
721 irq_domain_free_fwnode(fn);
725 vmd_attach_resources(vmd);
726 vmd_setup_dma_ops(vmd);
727 dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
728 pci_rescan_bus(vmd->bus);
730 WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
731 "domain"), "Can't create symlink to domain\n");
735 static irqreturn_t vmd_irq(int irq, void *data)
737 struct vmd_irq_list *irqs = data;
738 struct vmd_irq *vmdirq;
741 idx = srcu_read_lock(&irqs->srcu);
742 list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
743 generic_handle_irq(vmdirq->virq);
744 srcu_read_unlock(&irqs->srcu, idx);
749 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
754 if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
757 vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
762 err = pcim_enable_device(dev);
766 vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
771 if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
772 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)))
775 vmd->msix_count = pci_msix_vec_count(dev);
776 if (vmd->msix_count < 0)
779 vmd->msix_count = pci_alloc_irq_vectors(dev, 1, vmd->msix_count,
781 if (vmd->msix_count < 0)
782 return vmd->msix_count;
784 vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
789 for (i = 0; i < vmd->msix_count; i++) {
790 err = init_srcu_struct(&vmd->irqs[i].srcu);
794 INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
795 err = devm_request_irq(&dev->dev, pci_irq_vector(dev, i),
796 vmd_irq, IRQF_NO_THREAD,
797 "vmd", &vmd->irqs[i]);
802 spin_lock_init(&vmd->cfg_lock);
803 pci_set_drvdata(dev, vmd);
804 err = vmd_enable_domain(vmd, (unsigned long) id->driver_data);
808 dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
809 vmd->sysdata.domain);
813 static void vmd_cleanup_srcu(struct vmd_dev *vmd)
817 for (i = 0; i < vmd->msix_count; i++)
818 cleanup_srcu_struct(&vmd->irqs[i].srcu);
821 static void vmd_remove(struct pci_dev *dev)
823 struct vmd_dev *vmd = pci_get_drvdata(dev);
824 struct fwnode_handle *fn = vmd->irq_domain->fwnode;
826 sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
827 pci_stop_root_bus(vmd->bus);
828 pci_remove_root_bus(vmd->bus);
829 vmd_cleanup_srcu(vmd);
830 vmd_teardown_dma_ops(vmd);
831 vmd_detach_resources(vmd);
832 irq_domain_remove(vmd->irq_domain);
833 irq_domain_free_fwnode(fn);
836 #ifdef CONFIG_PM_SLEEP
837 static int vmd_suspend(struct device *dev)
839 struct pci_dev *pdev = to_pci_dev(dev);
840 struct vmd_dev *vmd = pci_get_drvdata(pdev);
843 for (i = 0; i < vmd->msix_count; i++)
844 devm_free_irq(dev, pci_irq_vector(pdev, i), &vmd->irqs[i]);
846 pci_save_state(pdev);
850 static int vmd_resume(struct device *dev)
852 struct pci_dev *pdev = to_pci_dev(dev);
853 struct vmd_dev *vmd = pci_get_drvdata(pdev);
856 for (i = 0; i < vmd->msix_count; i++) {
857 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
858 vmd_irq, IRQF_NO_THREAD,
859 "vmd", &vmd->irqs[i]);
864 pci_restore_state(pdev);
868 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
870 static const struct pci_device_id vmd_ids[] = {
871 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),},
872 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
873 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
874 VMD_FEAT_HAS_BUS_RESTRICTIONS,},
875 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
876 .driver_data = VMD_FEAT_HAS_BUS_RESTRICTIONS,},
879 MODULE_DEVICE_TABLE(pci, vmd_ids);
881 static struct pci_driver vmd_drv = {
885 .remove = vmd_remove,
887 .pm = &vmd_dev_pm_ops,
890 module_pci_driver(vmd_drv);
892 MODULE_AUTHOR("Intel Corporation");
893 MODULE_LICENSE("GPL v2");
894 MODULE_VERSION("0.6");