1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
10 * Bits taken from Synopsys DesignWare Host controller driver and
11 * ARM PCI Host generic driver.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/iopoll.h>
19 #include <linux/of_pci.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/reset.h>
25 #include "pcie-rockchip.h"
27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
29 struct device *dev = rockchip->dev;
30 struct platform_device *pdev = to_platform_device(dev);
31 struct device_node *node = dev->of_node;
32 struct resource *regs;
35 if (rockchip->is_rc) {
36 regs = platform_get_resource_byname(pdev,
39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
40 if (IS_ERR(rockchip->reg_base))
41 return PTR_ERR(rockchip->reg_base);
44 platform_get_resource_byname(pdev, IORESOURCE_MEM,
46 if (!rockchip->mem_res)
51 devm_platform_ioremap_resource_byname(pdev, "apb-base");
52 if (IS_ERR(rockchip->apb_base))
53 return PTR_ERR(rockchip->apb_base);
55 err = rockchip_pcie_get_phys(rockchip);
60 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
61 if (!err && (rockchip->lanes == 0 ||
62 rockchip->lanes == 3 ||
63 rockchip->lanes > 4)) {
64 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
68 rockchip->link_gen = of_pci_get_max_link_speed(node);
69 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
70 rockchip->link_gen = 2;
72 rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
73 if (IS_ERR(rockchip->core_rst)) {
74 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
75 dev_err(dev, "missing core reset property in node\n");
76 return PTR_ERR(rockchip->core_rst);
79 rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
80 if (IS_ERR(rockchip->mgmt_rst)) {
81 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
82 dev_err(dev, "missing mgmt reset property in node\n");
83 return PTR_ERR(rockchip->mgmt_rst);
86 rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
88 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
89 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
90 dev_err(dev, "missing mgmt-sticky reset property in node\n");
91 return PTR_ERR(rockchip->mgmt_sticky_rst);
94 rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
95 if (IS_ERR(rockchip->pipe_rst)) {
96 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
97 dev_err(dev, "missing pipe reset property in node\n");
98 return PTR_ERR(rockchip->pipe_rst);
101 rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
102 if (IS_ERR(rockchip->pm_rst)) {
103 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
104 dev_err(dev, "missing pm reset property in node\n");
105 return PTR_ERR(rockchip->pm_rst);
108 rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
109 if (IS_ERR(rockchip->pclk_rst)) {
110 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
111 dev_err(dev, "missing pclk reset property in node\n");
112 return PTR_ERR(rockchip->pclk_rst);
115 rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
116 if (IS_ERR(rockchip->aclk_rst)) {
117 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
118 dev_err(dev, "missing aclk reset property in node\n");
119 return PTR_ERR(rockchip->aclk_rst);
122 if (rockchip->is_rc) {
123 rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
125 if (IS_ERR(rockchip->ep_gpio))
126 return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
127 "failed to get ep GPIO\n");
130 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
131 if (IS_ERR(rockchip->aclk_pcie)) {
132 dev_err(dev, "aclk clock not found\n");
133 return PTR_ERR(rockchip->aclk_pcie);
136 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
137 if (IS_ERR(rockchip->aclk_perf_pcie)) {
138 dev_err(dev, "aclk_perf clock not found\n");
139 return PTR_ERR(rockchip->aclk_perf_pcie);
142 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
143 if (IS_ERR(rockchip->hclk_pcie)) {
144 dev_err(dev, "hclk clock not found\n");
145 return PTR_ERR(rockchip->hclk_pcie);
148 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
149 if (IS_ERR(rockchip->clk_pcie_pm)) {
150 dev_err(dev, "pm clock not found\n");
151 return PTR_ERR(rockchip->clk_pcie_pm);
156 EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
158 #define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
159 /* 100 ms max wait time for PHY PLLs to lock */
160 #define RK_PHY_PLL_LOCK_TIMEOUT_US 100000
161 /* Sleep should be less than 20ms */
162 #define RK_PHY_PLL_LOCK_SLEEP_US 1000
164 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
166 struct device *dev = rockchip->dev;
170 err = reset_control_assert(rockchip->aclk_rst);
172 dev_err(dev, "assert aclk_rst err %d\n", err);
176 err = reset_control_assert(rockchip->pclk_rst);
178 dev_err(dev, "assert pclk_rst err %d\n", err);
182 err = reset_control_assert(rockchip->pm_rst);
184 dev_err(dev, "assert pm_rst err %d\n", err);
188 for (i = 0; i < MAX_LANE_NUM; i++) {
189 err = phy_init(rockchip->phys[i]);
191 dev_err(dev, "init phy%d err %d\n", i, err);
196 err = reset_control_assert(rockchip->core_rst);
198 dev_err(dev, "assert core_rst err %d\n", err);
202 err = reset_control_assert(rockchip->mgmt_rst);
204 dev_err(dev, "assert mgmt_rst err %d\n", err);
208 err = reset_control_assert(rockchip->mgmt_sticky_rst);
210 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
214 err = reset_control_assert(rockchip->pipe_rst);
216 dev_err(dev, "assert pipe_rst err %d\n", err);
222 err = reset_control_deassert(rockchip->pm_rst);
224 dev_err(dev, "deassert pm_rst err %d\n", err);
228 err = reset_control_deassert(rockchip->aclk_rst);
230 dev_err(dev, "deassert aclk_rst err %d\n", err);
234 err = reset_control_deassert(rockchip->pclk_rst);
236 dev_err(dev, "deassert pclk_rst err %d\n", err);
240 if (rockchip->link_gen == 2)
241 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
244 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
247 regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE |
248 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
251 regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
253 regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;
255 rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
257 for (i = 0; i < MAX_LANE_NUM; i++) {
258 err = phy_power_on(rockchip->phys[i]);
260 dev_err(dev, "power on phy%d err %d\n", i, err);
261 goto err_power_off_phy;
265 err = readx_poll_timeout(rockchip_pcie_read_addr,
266 PCIE_CLIENT_SIDE_BAND_STATUS,
267 regs, !(regs & PCIE_CLIENT_PHY_ST),
268 RK_PHY_PLL_LOCK_SLEEP_US,
269 RK_PHY_PLL_LOCK_TIMEOUT_US);
271 dev_err(dev, "PHY PLLs could not lock, %d\n", err);
272 goto err_power_off_phy;
276 * Please don't reorder the deassert sequence of the following
279 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
281 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
282 goto err_power_off_phy;
285 err = reset_control_deassert(rockchip->core_rst);
287 dev_err(dev, "deassert core_rst err %d\n", err);
288 goto err_power_off_phy;
291 err = reset_control_deassert(rockchip->mgmt_rst);
293 dev_err(dev, "deassert mgmt_rst err %d\n", err);
294 goto err_power_off_phy;
297 err = reset_control_deassert(rockchip->pipe_rst);
299 dev_err(dev, "deassert pipe_rst err %d\n", err);
300 goto err_power_off_phy;
306 phy_power_off(rockchip->phys[i]);
310 phy_exit(rockchip->phys[i]);
313 EXPORT_SYMBOL_GPL(rockchip_pcie_init_port);
315 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
317 struct device *dev = rockchip->dev;
322 phy = devm_phy_get(dev, "pcie-phy");
324 rockchip->legacy_phy = true;
325 rockchip->phys[0] = phy;
326 dev_warn(dev, "legacy phy model is deprecated!\n");
330 if (PTR_ERR(phy) == -EPROBE_DEFER)
333 dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");
335 for (i = 0; i < MAX_LANE_NUM; i++) {
336 name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);
340 phy = devm_of_phy_get(dev, dev->of_node, name);
344 if (PTR_ERR(phy) != -EPROBE_DEFER)
345 dev_err(dev, "missing phy for lane %d: %ld\n",
350 rockchip->phys[i] = phy;
355 EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys);
357 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
361 for (i = 0; i < MAX_LANE_NUM; i++) {
362 /* inactive lanes are already powered off */
363 if (rockchip->lanes_map & BIT(i))
364 phy_power_off(rockchip->phys[i]);
365 phy_exit(rockchip->phys[i]);
368 EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys);
370 int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
372 struct device *dev = rockchip->dev;
375 err = clk_prepare_enable(rockchip->aclk_pcie);
377 dev_err(dev, "unable to enable aclk_pcie clock\n");
381 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
383 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
384 goto err_aclk_perf_pcie;
387 err = clk_prepare_enable(rockchip->hclk_pcie);
389 dev_err(dev, "unable to enable hclk_pcie clock\n");
393 err = clk_prepare_enable(rockchip->clk_pcie_pm);
395 dev_err(dev, "unable to enable clk_pcie_pm clock\n");
396 goto err_clk_pcie_pm;
402 clk_disable_unprepare(rockchip->hclk_pcie);
404 clk_disable_unprepare(rockchip->aclk_perf_pcie);
406 clk_disable_unprepare(rockchip->aclk_pcie);
409 EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
411 void rockchip_pcie_disable_clocks(void *data)
413 struct rockchip_pcie *rockchip = data;
415 clk_disable_unprepare(rockchip->clk_pcie_pm);
416 clk_disable_unprepare(rockchip->hclk_pcie);
417 clk_disable_unprepare(rockchip->aclk_perf_pcie);
418 clk_disable_unprepare(rockchip->aclk_pcie);
420 EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
422 void rockchip_pcie_cfg_configuration_accesses(
423 struct rockchip_pcie *rockchip, u32 type)
427 /* Configuration Accesses for region 0 */
428 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
430 rockchip_pcie_write(rockchip,
431 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
432 PCIE_CORE_OB_REGION_ADDR0);
433 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
434 PCIE_CORE_OB_REGION_ADDR1);
435 ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
436 ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
437 ob_desc_0 |= (type | (0x1 << 23));
438 rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
439 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
441 EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);