1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
10 * Bits taken from Synopsys DesignWare Host controller driver and
11 * ARM PCI Host generic driver.
14 #include <linux/bitrev.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/iopoll.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/kernel.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/of_pci.h>
30 #include <linux/of_platform.h>
31 #include <linux/of_irq.h>
32 #include <linux/pci.h>
33 #include <linux/pci_ids.h>
34 #include <linux/phy/phy.h>
35 #include <linux/platform_device.h>
36 #include <linux/reset.h>
37 #include <linux/regmap.h>
40 #include "pcie-rockchip.h"
42 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
46 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
47 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
48 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
51 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
55 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
56 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
57 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
60 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
64 /* Update Tx credit maximum update interval */
65 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
66 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
67 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
68 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
71 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
72 struct pci_bus *bus, int dev)
75 * Access only one slot on each root port.
76 * Do not read more than one device on the bus directly attached
77 * to RC's downstream side.
79 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent))
85 static u8 rockchip_pcie_lane_map(struct rockchip_pcie *rockchip)
90 if (rockchip->legacy_phy)
91 return GENMASK(MAX_LANE_NUM - 1, 0);
93 val = rockchip_pcie_read(rockchip, PCIE_CORE_LANE_MAP);
94 map = val & PCIE_CORE_LANE_MAP_MASK;
96 /* The link may be using a reverse-indexed mapping. */
97 if (val & PCIE_CORE_LANE_MAP_REVERSE)
98 map = bitrev8(map) >> 4;
103 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
104 int where, int size, u32 *val)
108 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
110 if (!IS_ALIGNED((uintptr_t)addr, size)) {
112 return PCIBIOS_BAD_REGISTER_NUMBER;
117 } else if (size == 2) {
119 } else if (size == 1) {
123 return PCIBIOS_BAD_REGISTER_NUMBER;
125 return PCIBIOS_SUCCESSFUL;
128 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
129 int where, int size, u32 val)
131 u32 mask, tmp, offset;
134 offset = where & ~0x3;
135 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
139 return PCIBIOS_SUCCESSFUL;
142 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
145 * N.B. This read/modify/write isn't safe in general because it can
146 * corrupt RW1C bits in adjacent registers. But the hardware
147 * doesn't support smaller writes.
149 tmp = readl(addr) & mask;
150 tmp |= val << ((where & 0x3) * 8);
153 return PCIBIOS_SUCCESSFUL;
156 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
157 struct pci_bus *bus, u32 devfn,
158 int where, int size, u32 *val)
162 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
163 PCI_FUNC(devfn), where);
165 if (!IS_ALIGNED(busdev, size)) {
167 return PCIBIOS_BAD_REGISTER_NUMBER;
170 if (pci_is_root_bus(bus->parent))
171 rockchip_pcie_cfg_configuration_accesses(rockchip,
172 AXI_WRAPPER_TYPE0_CFG);
174 rockchip_pcie_cfg_configuration_accesses(rockchip,
175 AXI_WRAPPER_TYPE1_CFG);
178 *val = readl(rockchip->reg_base + busdev);
179 } else if (size == 2) {
180 *val = readw(rockchip->reg_base + busdev);
181 } else if (size == 1) {
182 *val = readb(rockchip->reg_base + busdev);
185 return PCIBIOS_BAD_REGISTER_NUMBER;
187 return PCIBIOS_SUCCESSFUL;
190 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
191 struct pci_bus *bus, u32 devfn,
192 int where, int size, u32 val)
196 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
197 PCI_FUNC(devfn), where);
198 if (!IS_ALIGNED(busdev, size))
199 return PCIBIOS_BAD_REGISTER_NUMBER;
201 if (pci_is_root_bus(bus->parent))
202 rockchip_pcie_cfg_configuration_accesses(rockchip,
203 AXI_WRAPPER_TYPE0_CFG);
205 rockchip_pcie_cfg_configuration_accesses(rockchip,
206 AXI_WRAPPER_TYPE1_CFG);
209 writel(val, rockchip->reg_base + busdev);
211 writew(val, rockchip->reg_base + busdev);
213 writeb(val, rockchip->reg_base + busdev);
215 return PCIBIOS_BAD_REGISTER_NUMBER;
217 return PCIBIOS_SUCCESSFUL;
220 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
223 struct rockchip_pcie *rockchip = bus->sysdata;
225 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
227 return PCIBIOS_DEVICE_NOT_FOUND;
230 if (pci_is_root_bus(bus))
231 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
233 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size,
237 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
238 int where, int size, u32 val)
240 struct rockchip_pcie *rockchip = bus->sysdata;
242 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
243 return PCIBIOS_DEVICE_NOT_FOUND;
245 if (pci_is_root_bus(bus))
246 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
248 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size,
252 static struct pci_ops rockchip_pcie_ops = {
253 .read = rockchip_pcie_rd_conf,
254 .write = rockchip_pcie_wr_conf,
257 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
260 u32 status, scale, power;
262 if (IS_ERR(rockchip->vpcie3v3))
266 * Set RC's captured slot power limit and scale if
267 * vpcie3v3 available. The default values are both zero
268 * which means the software should set these two according
269 * to the actual power supply.
271 curr = regulator_get_current_limit(rockchip->vpcie3v3);
275 scale = 3; /* 0.001x */
276 curr = curr / 1000; /* convert to mA */
277 power = (curr * 3300) / 1000; /* milliwatt */
278 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
280 dev_warn(rockchip->dev, "invalid power supply\n");
287 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
288 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
289 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
290 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
294 * rockchip_pcie_host_init_port - Initialize hardware
295 * @rockchip: PCIe port information
297 static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
299 struct device *dev = rockchip->dev;
300 int err, i = MAX_LANE_NUM;
303 gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
305 err = rockchip_pcie_init_port(rockchip);
309 /* Fix the transmitted FTS count desired to exit from L0s. */
310 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
311 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
312 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
313 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
315 rockchip_pcie_set_power_limit(rockchip);
317 /* Set RC's clock architecture as common clock */
318 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
319 status |= PCI_EXP_LNKSTA_SLC << 16;
320 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
322 /* Set RC's RCB to 128 */
323 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
324 status |= PCI_EXP_LNKCTL_RCB;
325 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
327 /* Enable Gen1 training */
328 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
331 gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
333 /* 500ms timeout value should be enough for Gen1/2 training */
334 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
335 status, PCIE_LINK_UP(status), 20,
336 500 * USEC_PER_MSEC);
338 dev_err(dev, "PCIe link training gen1 timeout!\n");
339 goto err_power_off_phy;
342 if (rockchip->link_gen == 2) {
344 * Enable retrain for gen2. This should be configured only after
347 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
348 status |= PCI_EXP_LNKCTL_RL;
349 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
351 err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
352 status, PCIE_LINK_IS_GEN2(status), 20,
353 500 * USEC_PER_MSEC);
355 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
358 /* Check the final link width from negotiated lane counter from MGMT */
359 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
360 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
361 PCIE_CORE_PL_CONF_LANE_SHIFT);
362 dev_dbg(dev, "current link width is x%d\n", status);
364 /* Power off unused lane(s) */
365 rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
366 for (i = 0; i < MAX_LANE_NUM; i++) {
367 if (!(rockchip->lanes_map & BIT(i))) {
368 dev_dbg(dev, "idling lane %d\n", i);
369 phy_power_off(rockchip->phys[i]);
373 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
374 PCIE_CORE_CONFIG_VENDOR);
375 rockchip_pcie_write(rockchip,
376 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
377 PCIE_RC_CONFIG_RID_CCR);
379 /* Clear THP cap's next cap pointer to remove L1 substate cap */
380 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
381 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
382 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
384 /* Clear L0s from RC's link cap */
385 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) {
386 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
387 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
388 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
391 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR);
392 status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK;
393 status |= PCIE_RC_CONFIG_DCSR_MPS_256;
394 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR);
399 phy_power_off(rockchip->phys[i]);
402 phy_exit(rockchip->phys[i]);
406 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
408 struct rockchip_pcie *rockchip = arg;
409 struct device *dev = rockchip->dev;
413 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
414 if (reg & PCIE_CLIENT_INT_LOCAL) {
415 dev_dbg(dev, "local interrupt received\n");
416 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
417 if (sub_reg & PCIE_CORE_INT_PRFPE)
418 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
420 if (sub_reg & PCIE_CORE_INT_CRFPE)
421 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
423 if (sub_reg & PCIE_CORE_INT_RRPE)
424 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
426 if (sub_reg & PCIE_CORE_INT_PRFO)
427 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
429 if (sub_reg & PCIE_CORE_INT_CRFO)
430 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
432 if (sub_reg & PCIE_CORE_INT_RT)
433 dev_dbg(dev, "replay timer timed out\n");
435 if (sub_reg & PCIE_CORE_INT_RTR)
436 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
438 if (sub_reg & PCIE_CORE_INT_PE)
439 dev_dbg(dev, "phy error detected on receive side\n");
441 if (sub_reg & PCIE_CORE_INT_MTR)
442 dev_dbg(dev, "malformed TLP received from the link\n");
444 if (sub_reg & PCIE_CORE_INT_UCR)
445 dev_dbg(dev, "malformed TLP received from the link\n");
447 if (sub_reg & PCIE_CORE_INT_FCE)
448 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
450 if (sub_reg & PCIE_CORE_INT_CT)
451 dev_dbg(dev, "a request timed out waiting for completion\n");
453 if (sub_reg & PCIE_CORE_INT_UTC)
454 dev_dbg(dev, "unmapped TC error\n");
456 if (sub_reg & PCIE_CORE_INT_MMVC)
457 dev_dbg(dev, "MSI mask register changes\n");
459 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
460 } else if (reg & PCIE_CLIENT_INT_PHY) {
461 dev_dbg(dev, "phy link changes\n");
462 rockchip_pcie_update_txcredit_mui(rockchip);
463 rockchip_pcie_clr_bw_int(rockchip);
466 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
467 PCIE_CLIENT_INT_STATUS);
472 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
474 struct rockchip_pcie *rockchip = arg;
475 struct device *dev = rockchip->dev;
478 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
479 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
480 dev_dbg(dev, "legacy done interrupt received\n");
482 if (reg & PCIE_CLIENT_INT_MSG)
483 dev_dbg(dev, "message done interrupt received\n");
485 if (reg & PCIE_CLIENT_INT_HOT_RST)
486 dev_dbg(dev, "hot reset interrupt received\n");
488 if (reg & PCIE_CLIENT_INT_DPA)
489 dev_dbg(dev, "dpa interrupt received\n");
491 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
492 dev_dbg(dev, "fatal error interrupt received\n");
494 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
495 dev_dbg(dev, "no fatal error interrupt received\n");
497 if (reg & PCIE_CLIENT_INT_CORR_ERR)
498 dev_dbg(dev, "correctable error interrupt received\n");
500 if (reg & PCIE_CLIENT_INT_PHY)
501 dev_dbg(dev, "phy interrupt received\n");
503 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
504 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
505 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
506 PCIE_CLIENT_INT_NFATAL_ERR |
507 PCIE_CLIENT_INT_CORR_ERR |
508 PCIE_CLIENT_INT_PHY),
509 PCIE_CLIENT_INT_STATUS);
514 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
516 struct irq_chip *chip = irq_desc_get_chip(desc);
517 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
518 struct device *dev = rockchip->dev;
523 chained_irq_enter(chip, desc);
525 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
526 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
529 hwirq = ffs(reg) - 1;
532 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
534 generic_handle_irq(virq);
536 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
539 chained_irq_exit(chip, desc);
542 static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
545 struct device *dev = rockchip->dev;
546 struct platform_device *pdev = to_platform_device(dev);
548 irq = platform_get_irq_byname(pdev, "sys");
552 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
553 IRQF_SHARED, "pcie-sys", rockchip);
555 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
559 irq = platform_get_irq_byname(pdev, "legacy");
563 irq_set_chained_handler_and_data(irq,
564 rockchip_pcie_legacy_int_handler,
567 irq = platform_get_irq_byname(pdev, "client");
571 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
572 IRQF_SHARED, "pcie-client", rockchip);
574 dev_err(dev, "failed to request PCIe client IRQ\n");
582 * rockchip_pcie_parse_host_dt - Parse Device Tree
583 * @rockchip: PCIe port information
585 * Return: '0' on success and error value on failure
587 static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
589 struct device *dev = rockchip->dev;
592 err = rockchip_pcie_parse_dt(rockchip);
596 rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
597 if (IS_ERR(rockchip->vpcie12v)) {
598 if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
599 return PTR_ERR(rockchip->vpcie12v);
600 dev_info(dev, "no vpcie12v regulator found\n");
603 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
604 if (IS_ERR(rockchip->vpcie3v3)) {
605 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
606 return PTR_ERR(rockchip->vpcie3v3);
607 dev_info(dev, "no vpcie3v3 regulator found\n");
610 rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
611 if (IS_ERR(rockchip->vpcie1v8))
612 return PTR_ERR(rockchip->vpcie1v8);
614 rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
615 if (IS_ERR(rockchip->vpcie0v9))
616 return PTR_ERR(rockchip->vpcie0v9);
621 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
623 struct device *dev = rockchip->dev;
626 if (!IS_ERR(rockchip->vpcie12v)) {
627 err = regulator_enable(rockchip->vpcie12v);
629 dev_err(dev, "fail to enable vpcie12v regulator\n");
634 if (!IS_ERR(rockchip->vpcie3v3)) {
635 err = regulator_enable(rockchip->vpcie3v3);
637 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
638 goto err_disable_12v;
642 err = regulator_enable(rockchip->vpcie1v8);
644 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
645 goto err_disable_3v3;
648 err = regulator_enable(rockchip->vpcie0v9);
650 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
651 goto err_disable_1v8;
657 regulator_disable(rockchip->vpcie1v8);
659 if (!IS_ERR(rockchip->vpcie3v3))
660 regulator_disable(rockchip->vpcie3v3);
662 if (!IS_ERR(rockchip->vpcie12v))
663 regulator_disable(rockchip->vpcie12v);
668 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
670 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
671 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
672 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
675 rockchip_pcie_enable_bw_int(rockchip);
678 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
679 irq_hw_number_t hwirq)
681 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
682 irq_set_chip_data(irq, domain->host_data);
687 static const struct irq_domain_ops intx_domain_ops = {
688 .map = rockchip_pcie_intx_map,
691 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
693 struct device *dev = rockchip->dev;
694 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
697 dev_err(dev, "missing child interrupt-controller node\n");
701 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
702 &intx_domain_ops, rockchip);
704 if (!rockchip->irq_domain) {
705 dev_err(dev, "failed to get a INTx IRQ domain\n");
712 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
713 int region_no, int type, u8 num_pass_bits,
714 u32 lower_addr, u32 upper_addr)
721 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
723 if (num_pass_bits + 1 < 8)
725 if (num_pass_bits > 63)
727 if (region_no == 0) {
728 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
731 if (region_no != 0) {
732 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
736 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
738 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
739 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
740 ob_addr_1 = upper_addr;
741 ob_desc_0 = (1 << 23 | type);
743 rockchip_pcie_write(rockchip, ob_addr_0,
744 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
745 rockchip_pcie_write(rockchip, ob_addr_1,
746 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
747 rockchip_pcie_write(rockchip, ob_desc_0,
748 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
749 rockchip_pcie_write(rockchip, 0,
750 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
755 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
756 int region_no, u8 num_pass_bits,
757 u32 lower_addr, u32 upper_addr)
763 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
765 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
767 if (num_pass_bits > 63)
770 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
772 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
773 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
774 ib_addr_1 = upper_addr;
776 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
777 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
782 static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
784 struct device *dev = rockchip->dev;
785 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
786 struct resource_entry *entry;
792 rockchip_pcie_cfg_configuration_accesses(rockchip,
793 AXI_WRAPPER_TYPE0_CFG);
794 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
798 size = resource_size(entry->res);
799 pci_addr = entry->res->start - entry->offset;
800 rockchip->msg_bus_addr = pci_addr;
802 for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
803 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
804 AXI_WRAPPER_MEM_WRITE,
806 pci_addr + (reg_no << 20),
809 dev_err(dev, "program RC mem outbound ATU failed\n");
814 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
816 dev_err(dev, "program RC mem inbound ATU failed\n");
820 entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
824 /* store the register number offset to program RC io outbound ATU */
827 size = resource_size(entry->res);
828 pci_addr = entry->res->start - entry->offset;
830 for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
831 err = rockchip_pcie_prog_ob_atu(rockchip,
833 AXI_WRAPPER_IO_WRITE,
835 pci_addr + (reg_no << 20),
838 dev_err(dev, "program RC io outbound ATU failed\n");
843 /* assign message regions */
844 rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1 + offset,
848 rockchip->msg_bus_addr += ((reg_no + offset) << 20);
852 static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip)
857 /* send PME_TURN_OFF message */
858 writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
860 /* read LTSSM and wait for falling into L2 link state */
861 err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
862 value, PCIE_LINK_IS_L2(value), 20,
863 jiffies_to_usecs(5 * HZ));
865 dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
872 static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev)
874 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
877 /* disable core and cli int since we don't need to ack PME_ACK */
878 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) |
879 PCIE_CLIENT_INT_CLI, PCIE_CLIENT_INT_MASK);
880 rockchip_pcie_write(rockchip, (u32)PCIE_CORE_INT, PCIE_CORE_INT_MASK);
882 ret = rockchip_pcie_wait_l2(rockchip);
884 rockchip_pcie_enable_interrupts(rockchip);
888 rockchip_pcie_deinit_phys(rockchip);
890 rockchip_pcie_disable_clocks(rockchip);
892 regulator_disable(rockchip->vpcie0v9);
897 static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev)
899 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
902 err = regulator_enable(rockchip->vpcie0v9);
904 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
908 err = rockchip_pcie_enable_clocks(rockchip);
910 goto err_disable_0v9;
912 err = rockchip_pcie_host_init_port(rockchip);
914 goto err_pcie_resume;
916 err = rockchip_pcie_cfg_atu(rockchip);
918 goto err_err_deinit_port;
920 /* Need this to enter L1 again */
921 rockchip_pcie_update_txcredit_mui(rockchip);
922 rockchip_pcie_enable_interrupts(rockchip);
927 rockchip_pcie_deinit_phys(rockchip);
929 rockchip_pcie_disable_clocks(rockchip);
931 regulator_disable(rockchip->vpcie0v9);
935 static int rockchip_pcie_probe(struct platform_device *pdev)
937 struct rockchip_pcie *rockchip;
938 struct device *dev = &pdev->dev;
939 struct pci_host_bridge *bridge;
945 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rockchip));
949 rockchip = pci_host_bridge_priv(bridge);
951 platform_set_drvdata(pdev, rockchip);
953 rockchip->is_rc = true;
955 err = rockchip_pcie_parse_host_dt(rockchip);
959 err = rockchip_pcie_enable_clocks(rockchip);
963 err = rockchip_pcie_set_vpcie(rockchip);
965 dev_err(dev, "failed to set vpcie regulator\n");
969 err = rockchip_pcie_host_init_port(rockchip);
973 err = rockchip_pcie_init_irq_domain(rockchip);
975 goto err_deinit_port;
977 err = rockchip_pcie_cfg_atu(rockchip);
979 goto err_remove_irq_domain;
981 rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
982 if (!rockchip->msg_region) {
984 goto err_remove_irq_domain;
987 bridge->sysdata = rockchip;
988 bridge->ops = &rockchip_pcie_ops;
990 err = rockchip_pcie_setup_irq(rockchip);
992 goto err_remove_irq_domain;
994 rockchip_pcie_enable_interrupts(rockchip);
996 err = pci_host_probe(bridge);
998 goto err_remove_irq_domain;
1002 err_remove_irq_domain:
1003 irq_domain_remove(rockchip->irq_domain);
1005 rockchip_pcie_deinit_phys(rockchip);
1007 if (!IS_ERR(rockchip->vpcie12v))
1008 regulator_disable(rockchip->vpcie12v);
1009 if (!IS_ERR(rockchip->vpcie3v3))
1010 regulator_disable(rockchip->vpcie3v3);
1011 regulator_disable(rockchip->vpcie1v8);
1012 regulator_disable(rockchip->vpcie0v9);
1014 rockchip_pcie_disable_clocks(rockchip);
1018 static int rockchip_pcie_remove(struct platform_device *pdev)
1020 struct device *dev = &pdev->dev;
1021 struct rockchip_pcie *rockchip = dev_get_drvdata(dev);
1022 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
1024 pci_stop_root_bus(bridge->bus);
1025 pci_remove_root_bus(bridge->bus);
1026 irq_domain_remove(rockchip->irq_domain);
1028 rockchip_pcie_deinit_phys(rockchip);
1030 rockchip_pcie_disable_clocks(rockchip);
1032 if (!IS_ERR(rockchip->vpcie12v))
1033 regulator_disable(rockchip->vpcie12v);
1034 if (!IS_ERR(rockchip->vpcie3v3))
1035 regulator_disable(rockchip->vpcie3v3);
1036 regulator_disable(rockchip->vpcie1v8);
1037 regulator_disable(rockchip->vpcie0v9);
1042 static const struct dev_pm_ops rockchip_pcie_pm_ops = {
1043 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend_noirq,
1044 rockchip_pcie_resume_noirq)
1047 static const struct of_device_id rockchip_pcie_of_match[] = {
1048 { .compatible = "rockchip,rk3399-pcie", },
1051 MODULE_DEVICE_TABLE(of, rockchip_pcie_of_match);
1053 static struct platform_driver rockchip_pcie_driver = {
1055 .name = "rockchip-pcie",
1056 .of_match_table = rockchip_pcie_of_match,
1057 .pm = &rockchip_pcie_pm_ops,
1059 .probe = rockchip_pcie_probe,
1060 .remove = rockchip_pcie_remove,
1062 module_platform_driver(rockchip_pcie_driver);
1064 MODULE_AUTHOR("Rockchip Inc");
1065 MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
1066 MODULE_LICENSE("GPL v2");