1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
5 * Copyright (c) 2018 Rockchip, Inc.
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
11 #include <linux/configfs.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
15 #include <linux/pci-epc.h>
16 #include <linux/platform_device.h>
17 #include <linux/pci-epf.h>
18 #include <linux/sizes.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
25 * @max_regions: maximum number of regions supported by hardware
26 * @ob_region_map: bitmask of mapped outbound regions
27 * @ob_addr: base addresses in the AXI bus where the outbound regions start
28 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
29 * dedicated outbound regions is mapped.
30 * @irq_cpu_addr: base address in the CPU space where a write access triggers
31 * the sending of a memory write (MSI) / normal message (legacy
32 * IRQ) TLP through the PCIe bus.
33 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
34 * dedicated outbound region.
35 * @irq_pci_fn: the latest PCI function that has updated the mapping of
36 * the MSI/legacy IRQ dedicated outbound region.
37 * @irq_pending: bitmask of asserted legacy IRQs.
39 struct rockchip_pcie_ep {
40 struct rockchip_pcie rockchip;
43 unsigned long ob_region_map;
45 phys_addr_t irq_phys_addr;
46 void __iomem *irq_cpu_addr;
52 static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
55 rockchip_pcie_write(rockchip, 0,
56 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
57 rockchip_pcie_write(rockchip, 0,
58 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
59 rockchip_pcie_write(rockchip, 0,
60 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
61 rockchip_pcie_write(rockchip, 0,
62 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
63 rockchip_pcie_write(rockchip, 0,
64 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region));
65 rockchip_pcie_write(rockchip, 0,
66 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region));
69 static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
70 u32 r, u32 type, u64 cpu_addr,
71 u64 pci_addr, size_t size)
73 u64 sz = 1ULL << fls64(size - 1);
74 int num_pass_bits = ilog2(sz);
75 u32 addr0, addr1, desc0, desc1;
76 bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG);
78 /* The minimal region size is 1MB */
79 if (num_pass_bits < 8)
82 cpu_addr -= rockchip->mem_res->start;
83 addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) &
84 PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
85 (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
86 addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr);
87 desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
91 rockchip_pcie_write(rockchip, 0,
92 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
93 rockchip_pcie_write(rockchip, 0,
94 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
95 rockchip_pcie_write(rockchip, desc0,
96 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
97 rockchip_pcie_write(rockchip, desc1,
98 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
100 /* PCI bus address region */
101 rockchip_pcie_write(rockchip, addr0,
102 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
103 rockchip_pcie_write(rockchip, addr1,
104 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
105 rockchip_pcie_write(rockchip, desc0,
106 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
107 rockchip_pcie_write(rockchip, desc1,
108 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
111 ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
112 (lower_32_bits(cpu_addr) &
113 PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
114 addr1 = upper_32_bits(cpu_addr);
117 /* CPU bus address region */
118 rockchip_pcie_write(rockchip, addr0,
119 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r));
120 rockchip_pcie_write(rockchip, addr1,
121 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r));
124 static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
125 struct pci_epf_header *hdr)
128 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
129 struct rockchip_pcie *rockchip = &ep->rockchip;
131 /* All functions share the same vendor ID with function 0 */
133 u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
134 (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
136 rockchip_pcie_write(rockchip, vid_regs,
137 PCIE_CORE_CONFIG_VENDOR);
140 reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);
141 reg = (reg & 0xFFFF) | (hdr->deviceid << 16);
142 rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);
144 rockchip_pcie_write(rockchip,
146 hdr->progif_code << 8 |
147 hdr->subclass_code << 16 |
148 hdr->baseclass_code << 24,
149 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
150 rockchip_pcie_write(rockchip, hdr->cache_line_size,
151 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
152 PCI_CACHE_LINE_SIZE);
153 rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
154 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
155 PCI_SUBSYSTEM_VENDOR_ID);
156 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
157 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
163 static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
164 struct pci_epf_bar *epf_bar)
166 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
167 struct rockchip_pcie *rockchip = &ep->rockchip;
168 dma_addr_t bar_phys = epf_bar->phys_addr;
169 enum pci_barno bar = epf_bar->barno;
170 int flags = epf_bar->flags;
171 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
174 /* BAR size is 2^(aperture + 7) */
175 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
178 * roundup_pow_of_two() returns an unsigned long, which is not suited
181 sz = 1ULL << fls64(sz - 1);
182 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
184 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
185 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
187 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
188 bool is_64bits = sz > SZ_2G;
190 if (is_64bits && (bar & 1))
193 if (is_64bits && is_prefetch)
195 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
196 else if (is_prefetch)
198 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
200 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
202 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
206 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
209 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
213 addr0 = lower_32_bits(bar_phys);
214 addr1 = upper_32_bits(bar_phys);
216 cfg = rockchip_pcie_read(rockchip, reg);
217 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
218 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
219 cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
220 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
222 rockchip_pcie_write(rockchip, cfg, reg);
223 rockchip_pcie_write(rockchip, addr0,
224 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
225 rockchip_pcie_write(rockchip, addr1,
226 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
231 static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
232 struct pci_epf_bar *epf_bar)
234 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
235 struct rockchip_pcie *rockchip = &ep->rockchip;
236 u32 reg, cfg, b, ctrl;
237 enum pci_barno bar = epf_bar->barno;
240 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
243 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
247 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
248 cfg = rockchip_pcie_read(rockchip, reg);
249 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
250 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
251 cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
253 rockchip_pcie_write(rockchip, cfg, reg);
254 rockchip_pcie_write(rockchip, 0x0,
255 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
256 rockchip_pcie_write(rockchip, 0x0,
257 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
260 static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn,
261 phys_addr_t addr, u64 pci_addr,
264 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
265 struct rockchip_pcie *pcie = &ep->rockchip;
268 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
270 * Region 0 is reserved for configuration space and shouldn't
271 * be used elsewhere per TRM, so leave it out.
273 if (r >= ep->max_regions - 1) {
274 dev_err(&epc->dev, "no free outbound region\n");
278 rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr,
281 set_bit(r, &ep->ob_region_map);
282 ep->ob_addr[r] = addr;
287 static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
290 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
291 struct rockchip_pcie *rockchip = &ep->rockchip;
294 for (r = 0; r < ep->max_regions - 1; r++)
295 if (ep->ob_addr[r] == addr)
299 * Region 0 is reserved for configuration space and shouldn't
300 * be used elsewhere per TRM, so leave it out.
302 if (r == ep->max_regions - 1)
305 rockchip_pcie_clear_ep_ob_atu(rockchip, r);
308 clear_bit(r, &ep->ob_region_map);
311 static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn,
314 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
315 struct rockchip_pcie *rockchip = &ep->rockchip;
318 flags = rockchip_pcie_read(rockchip,
319 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
320 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
321 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
323 (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
324 (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
325 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
326 rockchip_pcie_write(rockchip, flags,
327 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
328 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
332 static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
334 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
335 struct rockchip_pcie *rockchip = &ep->rockchip;
338 flags = rockchip_pcie_read(rockchip,
339 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
340 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
341 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
344 return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
345 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
348 static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
349 u8 intx, bool do_assert)
351 struct rockchip_pcie *rockchip = &ep->rockchip;
356 ep->irq_pending |= BIT(intx);
357 rockchip_pcie_write(rockchip,
358 PCIE_CLIENT_INT_IN_ASSERT |
359 PCIE_CLIENT_INT_PEND_ST_PEND,
360 PCIE_CLIENT_LEGACY_INT_CTRL);
362 ep->irq_pending &= ~BIT(intx);
363 rockchip_pcie_write(rockchip,
364 PCIE_CLIENT_INT_IN_DEASSERT |
365 PCIE_CLIENT_INT_PEND_ST_NORMAL,
366 PCIE_CLIENT_LEGACY_INT_CTRL);
370 static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
375 cmd = rockchip_pcie_read(&ep->rockchip,
376 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
377 ROCKCHIP_PCIE_EP_CMD_STATUS);
379 if (cmd & PCI_COMMAND_INTX_DISABLE)
383 * Should add some delay between toggling INTx per TRM vaguely saying
384 * it depends on some cycles of the AHB bus clock to function it. So
385 * add sufficient 1ms here.
387 rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
389 rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
393 static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
396 struct rockchip_pcie *rockchip = &ep->rockchip;
397 u32 flags, mme, data, data_mask;
399 u64 pci_addr, pci_addr_mask = 0xff;
401 /* Check MSI enable bit */
402 flags = rockchip_pcie_read(&ep->rockchip,
403 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
404 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
405 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
408 /* Get MSI numbers from MME */
409 mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
410 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
411 msi_count = 1 << mme;
412 if (!interrupt_num || interrupt_num > msi_count)
415 /* Set MSI private data */
416 data_mask = msi_count - 1;
417 data = rockchip_pcie_read(rockchip,
418 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
419 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
421 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
423 /* Get MSI PCI address */
424 pci_addr = rockchip_pcie_read(rockchip,
425 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
426 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
429 pci_addr |= rockchip_pcie_read(rockchip,
430 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
431 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
433 pci_addr &= GENMASK_ULL(63, 2);
435 /* Set the outbound region if needed. */
436 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
437 ep->irq_pci_fn != fn)) {
438 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1,
439 AXI_WRAPPER_MEM_WRITE,
441 pci_addr & ~pci_addr_mask,
443 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
447 writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
451 static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
452 enum pci_epc_irq_type type,
455 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
458 case PCI_EPC_IRQ_LEGACY:
459 return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
460 case PCI_EPC_IRQ_MSI:
461 return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
467 static int rockchip_pcie_ep_start(struct pci_epc *epc)
469 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
470 struct rockchip_pcie *rockchip = &ep->rockchip;
475 list_for_each_entry(epf, &epc->pci_epf, list)
476 cfg |= BIT(epf->func_no);
478 rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
480 list_for_each_entry(epf, &epc->pci_epf, list)
486 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
487 .write_header = rockchip_pcie_ep_write_header,
488 .set_bar = rockchip_pcie_ep_set_bar,
489 .clear_bar = rockchip_pcie_ep_clear_bar,
490 .map_addr = rockchip_pcie_ep_map_addr,
491 .unmap_addr = rockchip_pcie_ep_unmap_addr,
492 .set_msi = rockchip_pcie_ep_set_msi,
493 .get_msi = rockchip_pcie_ep_get_msi,
494 .raise_irq = rockchip_pcie_ep_raise_irq,
495 .start = rockchip_pcie_ep_start,
498 static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
499 struct rockchip_pcie_ep *ep)
501 struct device *dev = rockchip->dev;
504 err = rockchip_pcie_parse_dt(rockchip);
508 err = rockchip_pcie_get_phys(rockchip);
512 err = of_property_read_u32(dev->of_node,
513 "rockchip,max-outbound-regions",
515 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
516 ep->max_regions = MAX_REGION_LIMIT;
518 err = of_property_read_u8(dev->of_node, "max-functions",
519 &ep->epc->max_functions);
521 ep->epc->max_functions = 1;
526 static const struct of_device_id rockchip_pcie_ep_of_match[] = {
527 { .compatible = "rockchip,rk3399-pcie-ep"},
531 static int rockchip_pcie_ep_probe(struct platform_device *pdev)
533 struct device *dev = &pdev->dev;
534 struct rockchip_pcie_ep *ep;
535 struct rockchip_pcie *rockchip;
540 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
544 rockchip = &ep->rockchip;
545 rockchip->is_rc = false;
548 epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
550 dev_err(dev, "failed to create epc device\n");
555 epc_set_drvdata(epc, ep);
557 err = rockchip_pcie_parse_ep_dt(rockchip, ep);
561 err = rockchip_pcie_enable_clocks(rockchip);
565 err = rockchip_pcie_init_port(rockchip);
567 goto err_disable_clocks;
569 /* Establish the link automatically */
570 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
573 max_regions = ep->max_regions;
574 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),
579 goto err_uninit_port;
582 /* Only enable function 0 by default */
583 rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
585 err = pci_epc_mem_init(epc, rockchip->mem_res->start,
586 resource_size(rockchip->mem_res));
588 dev_err(dev, "failed to initialize the memory space\n");
589 goto err_uninit_port;
592 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
594 if (!ep->irq_cpu_addr) {
595 dev_err(dev, "failed to reserve memory space for MSI\n");
597 goto err_epc_mem_exit;
600 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
602 rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
607 pci_epc_mem_exit(epc);
609 rockchip_pcie_deinit_phys(rockchip);
611 rockchip_pcie_disable_clocks(rockchip);
615 static struct platform_driver rockchip_pcie_ep_driver = {
617 .name = "rockchip-pcie-ep",
618 .of_match_table = rockchip_pcie_ep_of_match,
620 .probe = rockchip_pcie_ep_probe,
623 builtin_platform_driver(rockchip_pcie_ep_driver);