1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
4 * Copyright (C) 2015 Broadcom Corporation
7 #include <linux/kernel.h>
10 #include <linux/clk.h>
11 #include <linux/module.h>
12 #include <linux/mbus.h>
13 #include <linux/slab.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqchip/arm-gic-v3.h>
17 #include <linux/platform_device.h>
18 #include <linux/of_address.h>
19 #include <linux/of_pci.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/phy/phy.h>
24 #include "pcie-iproc.h"
26 #define EP_PERST_SOURCE_SELECT_SHIFT 2
27 #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
28 #define EP_MODE_SURVIVE_PERST_SHIFT 1
29 #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
31 #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
35 #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT)
37 #define MSI_ENABLE_CFG_SHIFT 0
38 #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT)
40 #define CFG_IND_ADDR_MASK 0x00001ffc
42 #define CFG_ADDR_BUS_NUM_SHIFT 20
43 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
44 #define CFG_ADDR_DEV_NUM_SHIFT 15
45 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
46 #define CFG_ADDR_FUNC_NUM_SHIFT 12
47 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
48 #define CFG_ADDR_REG_NUM_SHIFT 2
49 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
50 #define CFG_ADDR_CFG_TYPE_SHIFT 0
51 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
53 #define SYS_RC_INTX_MASK 0xf
55 #define PCIE_PHYLINKUP_SHIFT 3
56 #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
57 #define PCIE_DL_ACTIVE_SHIFT 2
58 #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
60 #define APB_ERR_EN_SHIFT 0
61 #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
63 #define CFG_RD_SUCCESS 0
67 #define CFG_RETRY_STATUS 0xffff0001
68 #define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milliseconds */
70 /* derive the enum index of the outbound/inbound mapping registers */
71 #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
74 * Maximum number of outbound mapping window sizes that can be supported by any
75 * OARR/OMAP mapping pair
77 #define MAX_NUM_OB_WINDOW_SIZES 4
79 #define OARR_VALID_SHIFT 0
80 #define OARR_VALID BIT(OARR_VALID_SHIFT)
81 #define OARR_SIZE_CFG_SHIFT 1
84 * Maximum number of inbound mapping region sizes that can be supported by an
87 #define MAX_NUM_IB_REGION_SIZES 9
89 #define IMAP_VALID_SHIFT 0
90 #define IMAP_VALID BIT(IMAP_VALID_SHIFT)
92 #define IPROC_PCI_PM_CAP 0x48
93 #define IPROC_PCI_PM_CAP_MASK 0xffff
94 #define IPROC_PCI_EXP_CAP 0xac
96 #define IPROC_PCIE_REG_INVALID 0xffff
99 * iProc PCIe outbound mapping controller specific parameters
101 * @window_sizes: list of supported outbound mapping window sizes in MB
102 * @nr_sizes: number of supported outbound mapping window sizes
104 struct iproc_pcie_ob_map {
105 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
106 unsigned int nr_sizes;
109 static const struct iproc_pcie_ob_map paxb_ob_map[] = {
112 .window_sizes = { 128, 256 },
117 .window_sizes = { 128, 256 },
122 static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
125 .window_sizes = { 128, 256 },
130 .window_sizes = { 128, 256 },
135 .window_sizes = { 128, 256, 512, 1024 },
140 .window_sizes = { 128, 256, 512, 1024 },
146 * iProc PCIe inbound mapping type
148 enum iproc_pcie_ib_map_type {
150 IPROC_PCIE_IB_MAP_MEM = 0,
152 /* for device I/O memory */
153 IPROC_PCIE_IB_MAP_IO,
155 /* invalid or unused */
156 IPROC_PCIE_IB_MAP_INVALID
160 * iProc PCIe inbound mapping controller specific parameters
162 * @type: inbound mapping region type
163 * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or
165 * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or
166 * GB, depending on the size unit
167 * @nr_sizes: number of supported inbound mapping region sizes
168 * @nr_windows: number of supported inbound mapping windows for the region
169 * @imap_addr_offset: register offset between the upper and lower 32-bit
170 * IMAP address registers
171 * @imap_window_offset: register offset between each IMAP window
173 struct iproc_pcie_ib_map {
174 enum iproc_pcie_ib_map_type type;
175 unsigned int size_unit;
176 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
177 unsigned int nr_sizes;
178 unsigned int nr_windows;
179 u16 imap_addr_offset;
180 u16 imap_window_offset;
183 static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
186 .type = IPROC_PCIE_IB_MAP_IO,
188 .region_sizes = { 32 },
191 .imap_addr_offset = 0x40,
192 .imap_window_offset = 0x4,
196 .type = IPROC_PCIE_IB_MAP_MEM,
198 .region_sizes = { 8 },
201 .imap_addr_offset = 0x4,
202 .imap_window_offset = 0x8,
207 .type = IPROC_PCIE_IB_MAP_MEM,
209 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
213 .imap_addr_offset = 0x4,
214 .imap_window_offset = 0x8,
218 .type = IPROC_PCIE_IB_MAP_MEM,
220 .region_sizes = { 1, 2, 4, 8, 16, 32 },
223 .imap_addr_offset = 0x4,
224 .imap_window_offset = 0x8,
228 .type = IPROC_PCIE_IB_MAP_MEM,
230 .region_sizes = { 32, 64, 128, 256, 512 },
233 .imap_addr_offset = 0x4,
234 .imap_window_offset = 0x8,
239 * iProc PCIe host registers
241 enum iproc_pcie_reg {
242 /* clock/reset signal control */
243 IPROC_PCIE_CLK_CTRL = 0,
246 * To allow MSI to be steered to an external MSI controller (e.g., ARM
249 IPROC_PCIE_MSI_GIC_MODE,
252 * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the
253 * window where the MSI posted writes are written, for the writes to be
254 * interpreted as MSI writes.
256 IPROC_PCIE_MSI_BASE_ADDR,
257 IPROC_PCIE_MSI_WINDOW_SIZE,
260 * To hold the address of the register where the MSI writes are
261 * programed. When ARM GICv3 ITS is used, this should be programmed
262 * with the address of the GITS_TRANSLATER register.
264 IPROC_PCIE_MSI_ADDR_LO,
265 IPROC_PCIE_MSI_ADDR_HI,
268 IPROC_PCIE_MSI_EN_CFG,
270 /* allow access to root complex configuration space */
271 IPROC_PCIE_CFG_IND_ADDR,
272 IPROC_PCIE_CFG_IND_DATA,
274 /* allow access to device configuration space */
281 /* outbound address mapping */
291 /* inbound address mapping */
303 /* config read status */
304 IPROC_PCIE_CFG_RD_STATUS,
307 IPROC_PCIE_LINK_STATUS,
309 /* enable APB error for unsupported requests */
310 IPROC_PCIE_APB_ERR_EN,
312 /* total number of core registers */
313 IPROC_PCIE_MAX_NUM_REG,
316 /* iProc PCIe PAXB BCMA registers */
317 static const u16 iproc_pcie_reg_paxb_bcma[IPROC_PCIE_MAX_NUM_REG] = {
318 [IPROC_PCIE_CLK_CTRL] = 0x000,
319 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
320 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
321 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
322 [IPROC_PCIE_CFG_DATA] = 0x1fc,
323 [IPROC_PCIE_INTX_EN] = 0x330,
324 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
327 /* iProc PCIe PAXB registers */
328 static const u16 iproc_pcie_reg_paxb[IPROC_PCIE_MAX_NUM_REG] = {
329 [IPROC_PCIE_CLK_CTRL] = 0x000,
330 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
331 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
332 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
333 [IPROC_PCIE_CFG_DATA] = 0x1fc,
334 [IPROC_PCIE_INTX_EN] = 0x330,
335 [IPROC_PCIE_OARR0] = 0xd20,
336 [IPROC_PCIE_OMAP0] = 0xd40,
337 [IPROC_PCIE_OARR1] = 0xd28,
338 [IPROC_PCIE_OMAP1] = 0xd48,
339 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
340 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
343 /* iProc PCIe PAXB v2 registers */
344 static const u16 iproc_pcie_reg_paxb_v2[IPROC_PCIE_MAX_NUM_REG] = {
345 [IPROC_PCIE_CLK_CTRL] = 0x000,
346 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
347 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
348 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
349 [IPROC_PCIE_CFG_DATA] = 0x1fc,
350 [IPROC_PCIE_INTX_EN] = 0x330,
351 [IPROC_PCIE_OARR0] = 0xd20,
352 [IPROC_PCIE_OMAP0] = 0xd40,
353 [IPROC_PCIE_OARR1] = 0xd28,
354 [IPROC_PCIE_OMAP1] = 0xd48,
355 [IPROC_PCIE_OARR2] = 0xd60,
356 [IPROC_PCIE_OMAP2] = 0xd68,
357 [IPROC_PCIE_OARR3] = 0xdf0,
358 [IPROC_PCIE_OMAP3] = 0xdf8,
359 [IPROC_PCIE_IARR0] = 0xd00,
360 [IPROC_PCIE_IMAP0] = 0xc00,
361 [IPROC_PCIE_IARR1] = 0xd08,
362 [IPROC_PCIE_IMAP1] = 0xd70,
363 [IPROC_PCIE_IARR2] = 0xd10,
364 [IPROC_PCIE_IMAP2] = 0xcc0,
365 [IPROC_PCIE_IARR3] = 0xe00,
366 [IPROC_PCIE_IMAP3] = 0xe08,
367 [IPROC_PCIE_IARR4] = 0xe68,
368 [IPROC_PCIE_IMAP4] = 0xe70,
369 [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
370 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
371 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
374 /* iProc PCIe PAXC v1 registers */
375 static const u16 iproc_pcie_reg_paxc[IPROC_PCIE_MAX_NUM_REG] = {
376 [IPROC_PCIE_CLK_CTRL] = 0x000,
377 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
378 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
379 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
380 [IPROC_PCIE_CFG_DATA] = 0x1fc,
383 /* iProc PCIe PAXC v2 registers */
384 static const u16 iproc_pcie_reg_paxc_v2[IPROC_PCIE_MAX_NUM_REG] = {
385 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
386 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
387 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
388 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
389 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
390 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
391 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
392 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
393 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
394 [IPROC_PCIE_CFG_DATA] = 0x1fc,
398 * List of device IDs of controllers that have corrupted capability list that
401 static const u16 iproc_pcie_corrupt_cap_did[] = {
408 static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
410 struct iproc_pcie *pcie = bus->sysdata;
414 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
416 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
419 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
420 enum iproc_pcie_reg reg)
422 return pcie->reg_offsets[reg];
425 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
426 enum iproc_pcie_reg reg)
428 u16 offset = iproc_pcie_reg_offset(pcie, reg);
430 if (iproc_pcie_reg_is_invalid(offset))
433 return readl(pcie->base + offset);
436 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
437 enum iproc_pcie_reg reg, u32 val)
439 u16 offset = iproc_pcie_reg_offset(pcie, reg);
441 if (iproc_pcie_reg_is_invalid(offset))
444 writel(val, pcie->base + offset);
448 * APB error forwarding can be disabled during access of configuration
449 * registers of the endpoint device, to prevent unsupported requests
450 * (typically seen during enumeration with multi-function devices) from
451 * triggering a system exception.
453 static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,
456 struct iproc_pcie *pcie = iproc_data(bus);
459 if (bus->number && pcie->has_apb_err_disable) {
460 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
465 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
469 static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
478 /* EP device access */
479 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
480 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
481 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
482 (where & CFG_ADDR_REG_NUM_MASK) |
483 (1 & CFG_ADDR_CFG_TYPE_MASK);
485 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
486 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
488 if (iproc_pcie_reg_is_invalid(offset))
491 return (pcie->base + offset);
494 static unsigned int iproc_pcie_cfg_retry(struct iproc_pcie *pcie,
495 void __iomem *cfg_data_p)
497 int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
502 * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only
503 * affects config reads of the Vendor ID. For config writes or any
504 * other config reads, the Root may automatically reissue the
505 * configuration request again as a new request.
507 * For config reads, this hardware returns CFG_RETRY_STATUS data
508 * when it receives a CRS completion, regardless of the address of
509 * the read or the CRS Software Visibility Enable bit. As a
510 * partial workaround for this, we retry in software any read that
511 * returns CFG_RETRY_STATUS.
513 * Note that a non-Vendor ID config register may have a value of
514 * CFG_RETRY_STATUS. If we read that, we can't distinguish it from
515 * a CRS completion, so we will incorrectly retry the read and
516 * eventually return the wrong data (0xffffffff).
518 data = readl(cfg_data_p);
519 while (data == CFG_RETRY_STATUS && timeout--) {
521 * CRS state is set in CFG_RD status register
522 * This will handle the case where CFG_RETRY_STATUS is
525 status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS);
526 if (status != CFG_RD_CRS)
530 data = readl(cfg_data_p);
533 if (data == CFG_RETRY_STATUS)
539 static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, u32 *val)
543 switch (where & ~0x3) {
548 * Activate fixup for those controllers that have corrupted
549 * capability list registers
551 for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++)
552 if (dev_id == iproc_pcie_corrupt_cap_did[i])
553 pcie->fix_paxc_cap = true;
556 case IPROC_PCI_PM_CAP:
557 if (pcie->fix_paxc_cap) {
558 /* advertise PM, force next capability to PCIe */
559 *val &= ~IPROC_PCI_PM_CAP_MASK;
560 *val |= IPROC_PCI_EXP_CAP << 8 | PCI_CAP_ID_PM;
564 case IPROC_PCI_EXP_CAP:
565 if (pcie->fix_paxc_cap) {
566 /* advertise root port, version 2, terminate here */
567 *val = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2) << 16 |
572 case IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL:
573 /* Don't advertise CRS SV support */
574 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
582 static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
583 int where, int size, u32 *val)
585 struct iproc_pcie *pcie = iproc_data(bus);
586 unsigned int slot = PCI_SLOT(devfn);
587 unsigned int fn = PCI_FUNC(devfn);
588 unsigned int busno = bus->number;
589 void __iomem *cfg_data_p;
593 /* root complex access */
595 ret = pci_generic_config_read32(bus, devfn, where, size, val);
596 if (ret == PCIBIOS_SUCCESSFUL)
597 iproc_pcie_fix_cap(pcie, where, val);
602 cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
605 return PCIBIOS_DEVICE_NOT_FOUND;
607 data = iproc_pcie_cfg_retry(pcie, cfg_data_p);
611 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
614 * For PAXC and PAXCv2, the total number of PFs that one can enumerate
615 * depends on the firmware configuration. Unfortunately, due to an ASIC
616 * bug, unconfigured PFs cannot be properly hidden from the root
617 * complex. As a result, write access to these PFs will cause bus lock
618 * up on the embedded processor
620 * Since all unconfigured PFs are left with an incorrect, staled device
621 * ID of 0x168e (PCI_DEVICE_ID_NX2_57810), we try to catch those access
622 * early here and reject them all
624 #define DEVICE_ID_MASK 0xffff0000
625 #define DEVICE_ID_SHIFT 16
626 if (pcie->rej_unconfig_pf &&
627 (where & CFG_ADDR_REG_NUM_MASK) == PCI_VENDOR_ID)
628 if ((*val & DEVICE_ID_MASK) ==
629 (PCI_DEVICE_ID_NX2_57810 << DEVICE_ID_SHIFT))
630 return PCIBIOS_FUNC_NOT_SUPPORTED;
632 return PCIBIOS_SUCCESSFUL;
636 * Note access to the configuration registers are protected at the higher layer
637 * by 'pci_lock' in drivers/pci/access.c
639 static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie,
640 int busno, unsigned int devfn,
643 unsigned slot = PCI_SLOT(devfn);
644 unsigned fn = PCI_FUNC(devfn);
647 /* root complex access */
649 if (slot > 0 || fn > 0)
652 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
653 where & CFG_IND_ADDR_MASK);
654 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
655 if (iproc_pcie_reg_is_invalid(offset))
658 return (pcie->base + offset);
661 return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
664 static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus,
668 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn,
672 static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
673 unsigned int devfn, int where,
678 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
681 return PCIBIOS_DEVICE_NOT_FOUND;
687 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
689 return PCIBIOS_SUCCESSFUL;
692 static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
693 unsigned int devfn, int where,
699 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
701 return PCIBIOS_DEVICE_NOT_FOUND;
705 return PCIBIOS_SUCCESSFUL;
708 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
709 tmp = readl(addr) & mask;
710 tmp |= val << ((where & 0x3) * 8);
713 return PCIBIOS_SUCCESSFUL;
716 static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
717 int where, int size, u32 *val)
720 struct iproc_pcie *pcie = iproc_data(bus);
722 iproc_pcie_apb_err_disable(bus, true);
723 if (pcie->iproc_cfg_read)
724 ret = iproc_pcie_config_read(bus, devfn, where, size, val);
726 ret = pci_generic_config_read32(bus, devfn, where, size, val);
727 iproc_pcie_apb_err_disable(bus, false);
732 static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn,
733 int where, int size, u32 val)
737 iproc_pcie_apb_err_disable(bus, true);
738 ret = pci_generic_config_write32(bus, devfn, where, size, val);
739 iproc_pcie_apb_err_disable(bus, false);
744 static struct pci_ops iproc_pcie_ops = {
745 .map_bus = iproc_pcie_bus_map_cfg_bus,
746 .read = iproc_pcie_config_read32,
747 .write = iproc_pcie_config_write32,
750 static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert)
755 * PAXC and the internal emulated endpoint device downstream should not
756 * be reset. If firmware has been loaded on the endpoint device at an
757 * earlier boot stage, reset here causes issues.
759 if (pcie->ep_is_internal)
763 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
764 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
766 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
769 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
770 val |= RC_PCIE_RST_OUTPUT;
771 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
776 int iproc_pcie_shutdown(struct iproc_pcie *pcie)
778 iproc_pcie_perst_ctrl(pcie, true);
783 EXPORT_SYMBOL_GPL(iproc_pcie_shutdown);
785 static int iproc_pcie_check_link(struct iproc_pcie *pcie)
787 struct device *dev = pcie->dev;
788 u32 hdr_type, link_ctrl, link_status, class, val;
789 bool link_is_active = false;
792 * PAXC connects to emulated endpoint devices directly and does not
793 * have a Serdes. Therefore skip the link detection logic here.
795 if (pcie->ep_is_internal)
798 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
799 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
800 dev_err(dev, "PHY or data link is INACTIVE!\n");
804 /* make sure we are not in EP mode */
805 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);
806 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
807 dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type);
811 /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
812 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
813 #define PCI_CLASS_BRIDGE_MASK 0xffff00
814 #define PCI_CLASS_BRIDGE_SHIFT 8
815 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
817 class &= ~PCI_CLASS_BRIDGE_MASK;
818 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
819 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
822 /* check link status to see if link is active */
823 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
825 if (link_status & PCI_EXP_LNKSTA_NLW)
826 link_is_active = true;
828 if (!link_is_active) {
829 /* try GEN 1 link speed */
830 #define PCI_TARGET_LINK_SPEED_MASK 0xf
831 #define PCI_TARGET_LINK_SPEED_GEN2 0x2
832 #define PCI_TARGET_LINK_SPEED_GEN1 0x1
833 iproc_pci_raw_config_read32(pcie, 0,
834 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
836 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
837 PCI_TARGET_LINK_SPEED_GEN2) {
838 link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
839 link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
840 iproc_pci_raw_config_write32(pcie, 0,
841 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
845 iproc_pci_raw_config_read32(pcie, 0,
846 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
848 if (link_status & PCI_EXP_LNKSTA_NLW)
849 link_is_active = true;
853 dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
855 return link_is_active ? 0 : -ENODEV;
858 static void iproc_pcie_enable(struct iproc_pcie *pcie)
860 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
863 static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
868 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
870 return !!(val & OARR_VALID);
873 static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
874 int size_idx, u64 axi_addr, u64 pci_addr)
876 struct device *dev = pcie->dev;
877 u16 oarr_offset, omap_offset;
880 * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based
883 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
885 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
887 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
888 iproc_pcie_reg_is_invalid(omap_offset))
892 * Program the OARR registers. The upper 32-bit OARR register is
893 * always right after the lower 32-bit OARR register.
895 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
896 OARR_VALID, pcie->base + oarr_offset);
897 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
899 /* now program the OMAP registers */
900 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
901 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
903 dev_dbg(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
904 window_idx, oarr_offset, &axi_addr, &pci_addr);
905 dev_dbg(dev, "oarr lo 0x%x oarr hi 0x%x\n",
906 readl(pcie->base + oarr_offset),
907 readl(pcie->base + oarr_offset + 4));
908 dev_dbg(dev, "omap lo 0x%x omap hi 0x%x\n",
909 readl(pcie->base + omap_offset),
910 readl(pcie->base + omap_offset + 4));
916 * Some iProc SoCs require the SW to configure the outbound address mapping
918 * Outbound address translation:
920 * iproc_pcie_address = axi_address - axi_offset
921 * OARR = iproc_pcie_address
924 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
926 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
927 u64 pci_addr, resource_size_t size)
929 struct iproc_pcie_ob *ob = &pcie->ob;
930 struct device *dev = pcie->dev;
931 int ret = -EINVAL, window_idx, size_idx;
933 if (axi_addr < ob->axi_offset) {
934 dev_err(dev, "axi address %pap less than offset %pap\n",
935 &axi_addr, &ob->axi_offset);
940 * Translate the AXI address to the internal address used by the iProc
941 * PCIe core before programming the OARR
943 axi_addr -= ob->axi_offset;
945 /* iterate through all OARR/OMAP mapping windows */
946 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
947 const struct iproc_pcie_ob_map *ob_map =
948 &pcie->ob_map[window_idx];
951 * If current outbound window is already in use, move on to the
954 if (iproc_pcie_ob_is_valid(pcie, window_idx))
958 * Iterate through all supported window sizes within the
959 * OARR/OMAP pair to find a match. Go through the window sizes
960 * in a descending order.
962 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
964 resource_size_t window_size =
965 ob_map->window_sizes[size_idx] * SZ_1M;
968 * Keep iterating until we reach the last window and
969 * with the minimal window size at index zero. In this
970 * case, we take a compromise by mapping it using the
971 * minimum window size that can be supported
973 if (size < window_size) {
974 if (size_idx > 0 || window_idx > 0)
978 * For the corner case of reaching the minimal
979 * window size that can be supported on the
982 axi_addr = ALIGN_DOWN(axi_addr, window_size);
983 pci_addr = ALIGN_DOWN(pci_addr, window_size);
987 if (!IS_ALIGNED(axi_addr, window_size) ||
988 !IS_ALIGNED(pci_addr, window_size)) {
990 "axi %pap or pci %pap not aligned\n",
991 &axi_addr, &pci_addr);
996 * Match found! Program both OARR and OMAP and mark
997 * them as a valid entry.
999 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
1000 axi_addr, pci_addr);
1004 size -= window_size;
1009 * If we are here, we are done with the current window,
1010 * but not yet finished all mappings. Need to move on
1011 * to the next window.
1013 axi_addr += window_size;
1014 pci_addr += window_size;
1020 dev_err(dev, "unable to configure outbound mapping\n");
1022 "axi %pap, axi offset %pap, pci %pap, res size %pap\n",
1023 &axi_addr, &ob->axi_offset, &pci_addr, &size);
1028 static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
1029 struct list_head *resources)
1031 struct device *dev = pcie->dev;
1032 struct resource_entry *window;
1035 resource_list_for_each_entry(window, resources) {
1036 struct resource *res = window->res;
1037 u64 res_type = resource_type(res);
1041 case IORESOURCE_BUS:
1043 case IORESOURCE_MEM:
1044 ret = iproc_pcie_setup_ob(pcie, res->start,
1045 res->start - window->offset,
1046 resource_size(res));
1051 dev_err(dev, "invalid resource %pR\n", res);
1059 static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
1062 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
1065 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
1067 return !!(val & (BIT(ib_map->nr_sizes) - 1));
1070 static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
1071 enum iproc_pcie_ib_map_type type)
1073 return !!(ib_map->type == type);
1076 static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
1077 int size_idx, int nr_windows, u64 axi_addr,
1078 u64 pci_addr, resource_size_t size)
1080 struct device *dev = pcie->dev;
1081 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
1082 u16 iarr_offset, imap_offset;
1086 iarr_offset = iproc_pcie_reg_offset(pcie,
1087 MAP_REG(IPROC_PCIE_IARR0, region_idx));
1088 imap_offset = iproc_pcie_reg_offset(pcie,
1089 MAP_REG(IPROC_PCIE_IMAP0, region_idx));
1090 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
1091 iproc_pcie_reg_is_invalid(imap_offset))
1094 dev_dbg(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
1095 region_idx, iarr_offset, &axi_addr, &pci_addr);
1098 * Program the IARR registers. The upper 32-bit IARR register is
1099 * always right after the lower 32-bit IARR register.
1101 writel(lower_32_bits(pci_addr) | BIT(size_idx),
1102 pcie->base + iarr_offset);
1103 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
1105 dev_dbg(dev, "iarr lo 0x%x iarr hi 0x%x\n",
1106 readl(pcie->base + iarr_offset),
1107 readl(pcie->base + iarr_offset + 4));
1110 * Now program the IMAP registers. Each IARR region may have one or
1111 * more IMAP windows.
1113 size >>= ilog2(nr_windows);
1114 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
1115 val = readl(pcie->base + imap_offset);
1116 val |= lower_32_bits(axi_addr) | IMAP_VALID;
1117 writel(val, pcie->base + imap_offset);
1118 writel(upper_32_bits(axi_addr),
1119 pcie->base + imap_offset + ib_map->imap_addr_offset);
1121 dev_dbg(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
1122 window_idx, readl(pcie->base + imap_offset),
1123 readl(pcie->base + imap_offset +
1124 ib_map->imap_addr_offset));
1126 imap_offset += ib_map->imap_window_offset;
1133 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
1134 struct resource_entry *entry,
1135 enum iproc_pcie_ib_map_type type)
1137 struct device *dev = pcie->dev;
1138 struct iproc_pcie_ib *ib = &pcie->ib;
1140 unsigned int region_idx, size_idx;
1141 u64 axi_addr = entry->res->start;
1142 u64 pci_addr = entry->res->start - entry->offset;
1143 resource_size_t size = resource_size(entry->res);
1145 /* iterate through all IARR mapping regions */
1146 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
1147 const struct iproc_pcie_ib_map *ib_map =
1148 &pcie->ib_map[region_idx];
1151 * If current inbound region is already in use or not a
1152 * compatible type, move on to the next.
1154 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
1155 !iproc_pcie_ib_check_type(ib_map, type))
1158 /* iterate through all supported region sizes to find a match */
1159 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
1160 resource_size_t region_size =
1161 ib_map->region_sizes[size_idx] * ib_map->size_unit;
1163 if (size != region_size)
1166 if (!IS_ALIGNED(axi_addr, region_size) ||
1167 !IS_ALIGNED(pci_addr, region_size)) {
1169 "axi %pap or pci %pap not aligned\n",
1170 &axi_addr, &pci_addr);
1174 /* Match found! Program IARR and all IMAP windows. */
1175 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
1176 ib_map->nr_windows, axi_addr,
1188 dev_err(dev, "unable to configure inbound mapping\n");
1189 dev_err(dev, "axi %pap, pci %pap, res size %pap\n",
1190 &axi_addr, &pci_addr, &size);
1195 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1197 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1198 struct resource_entry *entry;
1201 resource_list_for_each_entry(entry, &host->dma_ranges) {
1202 /* Each range entry corresponds to an inbound mapping region */
1203 ret = iproc_pcie_setup_ib(pcie, entry, IPROC_PCIE_IB_MAP_MEM);
1211 static void iproc_pcie_invalidate_mapping(struct iproc_pcie *pcie)
1213 struct iproc_pcie_ib *ib = &pcie->ib;
1214 struct iproc_pcie_ob *ob = &pcie->ob;
1217 if (pcie->ep_is_internal)
1220 if (pcie->need_ob_cfg) {
1221 /* iterate through all OARR mapping regions */
1222 for (idx = ob->nr_windows - 1; idx >= 0; idx--) {
1223 iproc_pcie_write_reg(pcie,
1224 MAP_REG(IPROC_PCIE_OARR0, idx), 0);
1228 if (pcie->need_ib_cfg) {
1229 /* iterate through all IARR mapping regions */
1230 for (idx = 0; idx < ib->nr_regions; idx++) {
1231 iproc_pcie_write_reg(pcie,
1232 MAP_REG(IPROC_PCIE_IARR0, idx), 0);
1237 static int iproce_pcie_get_msi(struct iproc_pcie *pcie,
1238 struct device_node *msi_node,
1241 struct device *dev = pcie->dev;
1243 struct resource res;
1246 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only
1247 * supported external MSI controller that requires steering.
1249 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) {
1250 dev_err(dev, "unable to find compatible MSI controller\n");
1254 /* derive GITS_TRANSLATER address from GICv3 */
1255 ret = of_address_to_resource(msi_node, 0, &res);
1257 dev_err(dev, "unable to obtain MSI controller resources\n");
1261 *msi_addr = res.start + GITS_TRANSLATER;
1265 static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1268 struct resource_entry entry;
1270 memset(&entry, 0, sizeof(entry));
1271 entry.res = &entry.__res;
1273 msi_addr &= ~(SZ_32K - 1);
1274 entry.res->start = msi_addr;
1275 entry.res->end = msi_addr + SZ_32K - 1;
1277 ret = iproc_pcie_setup_ib(pcie, &entry, IPROC_PCIE_IB_MAP_IO);
1281 static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr,
1288 * Disable PAXC MSI steering. All write transfers will be
1289 * treated as non-MSI transfers
1291 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
1292 val &= ~MSI_ENABLE_CFG;
1293 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
1298 * Program bits [43:13] of address of GITS_TRANSLATER register into
1299 * bits [30:0] of the MSI base address register. In fact, in all iProc
1300 * based SoCs, all I/O register bases are well below the 32-bit
1301 * boundary, so we can safely assume bits [43:32] are always zeros.
1303 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR,
1304 (u32)(msi_addr >> 13));
1306 /* use a default 8K window size */
1307 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0);
1309 /* steering MSI to GICv3 ITS */
1310 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE);
1312 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val);
1315 * Program bits [43:2] of address of GITS_TRANSLATER register into the
1316 * iProc MSI address registers.
1319 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI,
1320 upper_32_bits(msi_addr));
1321 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO,
1322 lower_32_bits(msi_addr));
1325 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
1326 val |= MSI_ENABLE_CFG;
1327 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
1330 static int iproc_pcie_msi_steer(struct iproc_pcie *pcie,
1331 struct device_node *msi_node)
1333 struct device *dev = pcie->dev;
1337 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr);
1339 dev_err(dev, "msi steering failed\n");
1343 switch (pcie->type) {
1344 case IPROC_PCIE_PAXB_V2:
1345 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr);
1349 case IPROC_PCIE_PAXC_V2:
1350 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr, true);
1359 static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
1361 struct device_node *msi_node;
1365 * Either the "msi-parent" or the "msi-map" phandle needs to exist
1366 * for us to obtain the MSI node.
1369 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
1371 const __be32 *msi_map = NULL;
1375 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len);
1379 phandle = be32_to_cpup(msi_map + 1);
1380 msi_node = of_find_node_by_phandle(phandle);
1386 * Certain revisions of the iProc PCIe controller require additional
1387 * configurations to steer the MSI writes towards an external MSI
1390 if (pcie->need_msi_steer) {
1391 ret = iproc_pcie_msi_steer(pcie, msi_node);
1397 * If another MSI controller is being used, the call below should fail
1400 ret = iproc_msi_init(pcie, msi_node);
1403 of_node_put(msi_node);
1407 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
1409 iproc_msi_exit(pcie);
1412 static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
1414 struct device *dev = pcie->dev;
1415 unsigned int reg_idx;
1418 switch (pcie->type) {
1419 case IPROC_PCIE_PAXB_BCMA:
1420 regs = iproc_pcie_reg_paxb_bcma;
1422 case IPROC_PCIE_PAXB:
1423 regs = iproc_pcie_reg_paxb;
1424 pcie->has_apb_err_disable = true;
1425 if (pcie->need_ob_cfg) {
1426 pcie->ob_map = paxb_ob_map;
1427 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map);
1430 case IPROC_PCIE_PAXB_V2:
1431 regs = iproc_pcie_reg_paxb_v2;
1432 pcie->iproc_cfg_read = true;
1433 pcie->has_apb_err_disable = true;
1434 if (pcie->need_ob_cfg) {
1435 pcie->ob_map = paxb_v2_ob_map;
1436 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
1438 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
1439 pcie->ib_map = paxb_v2_ib_map;
1440 pcie->need_msi_steer = true;
1441 dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n",
1444 case IPROC_PCIE_PAXC:
1445 regs = iproc_pcie_reg_paxc;
1446 pcie->ep_is_internal = true;
1447 pcie->iproc_cfg_read = true;
1448 pcie->rej_unconfig_pf = true;
1450 case IPROC_PCIE_PAXC_V2:
1451 regs = iproc_pcie_reg_paxc_v2;
1452 pcie->ep_is_internal = true;
1453 pcie->iproc_cfg_read = true;
1454 pcie->rej_unconfig_pf = true;
1455 pcie->need_msi_steer = true;
1458 dev_err(dev, "incompatible iProc PCIe interface\n");
1462 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG,
1463 sizeof(*pcie->reg_offsets),
1465 if (!pcie->reg_offsets)
1468 /* go through the register table and populate all valid registers */
1469 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
1470 IPROC_PCIE_REG_INVALID : regs[0];
1471 for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++)
1472 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
1473 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
1478 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
1482 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1486 ret = iproc_pcie_rev_init(pcie);
1488 dev_err(dev, "unable to initialize controller parameters\n");
1492 ret = phy_init(pcie->phy);
1494 dev_err(dev, "unable to initialize PCIe PHY\n");
1498 ret = phy_power_on(pcie->phy);
1500 dev_err(dev, "unable to power on PCIe PHY\n");
1504 iproc_pcie_perst_ctrl(pcie, true);
1505 iproc_pcie_perst_ctrl(pcie, false);
1507 iproc_pcie_invalidate_mapping(pcie);
1509 if (pcie->need_ob_cfg) {
1510 ret = iproc_pcie_map_ranges(pcie, res);
1512 dev_err(dev, "map failed\n");
1513 goto err_power_off_phy;
1517 if (pcie->need_ib_cfg) {
1518 ret = iproc_pcie_map_dma_ranges(pcie);
1519 if (ret && ret != -ENOENT)
1520 goto err_power_off_phy;
1523 ret = iproc_pcie_check_link(pcie);
1525 dev_err(dev, "no PCIe EP device detected\n");
1526 goto err_power_off_phy;
1529 iproc_pcie_enable(pcie);
1531 if (IS_ENABLED(CONFIG_PCI_MSI))
1532 if (iproc_pcie_msi_enable(pcie))
1533 dev_info(dev, "not using iProc MSI\n");
1535 host->ops = &iproc_pcie_ops;
1536 host->sysdata = pcie;
1537 host->map_irq = pcie->map_irq;
1539 ret = pci_host_probe(host);
1541 dev_err(dev, "failed to scan host: %d\n", ret);
1542 goto err_power_off_phy;
1548 phy_power_off(pcie->phy);
1550 phy_exit(pcie->phy);
1553 EXPORT_SYMBOL(iproc_pcie_setup);
1555 int iproc_pcie_remove(struct iproc_pcie *pcie)
1557 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1559 pci_stop_root_bus(host->bus);
1560 pci_remove_root_bus(host->bus);
1562 iproc_pcie_msi_disable(pcie);
1564 phy_power_off(pcie->phy);
1565 phy_exit(pcie->phy);
1569 EXPORT_SYMBOL(iproc_pcie_remove);
1572 * The MSI parsing logic in certain revisions of Broadcom PAXC based root
1573 * complex does not work and needs to be disabled
1575 static void quirk_paxc_disable_msi_parsing(struct pci_dev *pdev)
1577 struct iproc_pcie *pcie = iproc_data(pdev->bus);
1579 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
1580 iproc_pcie_paxc_v2_msi_steer(pcie, 0, false);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0,
1583 quirk_paxc_disable_msi_parsing);
1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802,
1585 quirk_paxc_disable_msi_parsing);
1586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,
1587 quirk_paxc_disable_msi_parsing);
1589 static void quirk_paxc_bridge(struct pci_dev *pdev)
1592 * The PCI config space is shared with the PAXC root port and the first
1593 * Ethernet device. So, we need to workaround this by telling the PCI
1594 * code that the bridge is not an Ethernet device.
1596 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
1597 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
1600 * MPSS is not being set properly (as it is currently 0). This is
1601 * because that area of the PCI config space is hard coded to zero, and
1602 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
1603 * so that the MPS can be set to the real max value.
1605 pdev->pcie_mpss = 2;
1607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
1608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
1609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
1610 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
1611 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
1613 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1614 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
1615 MODULE_LICENSE("GPL v2");