1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
5 * Author: Ley Foon Tan <lftan@altera.com>
6 * Description: Altera PCIe host controller driver
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
23 #define RP_TX_REG0 0x2000
24 #define RP_TX_REG1 0x2004
25 #define RP_TX_CNTRL 0x2008
28 #define RP_RXCPL_STATUS 0x2010
29 #define RP_RXCPL_EOP 0x2
30 #define RP_RXCPL_SOP 0x1
31 #define RP_RXCPL_REG0 0x2014
32 #define RP_RXCPL_REG1 0x2018
33 #define P2A_INT_STATUS 0x3060
34 #define P2A_INT_STS_ALL 0xf
35 #define P2A_INT_ENABLE 0x3070
36 #define P2A_INT_ENA_ALL 0xf
37 #define RP_LTSSM 0x3c64
38 #define RP_LTSSM_MASK 0x1f
41 #define S10_RP_TX_CNTRL 0x2004
42 #define S10_RP_RXCPL_REG 0x2008
43 #define S10_RP_RXCPL_STATUS 0x200C
44 #define S10_RP_CFG_ADDR(pcie, reg) \
45 (((pcie)->hip_base) + (reg) + (1 << 20))
46 #define S10_RP_SECONDARY(pcie) \
47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
49 /* TLP configuration type 0 and 1 */
50 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
51 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
52 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
53 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
54 #define TLP_PAYLOAD_SIZE 0x01
55 #define TLP_READ_TAG 0x1d
56 #define TLP_WRITE_TAG 0x10
58 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
59 #define TLP_CFG_DW0(pcie, cfg) \
62 #define TLP_CFG_DW1(pcie, tag, be) \
63 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
64 #define TLP_CFG_DW2(bus, devfn, offset) \
65 (((bus) << 24) | ((devfn) << 16) | (offset))
66 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
67 #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
68 #define TLP_HDR_SIZE 3
71 #define LINK_UP_TIMEOUT HZ
72 #define LINK_RETRAIN_TIMEOUT HZ
76 #define S10_TLP_FMTTYPE_CFGRD0 0x05
77 #define S10_TLP_FMTTYPE_CFGRD1 0x04
78 #define S10_TLP_FMTTYPE_CFGWR0 0x45
79 #define S10_TLP_FMTTYPE_CFGWR1 0x44
81 enum altera_pcie_version {
87 struct platform_device *pdev;
88 void __iomem *cra_base;
89 void __iomem *hip_base;
92 struct irq_domain *irq_domain;
93 struct resource bus_range;
94 const struct altera_pcie_data *pcie_data;
97 struct altera_pcie_ops {
98 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
99 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
100 u32 data, bool align);
101 bool (*get_link_status)(struct altera_pcie *pcie);
102 int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
103 int size, u32 *value);
104 int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
105 int where, int size, u32 value);
108 struct altera_pcie_data {
109 const struct altera_pcie_ops *ops;
110 enum altera_pcie_version version;
111 u32 cap_offset; /* PCIe capability structure register offset */
118 struct tlp_rp_regpair_t {
124 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
127 writel_relaxed(value, pcie->cra_base + reg);
130 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
132 return readl_relaxed(pcie->cra_base + reg);
135 static bool altera_pcie_link_up(struct altera_pcie *pcie)
137 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
140 static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
142 void __iomem *addr = S10_RP_CFG_ADDR(pcie,
143 pcie->pcie_data->cap_offset +
146 return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
150 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
151 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
152 * using these registers, so it can be reached by DMA from EP devices.
153 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
154 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
155 * should be hidden during enumeration to avoid the sizing and resource
156 * allocation by PCIe core.
158 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
161 if (pci_is_root_bus(bus) && (devfn == 0) &&
162 (offset == PCI_BASE_ADDRESS_0))
168 static void tlp_write_tx(struct altera_pcie *pcie,
169 struct tlp_rp_regpair_t *tlp_rp_regdata)
171 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
172 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
173 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
176 static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)
178 cra_writel(pcie, reg0, RP_TX_REG0);
179 cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);
182 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
183 struct pci_bus *bus, int dev)
185 /* If there is no link, then there is no device */
186 if (bus->number != pcie->root_bus_nr) {
187 if (!pcie->pcie_data->ops->get_link_status(pcie))
191 /* access only one slot on each root port */
192 if (bus->number == pcie->root_bus_nr && dev > 0)
198 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
207 * Minimum 2 loops to read TLP headers and 1 loop to read data
210 for (i = 0; i < TLP_LOOP; i++) {
211 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
212 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
213 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
214 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
216 if (ctrl & RP_RXCPL_SOP) {
218 comp_status = TLP_COMP_STATUS(reg1);
221 if (ctrl & RP_RXCPL_EOP) {
223 return PCIBIOS_DEVICE_NOT_FOUND;
228 return PCIBIOS_SUCCESSFUL;
234 return PCIBIOS_DEVICE_NOT_FOUND;
237 static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
243 struct device *dev = &pcie->pdev->dev;
245 for (count = 0; count < TLP_LOOP; count++) {
246 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
247 if (ctrl & RP_RXCPL_SOP) {
249 dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
256 /* SOP detection failed, return error */
257 if (count == TLP_LOOP)
258 return PCIBIOS_DEVICE_NOT_FOUND;
263 while (count < ARRAY_SIZE(dw)) {
264 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
265 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);
266 if (ctrl & RP_RXCPL_EOP) {
267 comp_status = TLP_COMP_STATUS(dw[1]);
269 return PCIBIOS_DEVICE_NOT_FOUND;
271 if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
275 return PCIBIOS_SUCCESSFUL;
279 dev_warn(dev, "Malformed TLP packet\n");
281 return PCIBIOS_DEVICE_NOT_FOUND;
284 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
285 u32 data, bool align)
287 struct tlp_rp_regpair_t tlp_rp_regdata;
289 tlp_rp_regdata.reg0 = headers[0];
290 tlp_rp_regdata.reg1 = headers[1];
291 tlp_rp_regdata.ctrl = RP_TX_SOP;
292 tlp_write_tx(pcie, &tlp_rp_regdata);
295 tlp_rp_regdata.reg0 = headers[2];
296 tlp_rp_regdata.reg1 = 0;
297 tlp_rp_regdata.ctrl = 0;
298 tlp_write_tx(pcie, &tlp_rp_regdata);
300 tlp_rp_regdata.reg0 = data;
301 tlp_rp_regdata.reg1 = 0;
303 tlp_rp_regdata.reg0 = headers[2];
304 tlp_rp_regdata.reg1 = data;
307 tlp_rp_regdata.ctrl = RP_TX_EOP;
308 tlp_write_tx(pcie, &tlp_rp_regdata);
311 static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
312 u32 data, bool dummy)
314 s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
315 s10_tlp_write_tx(pcie, headers[1], 0);
316 s10_tlp_write_tx(pcie, headers[2], 0);
317 s10_tlp_write_tx(pcie, data, RP_TX_EOP);
320 static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
321 int where, u8 byte_en, bool read, u32 *headers)
324 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
325 u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
326 u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
328 if (pcie->pcie_data->version == ALTERA_PCIE_V1)
329 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
331 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
333 headers[0] = TLP_CFG_DW0(pcie, cfg);
334 headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
335 headers[2] = TLP_CFG_DW2(bus, devfn, where);
338 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
339 int where, u8 byte_en, u32 *value)
341 u32 headers[TLP_HDR_SIZE];
343 get_tlp_header(pcie, bus, devfn, where, byte_en, true,
346 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
348 return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
351 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
352 int where, u8 byte_en, u32 value)
354 u32 headers[TLP_HDR_SIZE];
357 get_tlp_header(pcie, bus, devfn, where, byte_en, false,
360 /* check alignment to Qword */
361 if ((where & 0x7) == 0)
362 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
365 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
368 ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
369 if (ret != PCIBIOS_SUCCESSFUL)
373 * Monitor changes to PCI_PRIMARY_BUS register on root port
374 * and update local copy of root bus number accordingly.
376 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
377 pcie->root_bus_nr = (u8)(value);
379 return PCIBIOS_SUCCESSFUL;
382 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,
383 int size, u32 *value)
385 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
389 *value = readb(addr);
392 *value = readw(addr);
395 *value = readl(addr);
399 return PCIBIOS_SUCCESSFUL;
402 static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
403 int where, int size, u32 value)
405 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
420 * Monitor changes to PCI_PRIMARY_BUS register on root port
421 * and update local copy of root bus number accordingly.
423 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
424 pcie->root_bus_nr = value & 0xff;
426 return PCIBIOS_SUCCESSFUL;
429 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
430 unsigned int devfn, int where, int size,
437 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
438 return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
443 byte_en = 1 << (where & 3);
446 byte_en = 3 << (where & 3);
453 ret = tlp_cfg_dword_read(pcie, busno, devfn,
454 (where & ~DWORD_MASK), byte_en, &data);
455 if (ret != PCIBIOS_SUCCESSFUL)
460 *value = (data >> (8 * (where & 0x3))) & 0xff;
463 *value = (data >> (8 * (where & 0x2))) & 0xffff;
470 return PCIBIOS_SUCCESSFUL;
473 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
474 unsigned int devfn, int where, int size,
478 u32 shift = 8 * (where & 3);
481 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
482 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
487 data32 = (value & 0xff) << shift;
488 byte_en = 1 << (where & 3);
491 data32 = (value & 0xffff) << shift;
492 byte_en = 3 << (where & 3);
500 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
504 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
505 int where, int size, u32 *value)
507 struct altera_pcie *pcie = bus->sysdata;
509 if (altera_pcie_hide_rc_bar(bus, devfn, where))
510 return PCIBIOS_BAD_REGISTER_NUMBER;
512 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
513 return PCIBIOS_DEVICE_NOT_FOUND;
515 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
519 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
520 int where, int size, u32 value)
522 struct altera_pcie *pcie = bus->sysdata;
524 if (altera_pcie_hide_rc_bar(bus, devfn, where))
525 return PCIBIOS_BAD_REGISTER_NUMBER;
527 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
528 return PCIBIOS_DEVICE_NOT_FOUND;
530 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
534 static struct pci_ops altera_pcie_ops = {
535 .read = altera_pcie_cfg_read,
536 .write = altera_pcie_cfg_write,
539 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
540 unsigned int devfn, int offset, u16 *value)
545 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
546 pcie->pcie_data->cap_offset + offset,
553 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
554 unsigned int devfn, int offset, u16 value)
556 return _altera_pcie_cfg_write(pcie, busno, devfn,
557 pcie->pcie_data->cap_offset + offset,
562 static void altera_wait_link_retrain(struct altera_pcie *pcie)
564 struct device *dev = &pcie->pdev->dev;
566 unsigned long start_jiffies;
568 /* Wait for link training end. */
569 start_jiffies = jiffies;
571 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
572 PCI_EXP_LNKSTA, ®16);
573 if (!(reg16 & PCI_EXP_LNKSTA_LT))
576 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
577 dev_err(dev, "link retrain timeout\n");
583 /* Wait for link is up */
584 start_jiffies = jiffies;
586 if (pcie->pcie_data->ops->get_link_status(pcie))
589 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
590 dev_err(dev, "link up timeout\n");
597 static void altera_pcie_retrain(struct altera_pcie *pcie)
599 u16 linkcap, linkstat, linkctl;
601 if (!pcie->pcie_data->ops->get_link_status(pcie))
605 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
606 * current speed is 2.5 GB/s.
608 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
610 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
613 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
615 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
616 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
617 PCI_EXP_LNKCTL, &linkctl);
618 linkctl |= PCI_EXP_LNKCTL_RL;
619 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
620 PCI_EXP_LNKCTL, linkctl);
622 altera_wait_link_retrain(pcie);
626 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
627 irq_hw_number_t hwirq)
629 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
630 irq_set_chip_data(irq, domain->host_data);
634 static const struct irq_domain_ops intx_domain_ops = {
635 .map = altera_pcie_intx_map,
636 .xlate = pci_irqd_intx_xlate,
639 static void altera_pcie_isr(struct irq_desc *desc)
641 struct irq_chip *chip = irq_desc_get_chip(desc);
642 struct altera_pcie *pcie;
644 unsigned long status;
648 chained_irq_enter(chip, desc);
649 pcie = irq_desc_get_handler_data(desc);
650 dev = &pcie->pdev->dev;
652 while ((status = cra_readl(pcie, P2A_INT_STATUS)
653 & P2A_INT_STS_ALL) != 0) {
654 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
655 /* clear interrupts */
656 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
658 ret = generic_handle_domain_irq(pcie->irq_domain, bit);
660 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);
664 chained_irq_exit(chip, desc);
667 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
669 struct device *dev = &pcie->pdev->dev;
670 struct device_node *node = dev->of_node;
673 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
674 &intx_domain_ops, pcie);
675 if (!pcie->irq_domain) {
676 dev_err(dev, "Failed to get a INTx IRQ domain\n");
683 static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
685 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
686 irq_domain_remove(pcie->irq_domain);
687 irq_dispose_mapping(pcie->irq);
690 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
692 struct platform_device *pdev = pcie->pdev;
694 pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
695 if (IS_ERR(pcie->cra_base))
696 return PTR_ERR(pcie->cra_base);
698 if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
700 devm_platform_ioremap_resource_byname(pdev, "Hip");
701 if (IS_ERR(pcie->hip_base))
702 return PTR_ERR(pcie->hip_base);
706 pcie->irq = platform_get_irq(pdev, 0);
710 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
714 static void altera_pcie_host_init(struct altera_pcie *pcie)
716 altera_pcie_retrain(pcie);
719 static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
720 .tlp_read_pkt = tlp_read_packet,
721 .tlp_write_pkt = tlp_write_packet,
722 .get_link_status = altera_pcie_link_up,
725 static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
726 .tlp_read_pkt = s10_tlp_read_packet,
727 .tlp_write_pkt = s10_tlp_write_packet,
728 .get_link_status = s10_altera_pcie_link_up,
729 .rp_read_cfg = s10_rp_read_cfg,
730 .rp_write_cfg = s10_rp_write_cfg,
733 static const struct altera_pcie_data altera_pcie_1_0_data = {
734 .ops = &altera_pcie_ops_1_0,
736 .version = ALTERA_PCIE_V1,
737 .cfgrd0 = TLP_FMTTYPE_CFGRD0,
738 .cfgrd1 = TLP_FMTTYPE_CFGRD1,
739 .cfgwr0 = TLP_FMTTYPE_CFGWR0,
740 .cfgwr1 = TLP_FMTTYPE_CFGWR1,
743 static const struct altera_pcie_data altera_pcie_2_0_data = {
744 .ops = &altera_pcie_ops_2_0,
745 .version = ALTERA_PCIE_V2,
747 .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
748 .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
749 .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
750 .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
753 static const struct of_device_id altera_pcie_of_match[] = {
754 {.compatible = "altr,pcie-root-port-1.0",
755 .data = &altera_pcie_1_0_data },
756 {.compatible = "altr,pcie-root-port-2.0",
757 .data = &altera_pcie_2_0_data },
761 static int altera_pcie_probe(struct platform_device *pdev)
763 struct device *dev = &pdev->dev;
764 struct altera_pcie *pcie;
765 struct pci_host_bridge *bridge;
767 const struct altera_pcie_data *data;
769 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
773 pcie = pci_host_bridge_priv(bridge);
775 platform_set_drvdata(pdev, pcie);
777 data = of_device_get_match_data(&pdev->dev);
781 pcie->pcie_data = data;
783 ret = altera_pcie_parse_dt(pcie);
785 dev_err(dev, "Parsing DT failed\n");
789 ret = altera_pcie_init_irq_domain(pcie);
791 dev_err(dev, "Failed creating IRQ Domain\n");
795 /* clear all interrupts */
796 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
797 /* enable all interrupts */
798 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
799 altera_pcie_host_init(pcie);
801 bridge->sysdata = pcie;
802 bridge->busnr = pcie->root_bus_nr;
803 bridge->ops = &altera_pcie_ops;
805 return pci_host_probe(bridge);
808 static void altera_pcie_remove(struct platform_device *pdev)
810 struct altera_pcie *pcie = platform_get_drvdata(pdev);
811 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
813 pci_stop_root_bus(bridge->bus);
814 pci_remove_root_bus(bridge->bus);
815 altera_pcie_irq_teardown(pcie);
818 static struct platform_driver altera_pcie_driver = {
819 .probe = altera_pcie_probe,
820 .remove_new = altera_pcie_remove,
822 .name = "altera-pcie",
823 .of_match_table = altera_pcie_of_match,
827 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
828 module_platform_driver(altera_pcie_driver);
829 MODULE_LICENSE("GPL v2");