1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 - 2016 Cavium, Inc.
6 #include <linux/bitfield.h>
7 #include <linux/kernel.h>
8 #include <linux/init.h>
10 #include <linux/of_address.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
14 #include <linux/platform_device.h>
15 #include <linux/io-64-nonatomic-lo-hi.h>
18 #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
20 #define PEM_CFG_WR 0x28
21 #define PEM_CFG_RD 0x30
23 struct thunder_pem_pci {
25 void __iomem *pem_reg_base;
28 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
29 int where, int size, u32 *val)
31 u64 read_val, tmp_val;
32 struct pci_config_window *cfg = bus->sysdata;
33 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
35 if (devfn != 0 || where >= 2048) {
37 return PCIBIOS_DEVICE_NOT_FOUND;
41 * 32-bit accesses only. Write the address to the low order
42 * bits of PEM_CFG_RD, then trigger the read by reading back.
43 * The config data lands in the upper 32-bits of PEM_CFG_RD.
45 read_val = where & ~3ull;
46 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
47 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
51 * The config space contains some garbage, fix it up. Also
52 * synthesize an EA capability for the BAR used by MSI-X.
56 read_val &= 0xffff00ff;
57 read_val |= 0x00007000; /* Skip MSI CAP */
59 case 0x70: /* Express Cap */
61 * Change PME interrupt to vector 2 on T88 where it
62 * reads as 0, else leave it alone.
64 if (!(read_val & (0x1f << 25)))
65 read_val |= (2u << 25);
67 case 0xb0: /* MSI-X Cap */
68 /* TableSize=2 or 4, Next Cap is EA */
69 read_val &= 0xc00000ff;
71 * If Express Cap(0x70) raw PME vector reads as 0 we are on
72 * T88 and TableSize is reported as 4, else TableSize
75 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
76 tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
78 if (!(tmp_val & (0x1f << 25)))
79 read_val |= 0x0003bc00;
81 read_val |= 0x0001bc00;
84 /* Table offset=0, BIR=0 */
85 read_val = 0x00000000;
88 /* BPA offset=0xf0000, BIR=0 */
89 read_val = 0x000f0000;
92 /* EA, 1 entry, no next Cap */
93 read_val = 0x00010014;
97 read_val = 0x00000000;
100 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
101 read_val = 0x80ff0003;
104 read_val = pem_pci->ea_entry[0];
107 read_val = pem_pci->ea_entry[1];
110 read_val = pem_pci->ea_entry[2];
115 read_val >>= (8 * (where & 3));
127 return PCIBIOS_SUCCESSFUL;
130 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
131 int where, int size, u32 *val)
133 struct pci_config_window *cfg = bus->sysdata;
135 if (bus->number < cfg->busr.start ||
136 bus->number > cfg->busr.end)
137 return PCIBIOS_DEVICE_NOT_FOUND;
140 * The first device on the bus is the PEM PCIe bridge.
141 * Special case its config access.
143 if (bus->number == cfg->busr.start)
144 return thunder_pem_bridge_read(bus, devfn, where, size, val);
146 return pci_generic_config_read(bus, devfn, where, size, val);
150 * Some of the w1c_bits below also include read-only or non-writable
151 * reserved bits, this makes the code simpler and is OK as the bits
152 * are not affected by writing zeros to them.
154 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
158 switch (where_aligned) {
159 case 0x04: /* Command/Status */
160 case 0x1c: /* Base and I/O Limit/Secondary Status */
161 w1c_bits = 0xff000000;
163 case 0x44: /* Power Management Control and Status */
164 w1c_bits = 0xfffffe00;
166 case 0x78: /* Device Control/Device Status */
167 case 0x80: /* Link Control/Link Status */
168 case 0x88: /* Slot Control/Slot Status */
169 case 0x90: /* Root Status */
170 case 0xa0: /* Link Control 2 Registers/Link Status 2 */
171 w1c_bits = 0xffff0000;
173 case 0x104: /* Uncorrectable Error Status */
174 case 0x110: /* Correctable Error Status */
175 case 0x130: /* Error Status */
176 case 0x160: /* Link Control 4 */
177 w1c_bits = 0xffffffff;
185 /* Some bits must be written to one so they appear to be read-only. */
186 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
190 switch (where_aligned) {
191 case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
192 /* Force 32-bit I/O addressing. */
195 case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
196 /* Force 64-bit addressing */
197 w1_bits = 0x00010001;
206 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
207 int where, int size, u32 val)
209 struct pci_config_window *cfg = bus->sysdata;
210 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
211 u64 write_val, read_val;
212 u64 where_aligned = where & ~3ull;
216 if (devfn != 0 || where >= 2048)
217 return PCIBIOS_DEVICE_NOT_FOUND;
220 * 32-bit accesses only. If the write is for a size smaller
221 * than 32-bits, we must first read the 32-bit value and merge
222 * in the desired bits and then write the whole 32-bits back
227 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
228 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
230 mask = ~(0xff << (8 * (where & 3)));
232 val = (val & 0xff) << (8 * (where & 3));
233 val |= (u32)read_val;
236 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
237 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
239 mask = ~(0xffff << (8 * (where & 3)));
241 val = (val & 0xffff) << (8 * (where & 3));
242 val |= (u32)read_val;
249 * By expanding the write width to 32 bits, we may
250 * inadvertently hit some W1C bits that were not intended to
251 * be written. Calculate the mask that must be applied to the
252 * data to be written to avoid these cases.
255 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
264 * Some bits must be read-only with value of one. Since the
265 * access method allows these to be cleared if a zero is
266 * written, force them to one before writing.
268 val |= thunder_pem_bridge_w1_bits(where_aligned);
271 * Low order bits are the config address, the high order 32
272 * bits are the data to be written.
274 write_val = (((u64)val) << 32) | where_aligned;
275 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
276 return PCIBIOS_SUCCESSFUL;
279 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
280 int where, int size, u32 val)
282 struct pci_config_window *cfg = bus->sysdata;
284 if (bus->number < cfg->busr.start ||
285 bus->number > cfg->busr.end)
286 return PCIBIOS_DEVICE_NOT_FOUND;
288 * The first device on the bus is the PEM PCIe bridge.
289 * Special case its config access.
291 if (bus->number == cfg->busr.start)
292 return thunder_pem_bridge_write(bus, devfn, where, size, val);
295 return pci_generic_config_write(bus, devfn, where, size, val);
298 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
299 struct resource *res_pem)
301 struct thunder_pem_pci *pem_pci;
302 resource_size_t bar4_start;
304 pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
308 pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
309 if (!pem_pci->pem_reg_base)
313 * The MSI-X BAR for the PEM and AER interrupts is located at
314 * a fixed offset from the PEM register base. Generate a
315 * fragment of the synthesized Enhanced Allocation capability
316 * structure here for the BAR.
318 bar4_start = res_pem->start + 0xf00000;
319 pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
320 pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
321 pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
327 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
329 #define PEM_RES_BASE 0x87e0c0000000ULL
330 #define PEM_NODE_MASK GENMASK_ULL(45, 44)
331 #define PEM_INDX_MASK GENMASK_ULL(26, 24)
332 #define PEM_MIN_DOM_IN_NODE 4
333 #define PEM_MAX_DOM_IN_NODE 10
335 static void thunder_pem_reserve_range(struct device *dev, int seg,
338 resource_size_t start = r->start, end = r->end;
339 struct resource *res;
340 const char *regionid;
342 regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
346 res = request_mem_region(start, end - start + 1, regionid);
348 res->flags &= ~IORESOURCE_BUSY;
352 dev_info(dev, "%pR %s reserved\n", r,
353 res ? "has been" : "could not be");
356 static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
357 struct resource *res_pem)
359 int node = acpi_get_node(root->device->handle);
362 if (node == NUMA_NO_NODE)
365 index = root->segment - PEM_MIN_DOM_IN_NODE;
366 index -= node * PEM_MAX_DOM_IN_NODE;
367 res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
368 FIELD_PREP(PEM_INDX_MASK, index);
369 res_pem->flags = IORESOURCE_MEM;
372 static int thunder_pem_acpi_init(struct pci_config_window *cfg)
374 struct device *dev = cfg->parent;
375 struct acpi_device *adev = to_acpi_device(dev);
376 struct acpi_pci_root *root = acpi_driver_data(adev);
377 struct resource *res_pem;
380 res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
384 ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
387 * If we fail to gather resources it means that we run with old
388 * FW where we need to calculate PEM-specific resources manually.
391 thunder_pem_legacy_fw(root, res_pem);
393 * Reserve 64K size PEM specific resources. The full 16M range
394 * size is required for thunder_pem_init() call.
396 res_pem->end = res_pem->start + SZ_64K - 1;
397 thunder_pem_reserve_range(dev, root->segment, res_pem);
398 res_pem->end = res_pem->start + SZ_16M - 1;
400 /* Reserve PCI configuration space as well. */
401 thunder_pem_reserve_range(dev, root->segment, &cfg->res);
404 return thunder_pem_init(dev, cfg, res_pem);
407 const struct pci_ecam_ops thunder_pem_ecam_ops = {
409 .init = thunder_pem_acpi_init,
411 .map_bus = pci_ecam_map_bus,
412 .read = thunder_pem_config_read,
413 .write = thunder_pem_config_write,
419 #ifdef CONFIG_PCI_HOST_THUNDER_PEM
421 static int thunder_pem_platform_init(struct pci_config_window *cfg)
423 struct device *dev = cfg->parent;
424 struct platform_device *pdev = to_platform_device(dev);
425 struct resource *res_pem;
431 * The second register range is the PEM bridge to the PCIe
432 * bus. It has a different config access method than those
433 * devices behind the bridge.
435 res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
437 dev_err(dev, "missing \"reg[1]\"property\n");
441 return thunder_pem_init(dev, cfg, res_pem);
444 static const struct pci_ecam_ops pci_thunder_pem_ops = {
446 .init = thunder_pem_platform_init,
448 .map_bus = pci_ecam_map_bus,
449 .read = thunder_pem_config_read,
450 .write = thunder_pem_config_write,
454 static const struct of_device_id thunder_pem_of_match[] = {
456 .compatible = "cavium,pci-host-thunder-pem",
457 .data = &pci_thunder_pem_ops,
462 static struct platform_driver thunder_pem_driver = {
464 .name = KBUILD_MODNAME,
465 .of_match_table = thunder_pem_of_match,
466 .suppress_bind_attrs = true,
468 .probe = pci_host_common_probe,
470 builtin_platform_driver(thunder_pem_driver);