1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 #include <linux/kernel.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/init.h>
14 #include <linux/mbus.h>
15 #include <linux/slab.h>
16 #include <linux/platform_device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
24 #include "../pci-bridge-emul.h"
27 * PCIe unit register offsets.
29 #define PCIE_DEV_ID_OFF 0x0000
30 #define PCIE_CMD_OFF 0x0004
31 #define PCIE_DEV_REV_OFF 0x0008
32 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
33 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
34 #define PCIE_CAP_PCIEXP 0x0060
35 #define PCIE_HEADER_LOG_4_OFF 0x0128
36 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
37 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
38 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
39 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
40 #define PCIE_WIN5_CTRL_OFF 0x1880
41 #define PCIE_WIN5_BASE_OFF 0x1884
42 #define PCIE_WIN5_REMAP_OFF 0x188c
43 #define PCIE_CONF_ADDR_OFF 0x18f8
44 #define PCIE_CONF_ADDR_EN 0x80000000
45 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
46 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
47 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
48 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
49 #define PCIE_CONF_ADDR(bus, devfn, where) \
50 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
51 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
53 #define PCIE_CONF_DATA_OFF 0x18fc
54 #define PCIE_MASK_OFF 0x1910
55 #define PCIE_MASK_ENABLE_INTS 0x0f000000
56 #define PCIE_CTRL_OFF 0x1a00
57 #define PCIE_CTRL_X1_MODE 0x0001
58 #define PCIE_STAT_OFF 0x1a04
59 #define PCIE_STAT_BUS 0xff00
60 #define PCIE_STAT_DEV 0x1f0000
61 #define PCIE_STAT_LINK_DOWN BIT(0)
62 #define PCIE_RC_RTSTA 0x1a14
63 #define PCIE_DEBUG_CTRL 0x1a60
64 #define PCIE_DEBUG_SOFT_RESET BIT(20)
66 struct mvebu_pcie_port;
68 /* Structure representing all PCIe interfaces */
70 struct platform_device *pdev;
71 struct mvebu_pcie_port *ports;
73 struct resource realio;
79 struct mvebu_pcie_window {
85 /* Structure representing one PCIe interface */
86 struct mvebu_pcie_port {
92 unsigned int mem_target;
93 unsigned int mem_attr;
94 unsigned int io_target;
97 struct gpio_desc *reset_gpio;
99 struct pci_bridge_emul bridge;
100 struct device_node *dn;
101 struct mvebu_pcie *pcie;
102 struct mvebu_pcie_window memwin;
103 struct mvebu_pcie_window iowin;
105 struct resource regs;
108 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
110 writel(val, port->base + reg);
113 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
115 return readl(port->base + reg);
118 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
120 return port->io_target != -1 && port->io_attr != -1;
123 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
125 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
128 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
132 stat = mvebu_readl(port, PCIE_STAT_OFF);
133 stat &= ~PCIE_STAT_BUS;
135 mvebu_writel(port, stat, PCIE_STAT_OFF);
138 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
142 stat = mvebu_readl(port, PCIE_STAT_OFF);
143 stat &= ~PCIE_STAT_DEV;
145 mvebu_writel(port, stat, PCIE_STAT_OFF);
149 * Setup PCIE BARs and Address Decode Wins:
150 * BAR[0] -> internal registers (needed for MSI)
151 * BAR[1] -> covers all DRAM banks
153 * WIN[0-3] -> DRAM bank[0-3]
155 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
157 const struct mbus_dram_target_info *dram;
161 dram = mv_mbus_dram_info();
163 /* First, disable and clear BARs and windows. */
164 for (i = 1; i < 3; i++) {
165 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
166 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
167 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
170 for (i = 0; i < 5; i++) {
171 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
172 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
173 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
176 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
177 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
178 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
180 /* Setup windows for DDR banks. Count total DDR size on the fly. */
182 for (i = 0; i < dram->num_cs; i++) {
183 const struct mbus_dram_window *cs = dram->cs + i;
185 mvebu_writel(port, cs->base & 0xffff0000,
186 PCIE_WIN04_BASE_OFF(i));
187 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
189 ((cs->size - 1) & 0xffff0000) |
190 (cs->mbus_attr << 8) |
191 (dram->mbus_dram_target_id << 4) | 1,
192 PCIE_WIN04_CTRL_OFF(i));
197 /* Round up 'size' to the nearest power of two. */
198 if ((size & (size - 1)) != 0)
199 size = 1 << fls(size);
201 /* Setup BAR[1] to all DRAM banks. */
202 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
203 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
204 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
205 PCIE_BAR_CTRL_OFF(1));
208 * Point BAR[0] to the device's internal registers.
210 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
211 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
214 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
218 /* Point PCIe unit MBUS decode windows to DRAM space. */
219 mvebu_pcie_setup_wins(port);
221 /* Master + slave enable. */
222 cmd = mvebu_readl(port, PCIE_CMD_OFF);
223 cmd |= PCI_COMMAND_IO;
224 cmd |= PCI_COMMAND_MEMORY;
225 cmd |= PCI_COMMAND_MASTER;
226 mvebu_writel(port, cmd, PCIE_CMD_OFF);
228 /* Enable interrupt lines A-D. */
229 mask = mvebu_readl(port, PCIE_MASK_OFF);
230 mask |= PCIE_MASK_ENABLE_INTS;
231 mvebu_writel(port, mask, PCIE_MASK_OFF);
234 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
236 u32 devfn, int where, int size, u32 *val)
238 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
240 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
245 *val = readb_relaxed(conf_data + (where & 3));
248 *val = readw_relaxed(conf_data + (where & 2));
251 *val = readl_relaxed(conf_data);
255 return PCIBIOS_SUCCESSFUL;
258 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
260 u32 devfn, int where, int size, u32 val)
262 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
264 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
269 writeb(val, conf_data + (where & 3));
272 writew(val, conf_data + (where & 2));
275 writel(val, conf_data);
278 return PCIBIOS_BAD_REGISTER_NUMBER;
281 return PCIBIOS_SUCCESSFUL;
285 * Remove windows, starting from the largest ones to the smallest
288 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
289 phys_addr_t base, size_t size)
292 size_t sz = 1 << (fls(size) - 1);
294 mvebu_mbus_del_window(base, sz);
301 * MBus windows can only have a power of two size, but PCI BARs do not
302 * have this constraint. Therefore, we have to split the PCI BAR into
303 * areas each having a power of two size. We start from the largest
304 * one (i.e highest order bit set in the size).
306 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
307 unsigned int target, unsigned int attribute,
308 phys_addr_t base, size_t size,
311 size_t size_mapped = 0;
314 size_t sz = 1 << (fls(size) - 1);
317 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
320 phys_addr_t end = base + sz - 1;
322 dev_err(&port->pcie->pdev->dev,
323 "Could not create MBus window at [mem %pa-%pa]: %d\n",
325 mvebu_pcie_del_windows(port, base - size_mapped,
333 if (remap != MVEBU_MBUS_NO_REMAP)
338 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
339 unsigned int target, unsigned int attribute,
340 const struct mvebu_pcie_window *desired,
341 struct mvebu_pcie_window *cur)
343 if (desired->base == cur->base && desired->remap == cur->remap &&
344 desired->size == cur->size)
347 if (cur->size != 0) {
348 mvebu_pcie_del_windows(port, cur->base, cur->size);
353 * If something tries to change the window while it is enabled
354 * the change will not be done atomically. That would be
355 * difficult to do in the general case.
359 if (desired->size == 0)
362 mvebu_pcie_add_windows(port, target, attribute, desired->base,
363 desired->size, desired->remap);
367 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
369 struct mvebu_pcie_window desired = {};
370 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
372 /* Are the new iobase/iolimit values invalid? */
373 if (conf->iolimit < conf->iobase ||
374 conf->iolimitupper < conf->iobaseupper ||
375 !(conf->command & PCI_COMMAND_IO)) {
376 mvebu_pcie_set_window(port, port->io_target, port->io_attr,
377 &desired, &port->iowin);
381 if (!mvebu_has_ioport(port)) {
382 dev_WARN(&port->pcie->pdev->dev,
383 "Attempt to set IO when IO is disabled\n");
388 * We read the PCI-to-PCI bridge emulated registers, and
389 * calculate the base address and size of the address decoding
390 * window to setup, according to the PCI-to-PCI bridge
391 * specifications. iobase is the bus address, port->iowin_base
392 * is the CPU address.
394 desired.remap = ((conf->iobase & 0xF0) << 8) |
395 (conf->iobaseupper << 16);
396 desired.base = port->pcie->io.start + desired.remap;
397 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) |
398 (conf->iolimitupper << 16)) -
402 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
406 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
408 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
409 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
411 /* Are the new membase/memlimit values invalid? */
412 if (conf->memlimit < conf->membase ||
413 !(conf->command & PCI_COMMAND_MEMORY)) {
414 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
415 &desired, &port->memwin);
420 * We read the PCI-to-PCI bridge emulated registers, and
421 * calculate the base address and size of the address decoding
422 * window to setup, according to the PCI-to-PCI bridge
425 desired.base = ((conf->membase & 0xFFF0) << 16);
426 desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
429 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
433 static pci_bridge_emul_read_status_t
434 mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
437 struct mvebu_pcie_port *port = bridge->data;
441 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
445 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
446 ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
447 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
452 * PCIe requires the clock power management capability to be
453 * hard-wired to zero for downstream ports
455 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
456 ~PCI_EXP_LNKCAP_CLKPM;
460 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
464 *value = PCI_EXP_SLTSTA_PDS << 16;
468 *value = mvebu_readl(port, PCIE_RC_RTSTA);
472 return PCI_BRIDGE_EMUL_NOT_HANDLED;
475 return PCI_BRIDGE_EMUL_HANDLED;
479 mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
480 int reg, u32 old, u32 new, u32 mask)
482 struct mvebu_pcie_port *port = bridge->data;
483 struct pci_bridge_emul_conf *conf = &bridge->conf;
488 if (!mvebu_has_ioport(port))
489 conf->command &= ~PCI_COMMAND_IO;
491 if ((old ^ new) & PCI_COMMAND_IO)
492 mvebu_pcie_handle_iobase_change(port);
493 if ((old ^ new) & PCI_COMMAND_MEMORY)
494 mvebu_pcie_handle_membase_change(port);
501 * We keep bit 1 set, it is a read-only bit that
502 * indicates we support 32 bits addressing for the
505 conf->iobase |= PCI_IO_RANGE_TYPE_32;
506 conf->iolimit |= PCI_IO_RANGE_TYPE_32;
507 mvebu_pcie_handle_iobase_change(port);
510 case PCI_MEMORY_BASE:
511 mvebu_pcie_handle_membase_change(port);
514 case PCI_IO_BASE_UPPER16:
515 mvebu_pcie_handle_iobase_change(port);
518 case PCI_PRIMARY_BUS:
519 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
528 mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
529 int reg, u32 old, u32 new, u32 mask)
531 struct mvebu_pcie_port *port = bridge->data;
536 * Armada370 data says these bits must always
537 * be zero when in root complex mode.
539 new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
540 PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
542 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
547 * If we don't support CLKREQ, we must ensure that the
548 * CLKREQ enable bit always reads zero. Since we haven't
549 * had this capability, and it's dependent on board wiring,
550 * disable it for the time being.
552 new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
554 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
558 mvebu_writel(port, new, PCIE_RC_RTSTA);
563 static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
564 .write_base = mvebu_pci_bridge_emul_base_conf_write,
565 .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
566 .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
570 * Initialize the configuration space of the PCI-to-PCI bridge
571 * associated with the given PCIe interface.
573 static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
575 struct pci_bridge_emul *bridge = &port->bridge;
576 u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
577 u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);
579 bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
580 bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
581 bridge->conf.class_revision =
582 mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
584 if (mvebu_has_ioport(port)) {
585 /* We support 32 bits I/O addressing */
586 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
587 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
591 * Older mvebu hardware provides PCIe Capability structure only in
592 * version 1. New hardware provides it in version 2.
594 bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
596 bridge->has_pcie = true;
598 bridge->ops = &mvebu_pci_bridge_emul_ops;
600 pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
603 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
605 return sys->private_data;
608 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
614 for (i = 0; i < pcie->nports; i++) {
615 struct mvebu_pcie_port *port = &pcie->ports[i];
617 if (bus->number == 0 && port->devfn == devfn)
619 if (bus->number != 0 &&
620 bus->number >= port->bridge.conf.secondary_bus &&
621 bus->number <= port->bridge.conf.subordinate_bus)
628 /* PCI configuration space write function */
629 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
630 int where, int size, u32 val)
632 struct mvebu_pcie *pcie = bus->sysdata;
633 struct mvebu_pcie_port *port;
636 port = mvebu_pcie_find_port(pcie, bus, devfn);
638 return PCIBIOS_DEVICE_NOT_FOUND;
640 /* Access the emulated PCI-to-PCI bridge */
641 if (bus->number == 0)
642 return pci_bridge_emul_conf_write(&port->bridge, where,
645 if (!mvebu_pcie_link_up(port))
646 return PCIBIOS_DEVICE_NOT_FOUND;
648 /* Access the real PCIe interface */
649 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
655 /* PCI configuration space read function */
656 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
659 struct mvebu_pcie *pcie = bus->sysdata;
660 struct mvebu_pcie_port *port;
663 port = mvebu_pcie_find_port(pcie, bus, devfn);
666 return PCIBIOS_DEVICE_NOT_FOUND;
669 /* Access the emulated PCI-to-PCI bridge */
670 if (bus->number == 0)
671 return pci_bridge_emul_conf_read(&port->bridge, where,
674 if (!mvebu_pcie_link_up(port)) {
676 return PCIBIOS_DEVICE_NOT_FOUND;
679 /* Access the real PCIe interface */
680 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
686 static struct pci_ops mvebu_pcie_ops = {
687 .read = mvebu_pcie_rd_conf,
688 .write = mvebu_pcie_wr_conf,
691 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
692 const struct resource *res,
693 resource_size_t start,
694 resource_size_t size,
695 resource_size_t align)
697 if (dev->bus->number != 0)
701 * On the PCI-to-PCI bridge side, the I/O windows must have at
702 * least a 64 KB size and the memory windows must have at
703 * least a 1 MB size. Moreover, MBus windows need to have a
704 * base address aligned on their size, and their size must be
705 * a power of two. This means that if the BAR doesn't have a
706 * power of two size, several MBus windows will actually be
707 * created. We need to ensure that the biggest MBus window
708 * (which will be the first one) is aligned on its size, which
709 * explains the rounddown_pow_of_two() being done here.
711 if (res->flags & IORESOURCE_IO)
712 return round_up(start, max_t(resource_size_t, SZ_64K,
713 rounddown_pow_of_two(size)));
714 else if (res->flags & IORESOURCE_MEM)
715 return round_up(start, max_t(resource_size_t, SZ_1M,
716 rounddown_pow_of_two(size)));
721 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
722 struct device_node *np,
723 struct mvebu_pcie_port *port)
727 ret = of_address_to_resource(np, 0, &port->regs);
729 return (void __iomem *)ERR_PTR(ret);
731 return devm_ioremap_resource(&pdev->dev, &port->regs);
734 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
735 #define DT_TYPE_IO 0x1
736 #define DT_TYPE_MEM32 0x2
737 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
738 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
740 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
745 const int na = 3, ns = 2;
747 int rlen, nranges, rangesz, pna, i;
752 range = of_get_property(np, "ranges", &rlen);
756 pna = of_n_addr_cells(np);
757 rangesz = pna + na + ns;
758 nranges = rlen / sizeof(__be32) / rangesz;
760 for (i = 0; i < nranges; i++, range += rangesz) {
761 u32 flags = of_read_number(range, 1);
762 u32 slot = of_read_number(range + 1, 1);
763 u64 cpuaddr = of_read_number(range + na, pna);
766 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
767 rtype = IORESOURCE_IO;
768 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
769 rtype = IORESOURCE_MEM;
773 if (slot == PCI_SLOT(devfn) && type == rtype) {
774 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
775 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
783 #ifdef CONFIG_PM_SLEEP
784 static int mvebu_pcie_suspend(struct device *dev)
786 struct mvebu_pcie *pcie;
789 pcie = dev_get_drvdata(dev);
790 for (i = 0; i < pcie->nports; i++) {
791 struct mvebu_pcie_port *port = pcie->ports + i;
792 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
798 static int mvebu_pcie_resume(struct device *dev)
800 struct mvebu_pcie *pcie;
803 pcie = dev_get_drvdata(dev);
804 for (i = 0; i < pcie->nports; i++) {
805 struct mvebu_pcie_port *port = pcie->ports + i;
806 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
807 mvebu_pcie_setup_hw(port);
814 static void mvebu_pcie_port_clk_put(void *data)
816 struct mvebu_pcie_port *port = data;
821 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
822 struct mvebu_pcie_port *port, struct device_node *child)
824 struct device *dev = &pcie->pdev->dev;
825 enum of_gpio_flags flags;
830 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
831 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
836 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
839 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
846 port->devfn = of_pci_get_devfn(child);
850 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
851 &port->mem_target, &port->mem_attr);
853 dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
858 if (resource_size(&pcie->io) != 0) {
859 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
860 &port->io_target, &port->io_attr);
862 port->io_target = -1;
866 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
867 if (reset_gpio == -EPROBE_DEFER) {
872 if (gpio_is_valid(reset_gpio)) {
873 unsigned long gpio_flags;
875 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
877 if (!port->reset_name) {
882 if (flags & OF_GPIO_ACTIVE_LOW) {
883 dev_info(dev, "%pOF: reset gpio is active low\n",
885 gpio_flags = GPIOF_ACTIVE_LOW |
888 gpio_flags = GPIOF_OUT_INIT_HIGH;
891 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
894 if (ret == -EPROBE_DEFER)
899 port->reset_gpio = gpio_to_desc(reset_gpio);
902 port->clk = of_clk_get_by_name(child, NULL);
903 if (IS_ERR(port->clk)) {
904 dev_err(dev, "%s: cannot get clock\n", port->name);
908 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
919 /* In the case of skipping, we need to free these */
920 devm_kfree(dev, port->reset_name);
921 port->reset_name = NULL;
922 devm_kfree(dev, port->name);
930 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
931 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
932 * of the PCI Express Card Electromechanical Specification, 1.1.
934 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
938 ret = clk_prepare_enable(port->clk);
942 if (port->reset_gpio) {
943 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
945 of_property_read_u32(port->dn, "reset-delay-us",
950 gpiod_set_value_cansleep(port->reset_gpio, 0);
951 msleep(reset_udelay / 1000);
958 * Power down a PCIe port. Strictly, PCIe requires us to place the card
959 * in D3hot state before asserting PERST#.
961 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
963 gpiod_set_value_cansleep(port->reset_gpio, 1);
965 clk_disable_unprepare(port->clk);
969 * devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
970 * so we need extra resource setup parsing our special DT properties encoding
971 * the MEM and IO apertures.
973 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
975 struct device *dev = &pcie->pdev->dev;
976 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
979 /* Get the PCIe memory aperture */
980 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
981 if (resource_size(&pcie->mem) == 0) {
982 dev_err(dev, "invalid memory aperture size\n");
986 pcie->mem.name = "PCI MEM";
987 pci_add_resource(&bridge->windows, &pcie->mem);
988 ret = devm_request_resource(dev, &iomem_resource, &pcie->mem);
992 /* Get the PCIe IO aperture */
993 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
995 if (resource_size(&pcie->io) != 0) {
996 pcie->realio.flags = pcie->io.flags;
997 pcie->realio.start = PCIBIOS_MIN_IO;
998 pcie->realio.end = min_t(resource_size_t,
999 IO_SPACE_LIMIT - SZ_64K,
1000 resource_size(&pcie->io) - 1);
1001 pcie->realio.name = "PCI I/O";
1003 pci_add_resource(&bridge->windows, &pcie->realio);
1004 ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
1013 * This is a copy of pci_host_probe(), except that it does the I/O
1014 * remap as the last step, once we are sure we won't fail.
1016 * It should be removed once the I/O remap error handling issue has
1019 static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
1021 struct mvebu_pcie *pcie;
1022 struct pci_bus *bus, *child;
1025 ret = pci_scan_root_bus_bridge(bridge);
1027 dev_err(bridge->dev.parent, "Scanning root bridge failed");
1031 pcie = pci_host_bridge_priv(bridge);
1032 if (resource_size(&pcie->io) != 0) {
1035 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
1036 pci_ioremap_io(i, pcie->io.start + i);
1042 * We insert PCI resources into the iomem_resource and
1043 * ioport_resource trees in either pci_bus_claim_resources()
1044 * or pci_bus_assign_resources().
1046 if (pci_has_flag(PCI_PROBE_ONLY)) {
1047 pci_bus_claim_resources(bus);
1049 pci_bus_size_bridges(bus);
1050 pci_bus_assign_resources(bus);
1052 list_for_each_entry(child, &bus->children, node)
1053 pcie_bus_configure_settings(child);
1056 pci_bus_add_devices(bus);
1060 static int mvebu_pcie_probe(struct platform_device *pdev)
1062 struct device *dev = &pdev->dev;
1063 struct mvebu_pcie *pcie;
1064 struct pci_host_bridge *bridge;
1065 struct device_node *np = dev->of_node;
1066 struct device_node *child;
1069 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie));
1073 pcie = pci_host_bridge_priv(bridge);
1075 platform_set_drvdata(pdev, pcie);
1077 ret = mvebu_pcie_parse_request_resources(pcie);
1081 num = of_get_available_child_count(np);
1083 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
1088 for_each_available_child_of_node(np, child) {
1089 struct mvebu_pcie_port *port = &pcie->ports[i];
1091 ret = mvebu_pcie_parse_port(pcie, port, child);
1095 } else if (ret == 0) {
1104 for (i = 0; i < pcie->nports; i++) {
1105 struct mvebu_pcie_port *port = &pcie->ports[i];
1111 ret = mvebu_pcie_powerup(port);
1115 port->base = mvebu_pcie_map_registers(pdev, child, port);
1116 if (IS_ERR(port->base)) {
1117 dev_err(dev, "%s: cannot map registers\n", port->name);
1119 mvebu_pcie_powerdown(port);
1123 mvebu_pcie_setup_hw(port);
1124 mvebu_pcie_set_local_dev_nr(port, 1);
1125 mvebu_pci_bridge_emul_init(port);
1130 bridge->sysdata = pcie;
1131 bridge->ops = &mvebu_pcie_ops;
1132 bridge->align_resource = mvebu_pcie_align_resource;
1134 return mvebu_pci_host_probe(bridge);
1137 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1138 { .compatible = "marvell,armada-xp-pcie", },
1139 { .compatible = "marvell,armada-370-pcie", },
1140 { .compatible = "marvell,dove-pcie", },
1141 { .compatible = "marvell,kirkwood-pcie", },
1145 static const struct dev_pm_ops mvebu_pcie_pm_ops = {
1146 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume)
1149 static struct platform_driver mvebu_pcie_driver = {
1151 .name = "mvebu-pcie",
1152 .of_match_table = mvebu_pcie_of_match_table,
1153 /* driver unloading/unbinding currently not supported */
1154 .suppress_bind_attrs = true,
1155 .pm = &mvebu_pcie_pm_ops,
1157 .probe = mvebu_pcie_probe,
1159 builtin_platform_driver(mvebu_pcie_driver);