1 // SPDX-License-Identifier: GPL-2.0
3 * Loongson PCI Host Controller Driver
5 * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
8 #include <linux/of_device.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci.h>
11 #include <linux/pci_ids.h>
16 #define DEV_LS2K_PCIE_PORT0 0x1a05
17 #define DEV_LS7A_PCIE_PORT0 0x7a09
18 #define DEV_LS7A_PCIE_PORT1 0x7a19
19 #define DEV_LS7A_PCIE_PORT2 0x7a29
20 #define DEV_LS7A_PCIE_PORT3 0x7a39
21 #define DEV_LS7A_PCIE_PORT4 0x7a49
22 #define DEV_LS7A_PCIE_PORT5 0x7a59
23 #define DEV_LS7A_PCIE_PORT6 0x7a69
25 #define DEV_LS2K_APB 0x7a02
26 #define DEV_LS7A_CONF 0x7a10
27 #define DEV_LS7A_LPC 0x7a0c
29 #define FLAG_CFG0 BIT(0)
30 #define FLAG_CFG1 BIT(1)
31 #define FLAG_DEV_FIX BIT(2)
34 void __iomem *cfg0_base;
35 void __iomem *cfg1_base;
36 struct platform_device *pdev;
40 /* Fixup wrong class code in PCIe bridges */
41 static void bridge_class_quirk(struct pci_dev *dev)
43 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
45 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
46 DEV_LS7A_PCIE_PORT0, bridge_class_quirk);
47 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
48 DEV_LS7A_PCIE_PORT1, bridge_class_quirk);
49 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
50 DEV_LS7A_PCIE_PORT2, bridge_class_quirk);
52 static void system_bus_quirk(struct pci_dev *pdev)
55 * The address space consumed by these devices is outside the
56 * resources of the host bridge.
58 pdev->mmio_always_on = 1;
59 pdev->non_compliant_bars = 1;
61 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
62 DEV_LS2K_APB, system_bus_quirk);
63 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
64 DEV_LS7A_CONF, system_bus_quirk);
65 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
66 DEV_LS7A_LPC, system_bus_quirk);
69 * Some Loongson PCIe ports have hardware limitations on their Maximum Read
70 * Request Size. They can't handle anything larger than this. Sane
71 * firmware will set proper MRRS at boot, so we only need no_inc_mrrs for
72 * bridges. However, some MIPS Loongson firmware doesn't set MRRS properly,
73 * so we have to enforce maximum safe MRRS, which is 256 bytes.
76 static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev)
78 struct pci_bus *bus = pdev->bus;
79 struct pci_dev *bridge;
80 static const struct pci_device_id bridge_devids[] = {
81 { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) },
82 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) },
83 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) },
84 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) },
85 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) },
86 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) },
87 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) },
88 { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) },
92 /* look for the matching bridge */
93 while (!pci_is_root_bus(bus)) {
97 if (pci_match_id(bridge_devids, bridge)) {
98 if (pcie_get_readrq(pdev) > 256) {
99 pci_info(pdev, "limiting MRRS to 256\n");
100 pcie_set_readrq(pdev, 256);
106 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_set_min_mrrs_quirk);
109 static void loongson_mrrs_quirk(struct pci_dev *pdev)
111 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
113 bridge->no_inc_mrrs = 1;
115 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
116 DEV_LS2K_PCIE_PORT0, loongson_mrrs_quirk);
117 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
118 DEV_LS7A_PCIE_PORT0, loongson_mrrs_quirk);
119 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
120 DEV_LS7A_PCIE_PORT1, loongson_mrrs_quirk);
121 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
122 DEV_LS7A_PCIE_PORT2, loongson_mrrs_quirk);
123 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
124 DEV_LS7A_PCIE_PORT3, loongson_mrrs_quirk);
125 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
126 DEV_LS7A_PCIE_PORT4, loongson_mrrs_quirk);
127 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
128 DEV_LS7A_PCIE_PORT5, loongson_mrrs_quirk);
129 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
130 DEV_LS7A_PCIE_PORT6, loongson_mrrs_quirk);
132 static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
133 unsigned int devfn, int where)
135 unsigned long addroff = 0x0;
138 addroff |= BIT(28); /* Type 1 Access */
139 addroff |= (where & 0xff) | ((where & 0xf00) << 16);
140 addroff |= (bus << 16) | (devfn << 8);
141 return priv->cfg1_base + addroff;
144 static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
145 unsigned int devfn, int where)
147 unsigned long addroff = 0x0;
150 addroff |= BIT(24); /* Type 1 Access */
151 addroff |= (bus << 16) | (devfn << 8) | where;
152 return priv->cfg0_base + addroff;
155 static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
158 unsigned char busnum = bus->number;
159 struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
160 struct loongson_pci *priv = pci_host_bridge_priv(bridge);
163 * Do not read more than one device on the bus other than
164 * the host bus. For our hardware the root bus is always bus 0.
166 if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
170 /* CFG0 can only access standard space */
171 if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
172 return cfg0_map(priv, busnum, devfn, where);
174 /* CFG1 can access extended space */
175 if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
176 return cfg1_map(priv, busnum, devfn, where);
181 static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
186 irq = of_irq_parse_and_map_pci(dev, slot, pin);
190 /* Care i8259 legacy systems */
191 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
192 /* i8259 only have 15 IRQs */
199 /* H/w only accept 32-bit PCI operations */
200 static struct pci_ops loongson_pci_ops = {
201 .map_bus = pci_loongson_map_bus,
202 .read = pci_generic_config_read32,
203 .write = pci_generic_config_write32,
206 static const struct of_device_id loongson_pci_of_match[] = {
207 { .compatible = "loongson,ls2k-pci",
208 .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
209 { .compatible = "loongson,ls7a-pci",
210 .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
211 { .compatible = "loongson,rs780e-pci",
212 .data = (void *)(FLAG_CFG0), },
216 static int loongson_pci_probe(struct platform_device *pdev)
218 struct loongson_pci *priv;
219 struct device *dev = &pdev->dev;
220 struct device_node *node = dev->of_node;
221 struct pci_host_bridge *bridge;
222 struct resource *regs;
227 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
231 priv = pci_host_bridge_priv(bridge);
233 priv->flags = (unsigned long)of_device_get_match_data(dev);
235 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
237 dev_err(dev, "missing mem resources for cfg0\n");
241 priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
242 if (IS_ERR(priv->cfg0_base))
243 return PTR_ERR(priv->cfg0_base);
245 /* CFG1 is optional */
246 if (priv->flags & FLAG_CFG1) {
247 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
249 dev_info(dev, "missing mem resource for cfg1\n");
251 priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
252 if (IS_ERR(priv->cfg1_base))
253 priv->cfg1_base = NULL;
257 bridge->sysdata = priv;
258 bridge->ops = &loongson_pci_ops;
259 bridge->map_irq = loongson_map_irq;
261 return pci_host_probe(bridge);
264 static struct platform_driver loongson_pci_driver = {
266 .name = "loongson-pci",
267 .of_match_table = loongson_pci_of_match,
269 .probe = loongson_pci_probe,
271 builtin_platform_driver(loongson_pci_driver);