1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
6 * Copyright (C) 2016 Marvell
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_gpio.h>
25 #include <linux/of_pci.h>
28 #include "../pci-bridge-emul.h"
30 /* PCIe core registers */
31 #define PCIE_CORE_DEV_ID_REG 0x0
32 #define PCIE_CORE_CMD_STATUS_REG 0x4
33 #define PCIE_CORE_DEV_REV_REG 0x8
34 #define PCIE_CORE_PCIEXP_CAP 0xc0
35 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
36 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
37 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
40 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
41 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
42 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3
43 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4
44 /* PIO registers base address and register offsets */
45 #define PIO_BASE_ADDR 0x4000
46 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
47 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
48 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
49 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
50 #define PIO_COMPLETION_STATUS_SHIFT 7
51 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
52 #define PIO_COMPLETION_STATUS_OK 0
53 #define PIO_COMPLETION_STATUS_UR 1
54 #define PIO_COMPLETION_STATUS_CRS 2
55 #define PIO_COMPLETION_STATUS_CA 4
56 #define PIO_NON_POSTED_REQ BIT(10)
57 #define PIO_ERR_STATUS BIT(11)
58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63 #define PIO_START (PIO_BASE_ADDR + 0x1c)
64 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
67 /* Aardvark Control registers */
68 #define CONTROL_BASE_ADDR 0x4800
69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70 #define PCIE_GEN_SEL_MSK 0x3
71 #define PCIE_GEN_SEL_SHIFT 0x0
77 #define LANE_CNT_MSK 0x18
78 #define LANE_CNT_SHIFT 0x3
79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
81 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
82 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
83 #define LINK_TRAINING_EN BIT(6)
84 #define LEGACY_INTA BIT(28)
85 #define LEGACY_INTB BIT(29)
86 #define LEGACY_INTC BIT(30)
87 #define LEGACY_INTD BIT(31)
88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89 #define HOT_RESET_GEN BIT(0)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
95 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
96 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
97 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
98 #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2)
99 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
100 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
101 #define PCIE_MSG_PM_PME_MASK BIT(7)
102 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
103 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
104 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
105 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
106 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
107 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
108 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
109 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
110 #define PCIE_ISR1_FLUSH BIT(5)
111 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
112 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
113 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
114 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
115 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
116 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
117 #define PCIE_MSI_ALL_MASK GENMASK(31, 0)
118 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
119 #define PCIE_MSI_DATA_MASK GENMASK(15, 0)
121 /* PCIe window configuration */
122 #define OB_WIN_BASE_ADDR 0x4c00
123 #define OB_WIN_BLOCK_SIZE 0x20
124 #define OB_WIN_COUNT 8
125 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
126 OB_WIN_BLOCK_SIZE * (win) + \
128 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
129 #define OB_WIN_ENABLE BIT(0)
130 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
131 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
132 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
133 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
134 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
135 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
136 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
137 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
138 #define OB_WIN_FUNC_NUM_SHIFT 24
139 #define OB_WIN_FUNC_NUM_ENABLE BIT(23)
140 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
141 #define OB_WIN_BUS_NUM_BITS_SHIFT 20
142 #define OB_WIN_MSG_CODE_ENABLE BIT(22)
143 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
144 #define OB_WIN_MSG_CODE_SHIFT 14
145 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
146 #define OB_WIN_ATTR_ENABLE BIT(11)
147 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
148 #define OB_WIN_ATTR_TC_SHIFT 8
149 #define OB_WIN_ATTR_RELAXED BIT(7)
150 #define OB_WIN_ATTR_NOSNOOP BIT(6)
151 #define OB_WIN_ATTR_POISON BIT(5)
152 #define OB_WIN_ATTR_IDO BIT(4)
153 #define OB_WIN_TYPE_MASK GENMASK(3, 0)
154 #define OB_WIN_TYPE_SHIFT 0
155 #define OB_WIN_TYPE_MEM 0x0
156 #define OB_WIN_TYPE_IO 0x4
157 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
158 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
159 #define OB_WIN_TYPE_MSG 0xc
161 /* LMI registers base address and register offsets */
162 #define LMI_BASE_ADDR 0x6000
163 #define CFG_REG (LMI_BASE_ADDR + 0x0)
164 #define LTSSM_SHIFT 24
165 #define LTSSM_MASK 0x3f
166 #define RC_BAR_CONFIG 0x300
168 /* LTSSM values in CFG_REG */
170 LTSSM_DETECT_QUIET = 0x0,
171 LTSSM_DETECT_ACTIVE = 0x1,
172 LTSSM_POLLING_ACTIVE = 0x2,
173 LTSSM_POLLING_COMPLIANCE = 0x3,
174 LTSSM_POLLING_CONFIGURATION = 0x4,
175 LTSSM_CONFIG_LINKWIDTH_START = 0x5,
176 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
177 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
178 LTSSM_CONFIG_LANENUM_WAIT = 0x8,
179 LTSSM_CONFIG_COMPLETE = 0x9,
180 LTSSM_CONFIG_IDLE = 0xa,
181 LTSSM_RECOVERY_RCVR_LOCK = 0xb,
182 LTSSM_RECOVERY_SPEED = 0xc,
183 LTSSM_RECOVERY_RCVR_CFG = 0xd,
184 LTSSM_RECOVERY_IDLE = 0xe,
186 LTSSM_RX_L0S_ENTRY = 0x11,
187 LTSSM_RX_L0S_IDLE = 0x12,
188 LTSSM_RX_L0S_FTS = 0x13,
189 LTSSM_TX_L0S_ENTRY = 0x14,
190 LTSSM_TX_L0S_IDLE = 0x15,
191 LTSSM_TX_L0S_FTS = 0x16,
192 LTSSM_L1_ENTRY = 0x17,
193 LTSSM_L1_IDLE = 0x18,
194 LTSSM_L2_IDLE = 0x19,
195 LTSSM_L2_TRANSMIT_WAKE = 0x1a,
196 LTSSM_DISABLED = 0x20,
197 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
198 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
199 LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
200 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
201 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
202 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
203 LTSSM_HOT_RESET = 0x27,
204 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
205 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
206 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
207 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
210 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
212 /* PCIe core controller registers */
213 #define CTRL_CORE_BASE_ADDR 0x18000
214 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
215 #define CTRL_MODE_SHIFT 0x0
216 #define CTRL_MODE_MASK 0x1
217 #define PCIE_CORE_MODE_DIRECT 0x0
218 #define PCIE_CORE_MODE_COMMAND 0x1
220 /* PCIe Central Interrupts Registers */
221 #define CENTRAL_INT_BASE_ADDR 0x1b000
222 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
223 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
224 #define PCIE_IRQ_CMDQ_INT BIT(0)
225 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
226 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
227 #define PCIE_IRQ_DMA_INT BIT(4)
228 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
229 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
230 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
231 #define PCIE_IRQ_COMPQ_INT BIT(12)
232 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
233 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
234 #define PCIE_IRQ_CORE_INT BIT(16)
235 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
236 #define PCIE_IRQ_DPMU_INT BIT(18)
237 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
238 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
239 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
240 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
241 #define PCIE_IRQ_EP_STATUS BIT(23)
242 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
243 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
245 /* Transaction types */
246 #define PCIE_CONFIG_RD_TYPE0 0x8
247 #define PCIE_CONFIG_RD_TYPE1 0x9
248 #define PCIE_CONFIG_WR_TYPE0 0xa
249 #define PCIE_CONFIG_WR_TYPE1 0xb
251 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
252 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
253 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
254 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
255 #define PCIE_CONF_ADDR(bus, devfn, where) \
256 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
257 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
259 #define PIO_RETRY_CNT 750000 /* 1.5 s */
260 #define PIO_RETRY_DELAY 2 /* 2 us*/
262 #define LINK_WAIT_MAX_RETRIES 10
263 #define LINK_WAIT_USLEEP_MIN 90000
264 #define LINK_WAIT_USLEEP_MAX 100000
265 #define RETRAIN_WAIT_MAX_RETRIES 10
266 #define RETRAIN_WAIT_USLEEP_US 2000
268 #define MSI_IRQ_NUM 32
270 #define CFG_RD_CRS_VAL 0xffff0001
273 struct platform_device *pdev;
280 } wins[OB_WIN_COUNT];
282 struct irq_domain *irq_domain;
283 struct irq_chip irq_chip;
284 raw_spinlock_t irq_lock;
285 struct irq_domain *msi_domain;
286 struct irq_domain *msi_inner_domain;
287 struct irq_chip msi_bottom_irq_chip;
288 struct irq_chip msi_irq_chip;
289 struct msi_domain_info msi_domain_info;
290 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
291 struct mutex msi_used_lock;
294 struct pci_bridge_emul bridge;
295 struct gpio_desc *reset_gpio;
299 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
301 writel(val, pcie->base + reg);
304 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
306 return readl(pcie->base + reg);
309 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
314 val = advk_readl(pcie, CFG_REG);
315 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
319 static inline bool advk_pcie_link_up(struct advk_pcie *pcie)
321 /* check if LTSSM is in normal operation - some L* state */
322 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
323 return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
326 static inline bool advk_pcie_link_active(struct advk_pcie *pcie)
329 * According to PCIe Base specification 3.0, Table 4-14: Link
330 * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle
331 * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0,
332 * L0s, L1 and L2 states. And according to 3.2.1. Data Link
333 * Control and Management State Machine Rules is DL Up status
334 * reported in DL Active state.
336 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
337 return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED;
340 static inline bool advk_pcie_link_training(struct advk_pcie *pcie)
343 * According to PCIe Base specification 3.0, Table 4-14: Link
344 * Status Mapped to the LTSSM is Link Training mapped to LTSSM
345 * Configuration and Recovery states.
347 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
348 return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START &&
349 ltssm_state < LTSSM_L0) ||
350 (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 &&
351 ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3));
354 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
358 /* check if the link is up or not */
359 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
360 if (advk_pcie_link_up(pcie))
363 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
369 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
373 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
374 if (advk_pcie_link_training(pcie))
376 udelay(RETRAIN_WAIT_USLEEP_US);
380 static void advk_pcie_issue_perst(struct advk_pcie *pcie)
382 if (!pcie->reset_gpio)
385 /* 10ms delay is needed for some cards */
386 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
387 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
388 usleep_range(10000, 11000);
389 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
392 static void advk_pcie_train_link(struct advk_pcie *pcie)
394 struct device *dev = &pcie->pdev->dev;
399 * Setup PCIe rev / gen compliance based on device tree property
400 * 'max-link-speed' which also forces maximal link speed.
402 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
403 reg &= ~PCIE_GEN_SEL_MSK;
404 if (pcie->link_gen == 3)
406 else if (pcie->link_gen == 2)
410 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
413 * Set maximal link speed value also into PCIe Link Control 2 register.
414 * Armada 3700 Functional Specification says that default value is based
415 * on SPEED_GEN but tests showed that default value is always 8.0 GT/s.
417 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
418 reg &= ~PCI_EXP_LNKCTL2_TLS;
419 if (pcie->link_gen == 3)
420 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;
421 else if (pcie->link_gen == 2)
422 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;
424 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;
425 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
427 /* Enable link training after selecting PCIe generation */
428 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
429 reg |= LINK_TRAINING_EN;
430 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
433 * Reset PCIe card via PERST# signal. Some cards are not detected
434 * during link training when they are in some non-initial state.
436 advk_pcie_issue_perst(pcie);
439 * PERST# signal could have been asserted by pinctrl subsystem before
440 * probe() callback has been called or issued explicitly by reset gpio
441 * function advk_pcie_issue_perst(), making the endpoint going into
442 * fundamental reset. As required by PCI Express spec (PCI Express
443 * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1
444 * Conventional Reset) a delay for at least 100ms after such a reset
445 * before sending a Configuration Request to the device is needed.
446 * So wait until PCIe link is up. Function advk_pcie_wait_for_link()
447 * waits for link at least 900ms.
449 ret = advk_pcie_wait_for_link(pcie);
451 dev_err(dev, "link never came up\n");
453 dev_info(dev, "link up\n");
457 * Set PCIe address window register which could be used for memory
460 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num,
461 phys_addr_t match, phys_addr_t remap,
462 phys_addr_t mask, u32 actions)
464 advk_writel(pcie, OB_WIN_ENABLE |
465 lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
466 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
467 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
468 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
469 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
470 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
471 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
474 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num)
476 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
477 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
478 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
479 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
480 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
481 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
482 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
485 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
491 * Configure PCIe Reference clock. Direction is from the PCIe
492 * controller to the endpoint card, so enable transmitting of
493 * Reference clock differential signal off-chip and disable
494 * receiving off-chip differential signal.
496 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
497 reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
498 reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE;
499 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
501 /* Set to Direct mode */
502 reg = advk_readl(pcie, CTRL_CONFIG_REG);
503 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
504 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
505 advk_writel(pcie, reg, CTRL_CONFIG_REG);
507 /* Set PCI global control register to RC mode */
508 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
509 reg |= (IS_RC_MSK << IS_RC_SHIFT);
510 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
513 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
514 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
515 * id in high 16 bits. Updating this register changes readback value of
516 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
517 * for erratum 4.1: "The value of device and vendor ID is incorrect".
519 reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
520 advk_writel(pcie, reg, VENDOR_ID_REG);
523 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
524 * because the default value is Mass storage controller (0x010400).
526 * Note that this Aardvark PCI Bridge does not have compliant Type 1
527 * Configuration Space and it even cannot be accessed via Aardvark's
528 * PCI config space access method. Something like config space is
529 * available in internal Aardvark registers starting at offset 0x0
530 * and is reported as Type 0. In range 0x10 - 0x34 it has totally
531 * different registers.
533 * Therefore driver uses emulation of PCI Bridge which emulates
534 * access to configuration space via internal Aardvark registers or
535 * emulated configuration buffer.
537 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
539 reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
540 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
542 /* Disable Root Bridge I/O space, memory space and bus mastering */
543 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
544 reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
545 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
547 /* Set Advanced Error Capabilities and Control PF0 register */
548 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
549 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
550 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
551 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
552 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
554 /* Set PCIe Device Control register */
555 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
556 reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
557 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
558 reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
559 reg &= ~PCI_EXP_DEVCTL_READRQ;
560 reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
561 reg |= PCI_EXP_DEVCTL_READRQ_512B;
562 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
564 /* Program PCIe Control 2 to disable strict ordering */
565 reg = PCIE_CORE_CTRL2_RESERVED |
566 PCIE_CORE_CTRL2_TD_ENABLE;
567 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
570 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
571 reg &= ~LANE_CNT_MSK;
573 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
577 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
578 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
580 /* Clear all interrupts */
581 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
582 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
583 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
584 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
586 /* Disable All ISR0/1 Sources */
587 reg = PCIE_ISR0_ALL_MASK;
588 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
589 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
591 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
593 /* Unmask all MSIs */
594 advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
596 /* Enable summary interrupt for GIC SPI source */
597 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
598 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
601 * Enable AXI address window location generation:
602 * When it is enabled, the default outbound window
603 * configurations (Default User Field: 0xD0074CFC)
604 * are used to transparent address translation for
605 * the outbound transactions. Thus, PCIe address
606 * windows are not required for transparent memory
607 * access when default outbound window configuration
608 * is set for memory access.
610 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
611 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
612 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
615 * Set memory access in Default User Field so it
616 * is not required to configure PCIe address for
617 * transparent memory access.
619 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
622 * Bypass the address window mapping for PIO:
623 * Since PIO access already contains all required
624 * info over AXI interface by PIO registers, the
625 * address window is not required.
627 reg = advk_readl(pcie, PIO_CTRL);
628 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
629 advk_writel(pcie, reg, PIO_CTRL);
632 * Configure PCIe address windows for non-memory or
633 * non-transparent access as by default PCIe uses
634 * transparent memory access.
636 for (i = 0; i < pcie->wins_count; i++)
637 advk_pcie_set_ob_win(pcie, i,
638 pcie->wins[i].match, pcie->wins[i].remap,
639 pcie->wins[i].mask, pcie->wins[i].actions);
641 /* Disable remaining PCIe outbound windows */
642 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
643 advk_pcie_disable_ob_win(pcie, i);
645 advk_pcie_train_link(pcie);
648 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
650 struct device *dev = &pcie->pdev->dev;
653 char *strcomp_status, *str_posted;
656 reg = advk_readl(pcie, PIO_STAT);
657 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
658 PIO_COMPLETION_STATUS_SHIFT;
661 * According to HW spec, the PIO status check sequence as below:
662 * 1) even if COMPLETION_STATUS(bit9:7) indicates successful,
663 * it still needs to check Error Status(bit11), only when this bit
664 * indicates no error happen, the operation is successful.
665 * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only
666 * means a PIO write error, and for PIO read it is successful with
667 * a read value of 0xFFFFFFFF.
668 * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7)
669 * only means a PIO write error, and for PIO read it is successful
670 * with a read value of 0xFFFF0001.
671 * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means
672 * error for both PIO read and PIO write operation.
673 * 5) other errors are indicated as 'unknown'.
676 case PIO_COMPLETION_STATUS_OK:
677 if (reg & PIO_ERR_STATUS) {
678 strcomp_status = "COMP_ERR";
682 /* Get the read result */
684 *val = advk_readl(pcie, PIO_RD_DATA);
686 strcomp_status = NULL;
689 case PIO_COMPLETION_STATUS_UR:
690 strcomp_status = "UR";
693 case PIO_COMPLETION_STATUS_CRS:
694 if (allow_crs && val) {
695 /* PCIe r4.0, sec 2.3.2, says:
696 * If CRS Software Visibility is enabled:
697 * For a Configuration Read Request that includes both
698 * bytes of the Vendor ID field of a device Function's
699 * Configuration Space Header, the Root Complex must
700 * complete the Request to the host by returning a
701 * read-data value of 0001h for the Vendor ID field and
702 * all '1's for any additional bytes included in the
705 * So CRS in this case is not an error status.
707 *val = CFG_RD_CRS_VAL;
708 strcomp_status = NULL;
712 /* PCIe r4.0, sec 2.3.2, says:
713 * If CRS Software Visibility is not enabled, the Root Complex
714 * must re-issue the Configuration Request as a new Request.
715 * If CRS Software Visibility is enabled: For a Configuration
716 * Write Request or for any other Configuration Read Request,
717 * the Root Complex must re-issue the Configuration Request as
719 * A Root Complex implementation may choose to limit the number
720 * of Configuration Request/CRS Completion Status loops before
721 * determining that something is wrong with the target of the
722 * Request and taking appropriate action, e.g., complete the
723 * Request to the host as a failed transaction.
725 * So return -EAGAIN and caller (pci-aardvark.c driver) will
726 * re-issue request again up to the PIO_RETRY_CNT retries.
728 strcomp_status = "CRS";
731 case PIO_COMPLETION_STATUS_CA:
732 strcomp_status = "CA";
736 strcomp_status = "Unknown";
744 if (reg & PIO_NON_POSTED_REQ)
745 str_posted = "Non-posted";
747 str_posted = "Posted";
749 dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
750 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
755 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
757 struct device *dev = &pcie->pdev->dev;
760 for (i = 1; i <= PIO_RETRY_CNT; i++) {
763 start = advk_readl(pcie, PIO_START);
764 isr = advk_readl(pcie, PIO_ISR);
767 udelay(PIO_RETRY_DELAY);
770 dev_err(dev, "PIO read/write transfer time out\n");
774 static pci_bridge_emul_read_status_t
775 advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
778 struct advk_pcie *pcie = bridge->data;
782 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
783 return PCI_BRIDGE_EMUL_HANDLED;
785 case PCI_INTERRUPT_LINE: {
787 * From the whole 32bit register we support reading from HW only
788 * one bit: PCI_BRIDGE_CTL_BUS_RESET.
789 * Other bits are retrieved only from emulated config buffer.
791 __le32 *cfgspace = (__le32 *)&bridge->conf;
792 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
793 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)
794 val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
796 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
798 return PCI_BRIDGE_EMUL_HANDLED;
802 return PCI_BRIDGE_EMUL_NOT_HANDLED;
807 advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
808 int reg, u32 old, u32 new, u32 mask)
810 struct advk_pcie *pcie = bridge->data;
814 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
817 case PCI_INTERRUPT_LINE:
818 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
819 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
820 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
821 val |= HOT_RESET_GEN;
823 val &= ~HOT_RESET_GEN;
824 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
833 static pci_bridge_emul_read_status_t
834 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
837 struct advk_pcie *pcie = bridge->data;
842 *value = PCI_EXP_SLTSTA_PDS << 16;
843 return PCI_BRIDGE_EMUL_HANDLED;
845 case PCI_EXP_RTCTL: {
846 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
847 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
848 *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE;
849 *value |= PCI_EXP_RTCAP_CRSVIS << 16;
850 return PCI_BRIDGE_EMUL_HANDLED;
853 case PCI_EXP_RTSTA: {
854 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
855 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
856 *value = msglog >> 16;
857 if (isr0 & PCIE_MSG_PM_PME_MASK)
858 *value |= PCI_EXP_RTSTA_PME;
859 return PCI_BRIDGE_EMUL_HANDLED;
862 case PCI_EXP_LNKCAP: {
863 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
865 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0.
866 * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm
867 * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag.
869 val |= PCI_EXP_LNKCAP_DLLLARC;
871 return PCI_BRIDGE_EMUL_HANDLED;
874 case PCI_EXP_LNKCTL: {
875 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
876 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
877 ~(PCI_EXP_LNKSTA_LT << 16);
878 if (advk_pcie_link_training(pcie))
879 val |= (PCI_EXP_LNKSTA_LT << 16);
880 if (advk_pcie_link_active(pcie))
881 val |= (PCI_EXP_LNKSTA_DLLLA << 16);
883 return PCI_BRIDGE_EMUL_HANDLED;
888 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
889 return PCI_BRIDGE_EMUL_HANDLED;
891 return PCI_BRIDGE_EMUL_NOT_HANDLED;
897 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
898 int reg, u32 old, u32 new, u32 mask)
900 struct advk_pcie *pcie = bridge->data;
904 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
908 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
909 if (new & PCI_EXP_LNKCTL_RL)
910 advk_pcie_wait_for_retrain(pcie);
913 case PCI_EXP_RTCTL: {
914 /* Only mask/unmask PME interrupt */
915 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
916 ~PCIE_MSG_PM_PME_MASK;
917 if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
918 val |= PCIE_MSG_PM_PME_MASK;
919 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
924 new = (new & PCI_EXP_RTSTA_PME) >> 9;
925 advk_writel(pcie, new, PCIE_ISR0_REG);
933 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
934 .read_base = advk_pci_bridge_emul_base_conf_read,
935 .write_base = advk_pci_bridge_emul_base_conf_write,
936 .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
937 .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
941 * Initialize the configuration space of the PCI-to-PCI bridge
942 * associated with the given PCIe interface.
944 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
946 struct pci_bridge_emul *bridge = &pcie->bridge;
948 bridge->conf.vendor =
949 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
950 bridge->conf.device =
951 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
952 bridge->conf.class_revision =
953 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
955 /* Support 32 bits I/O addressing */
956 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
957 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
959 /* Support 64 bits memory pref */
960 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
961 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
963 /* Support interrupt A for MSI feature */
964 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
966 /* Aardvark HW provides PCIe Capability structure in version 2 */
967 bridge->pcie_conf.cap = cpu_to_le16(2);
969 /* Indicates supports for Completion Retry Status */
970 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);
972 bridge->has_pcie = true;
974 bridge->ops = &advk_pci_bridge_emul_ops;
976 return pci_bridge_emul_init(bridge, 0);
979 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
982 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0)
986 * If the link goes down after we check for link-up, nothing bad
987 * happens but the config access times out.
989 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
995 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
997 struct device *dev = &pcie->pdev->dev;
1000 * Trying to start a new PIO transfer when previous has not completed
1001 * cause External Abort on CPU which results in kernel panic:
1003 * SError Interrupt on CPU0, code 0xbf000002 -- SError
1004 * Kernel panic - not syncing: Asynchronous SError Interrupt
1006 * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected
1007 * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent
1008 * concurrent calls at the same time. But because PIO transfer may take
1009 * about 1.5s when link is down or card is disconnected, it means that
1010 * advk_pcie_wait_pio() does not always have to wait for completion.
1012 * Some versions of ARM Trusted Firmware handles this External Abort at
1013 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:
1014 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
1016 if (advk_readl(pcie, PIO_START)) {
1017 dev_err(dev, "Previous PIO read/write transfer is still running\n");
1024 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
1025 int where, int size, u32 *val)
1027 struct advk_pcie *pcie = bus->sysdata;
1033 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
1035 return PCIBIOS_DEVICE_NOT_FOUND;
1038 if (pci_is_root_bus(bus))
1039 return pci_bridge_emul_conf_read(&pcie->bridge, where,
1043 * Completion Retry Status is possible to return only when reading all
1044 * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and
1045 * CRSSVE flag on Root Bridge is enabled.
1047 allow_crs = (where == PCI_VENDOR_ID) && (size == 4) &&
1048 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) &
1049 PCI_EXP_RTCTL_CRSSVE);
1051 if (advk_pcie_pio_is_running(pcie))
1054 /* Program the control register */
1055 reg = advk_readl(pcie, PIO_CTRL);
1056 reg &= ~PIO_CTRL_TYPE_MASK;
1057 if (pci_is_root_bus(bus->parent))
1058 reg |= PCIE_CONFIG_RD_TYPE0;
1060 reg |= PCIE_CONFIG_RD_TYPE1;
1061 advk_writel(pcie, reg, PIO_CTRL);
1063 /* Program the address registers */
1064 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
1065 advk_writel(pcie, reg, PIO_ADDR_LS);
1066 advk_writel(pcie, 0, PIO_ADDR_MS);
1068 /* Program the data strobe */
1069 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
1073 /* Clear PIO DONE ISR and start the transfer */
1074 advk_writel(pcie, 1, PIO_ISR);
1075 advk_writel(pcie, 1, PIO_START);
1077 ret = advk_pcie_wait_pio(pcie);
1083 /* Check PIO status and get the read result */
1084 ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
1085 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
1091 *val = (*val >> (8 * (where & 3))) & 0xff;
1093 *val = (*val >> (8 * (where & 3))) & 0xffff;
1095 return PCIBIOS_SUCCESSFUL;
1099 * If it is possible, return Completion Retry Status so that caller
1100 * tries to issue the request again instead of failing.
1103 *val = CFG_RD_CRS_VAL;
1104 return PCIBIOS_SUCCESSFUL;
1109 return PCIBIOS_SET_FAILED;
1112 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
1113 int where, int size, u32 val)
1115 struct advk_pcie *pcie = bus->sysdata;
1117 u32 data_strobe = 0x0;
1122 if (!advk_pcie_valid_device(pcie, bus, devfn))
1123 return PCIBIOS_DEVICE_NOT_FOUND;
1125 if (pci_is_root_bus(bus))
1126 return pci_bridge_emul_conf_write(&pcie->bridge, where,
1130 return PCIBIOS_SET_FAILED;
1132 if (advk_pcie_pio_is_running(pcie))
1133 return PCIBIOS_SET_FAILED;
1135 /* Program the control register */
1136 reg = advk_readl(pcie, PIO_CTRL);
1137 reg &= ~PIO_CTRL_TYPE_MASK;
1138 if (pci_is_root_bus(bus->parent))
1139 reg |= PCIE_CONFIG_WR_TYPE0;
1141 reg |= PCIE_CONFIG_WR_TYPE1;
1142 advk_writel(pcie, reg, PIO_CTRL);
1144 /* Program the address registers */
1145 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
1146 advk_writel(pcie, reg, PIO_ADDR_LS);
1147 advk_writel(pcie, 0, PIO_ADDR_MS);
1149 /* Calculate the write strobe */
1150 offset = where & 0x3;
1151 reg = val << (8 * offset);
1152 data_strobe = GENMASK(size - 1, 0) << offset;
1154 /* Program the data register */
1155 advk_writel(pcie, reg, PIO_WR_DATA);
1157 /* Program the data strobe */
1158 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
1162 /* Clear PIO DONE ISR and start the transfer */
1163 advk_writel(pcie, 1, PIO_ISR);
1164 advk_writel(pcie, 1, PIO_START);
1166 ret = advk_pcie_wait_pio(pcie);
1168 return PCIBIOS_SET_FAILED;
1172 ret = advk_pcie_check_pio_status(pcie, false, NULL);
1173 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
1175 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
1178 static struct pci_ops advk_pcie_ops = {
1179 .read = advk_pcie_rd_conf,
1180 .write = advk_pcie_wr_conf,
1183 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
1184 struct msi_msg *msg)
1186 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
1187 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
1189 msg->address_lo = lower_32_bits(msi_msg);
1190 msg->address_hi = upper_32_bits(msi_msg);
1191 msg->data = data->hwirq;
1194 static int advk_msi_set_affinity(struct irq_data *irq_data,
1195 const struct cpumask *mask, bool force)
1200 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
1202 unsigned int nr_irqs, void *args)
1204 struct advk_pcie *pcie = domain->host_data;
1207 mutex_lock(&pcie->msi_used_lock);
1208 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM,
1209 order_base_2(nr_irqs));
1210 mutex_unlock(&pcie->msi_used_lock);
1214 for (i = 0; i < nr_irqs; i++)
1215 irq_domain_set_info(domain, virq + i, hwirq + i,
1216 &pcie->msi_bottom_irq_chip,
1217 domain->host_data, handle_simple_irq,
1223 static void advk_msi_irq_domain_free(struct irq_domain *domain,
1224 unsigned int virq, unsigned int nr_irqs)
1226 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1227 struct advk_pcie *pcie = domain->host_data;
1229 mutex_lock(&pcie->msi_used_lock);
1230 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs));
1231 mutex_unlock(&pcie->msi_used_lock);
1234 static const struct irq_domain_ops advk_msi_domain_ops = {
1235 .alloc = advk_msi_irq_domain_alloc,
1236 .free = advk_msi_irq_domain_free,
1239 static void advk_pcie_irq_mask(struct irq_data *d)
1241 struct advk_pcie *pcie = d->domain->host_data;
1242 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1243 unsigned long flags;
1246 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
1247 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1248 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
1249 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1250 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
1253 static void advk_pcie_irq_unmask(struct irq_data *d)
1255 struct advk_pcie *pcie = d->domain->host_data;
1256 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1257 unsigned long flags;
1260 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
1261 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1262 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
1263 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1264 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
1267 static int advk_pcie_irq_map(struct irq_domain *h,
1268 unsigned int virq, irq_hw_number_t hwirq)
1270 struct advk_pcie *pcie = h->host_data;
1272 advk_pcie_irq_mask(irq_get_irq_data(virq));
1273 irq_set_status_flags(virq, IRQ_LEVEL);
1274 irq_set_chip_and_handler(virq, &pcie->irq_chip,
1276 irq_set_chip_data(virq, pcie);
1281 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
1282 .map = advk_pcie_irq_map,
1283 .xlate = irq_domain_xlate_onecell,
1286 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
1288 struct device *dev = &pcie->pdev->dev;
1289 struct device_node *node = dev->of_node;
1290 struct irq_chip *bottom_ic, *msi_ic;
1291 struct msi_domain_info *msi_di;
1292 phys_addr_t msi_msg_phys;
1294 mutex_init(&pcie->msi_used_lock);
1296 bottom_ic = &pcie->msi_bottom_irq_chip;
1298 bottom_ic->name = "MSI";
1299 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
1300 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
1302 msi_ic = &pcie->msi_irq_chip;
1303 msi_ic->name = "advk-MSI";
1305 msi_di = &pcie->msi_domain_info;
1306 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
1307 MSI_FLAG_MULTI_PCI_MSI;
1308 msi_di->chip = msi_ic;
1310 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
1312 advk_writel(pcie, lower_32_bits(msi_msg_phys),
1313 PCIE_MSI_ADDR_LOW_REG);
1314 advk_writel(pcie, upper_32_bits(msi_msg_phys),
1315 PCIE_MSI_ADDR_HIGH_REG);
1317 pcie->msi_inner_domain =
1318 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
1319 &advk_msi_domain_ops, pcie);
1320 if (!pcie->msi_inner_domain)
1324 pci_msi_create_irq_domain(of_node_to_fwnode(node),
1325 msi_di, pcie->msi_inner_domain);
1326 if (!pcie->msi_domain) {
1327 irq_domain_remove(pcie->msi_inner_domain);
1334 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
1336 irq_domain_remove(pcie->msi_domain);
1337 irq_domain_remove(pcie->msi_inner_domain);
1340 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
1342 struct device *dev = &pcie->pdev->dev;
1343 struct device_node *node = dev->of_node;
1344 struct device_node *pcie_intc_node;
1345 struct irq_chip *irq_chip;
1348 raw_spin_lock_init(&pcie->irq_lock);
1350 pcie_intc_node = of_get_next_child(node, NULL);
1351 if (!pcie_intc_node) {
1352 dev_err(dev, "No PCIe Intc node found\n");
1356 irq_chip = &pcie->irq_chip;
1358 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
1360 if (!irq_chip->name) {
1365 irq_chip->irq_mask = advk_pcie_irq_mask;
1366 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
1367 irq_chip->irq_unmask = advk_pcie_irq_unmask;
1370 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
1371 &advk_pcie_irq_domain_ops, pcie);
1372 if (!pcie->irq_domain) {
1373 dev_err(dev, "Failed to get a INTx IRQ domain\n");
1379 of_node_put(pcie_intc_node);
1383 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
1385 irq_domain_remove(pcie->irq_domain);
1388 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
1390 u32 msi_val, msi_mask, msi_status, msi_idx;
1393 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1394 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
1395 msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
1397 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
1398 if (!(BIT(msi_idx) & msi_status))
1401 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
1402 virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);
1403 generic_handle_irq(virq);
1406 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
1410 static void advk_pcie_handle_int(struct advk_pcie *pcie)
1412 u32 isr0_val, isr0_mask, isr0_status;
1413 u32 isr1_val, isr1_mask, isr1_status;
1416 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1417 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1418 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
1420 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1421 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1422 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
1424 /* Process MSI interrupts */
1425 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1426 advk_pcie_handle_msi(pcie);
1428 /* Process legacy interrupts */
1429 for (i = 0; i < PCI_NUM_INTX; i++) {
1430 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1433 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1436 virq = irq_find_mapping(pcie->irq_domain, i);
1437 generic_handle_irq(virq);
1441 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
1443 struct advk_pcie *pcie = arg;
1446 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1447 if (!(status & PCIE_IRQ_CORE_INT))
1450 advk_pcie_handle_int(pcie);
1452 /* Clear interrupt */
1453 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1458 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
1460 phy_power_off(pcie->phy);
1461 phy_exit(pcie->phy);
1464 static int advk_pcie_enable_phy(struct advk_pcie *pcie)
1471 ret = phy_init(pcie->phy);
1475 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
1477 phy_exit(pcie->phy);
1481 ret = phy_power_on(pcie->phy);
1482 if (ret == -EOPNOTSUPP) {
1483 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n");
1485 phy_exit(pcie->phy);
1492 static int advk_pcie_setup_phy(struct advk_pcie *pcie)
1494 struct device *dev = &pcie->pdev->dev;
1495 struct device_node *node = dev->of_node;
1498 pcie->phy = devm_of_phy_get(dev, node, NULL);
1499 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
1500 return PTR_ERR(pcie->phy);
1502 /* Old bindings miss the PHY handle */
1503 if (IS_ERR(pcie->phy)) {
1504 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
1509 ret = advk_pcie_enable_phy(pcie);
1511 dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
1516 static int advk_pcie_probe(struct platform_device *pdev)
1518 struct device *dev = &pdev->dev;
1519 struct advk_pcie *pcie;
1520 struct pci_host_bridge *bridge;
1521 struct resource_entry *entry;
1524 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1528 pcie = pci_host_bridge_priv(bridge);
1530 platform_set_drvdata(pdev, pcie);
1532 resource_list_for_each_entry(entry, &bridge->windows) {
1533 resource_size_t start = entry->res->start;
1534 resource_size_t size = resource_size(entry->res);
1535 unsigned long type = resource_type(entry->res);
1539 * Aardvark hardware allows to configure also PCIe window
1540 * for config type 0 and type 1 mapping, but driver uses
1541 * only PIO for issuing configuration transfers which does
1542 * not use PCIe window configuration.
1544 if (type != IORESOURCE_MEM && type != IORESOURCE_MEM_64 &&
1545 type != IORESOURCE_IO)
1549 * Skip transparent memory resources. Default outbound access
1550 * configuration is set to transparent memory access so it
1551 * does not need window configuration.
1553 if ((type == IORESOURCE_MEM || type == IORESOURCE_MEM_64) &&
1558 * The n-th PCIe window is configured by tuple (match, remap, mask)
1559 * and an access to address A uses this window if A matches the
1560 * match with given mask.
1561 * So every PCIe window size must be a power of two and every start
1562 * address must be aligned to window size. Minimal size is 64 KiB
1563 * because lower 16 bits of mask must be zero. Remapped address
1564 * may have set only bits from the mask.
1566 while (pcie->wins_count < OB_WIN_COUNT && size > 0) {
1567 /* Calculate the largest aligned window size */
1568 win_size = (1ULL << (fls64(size)-1)) |
1569 (start ? (1ULL << __ffs64(start)) : 0);
1570 win_size = 1ULL << __ffs64(win_size);
1571 if (win_size < 0x10000)
1575 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n",
1576 pcie->wins_count, (unsigned long long)start,
1577 (unsigned long long)start + win_size, type);
1579 if (type == IORESOURCE_IO) {
1580 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO;
1581 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start);
1583 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM;
1584 pcie->wins[pcie->wins_count].match = start;
1586 pcie->wins[pcie->wins_count].remap = start - entry->offset;
1587 pcie->wins[pcie->wins_count].mask = ~(win_size - 1);
1589 if (pcie->wins[pcie->wins_count].remap & (win_size - 1))
1598 dev_err(&pcie->pdev->dev,
1599 "Invalid PCIe region [0x%llx-0x%llx]\n",
1600 (unsigned long long)entry->res->start,
1601 (unsigned long long)entry->res->end + 1);
1606 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1607 if (IS_ERR(pcie->base))
1608 return PTR_ERR(pcie->base);
1610 irq = platform_get_irq(pdev, 0);
1614 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
1615 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1618 dev_err(dev, "Failed to register interrupt\n");
1622 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
1626 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1628 if (ret == -ENOENT) {
1629 pcie->reset_gpio = NULL;
1631 if (ret != -EPROBE_DEFER)
1632 dev_err(dev, "Failed to get reset-gpio: %i\n",
1638 ret = of_pci_get_max_link_speed(dev->of_node);
1639 if (ret <= 0 || ret > 3)
1642 pcie->link_gen = ret;
1644 ret = advk_pcie_setup_phy(pcie);
1648 advk_pcie_setup_hw(pcie);
1650 ret = advk_sw_pci_bridge_init(pcie);
1652 dev_err(dev, "Failed to register emulated root PCI bridge\n");
1656 ret = advk_pcie_init_irq_domain(pcie);
1658 dev_err(dev, "Failed to initialize irq\n");
1662 ret = advk_pcie_init_msi_irq_domain(pcie);
1664 dev_err(dev, "Failed to initialize irq\n");
1665 advk_pcie_remove_irq_domain(pcie);
1669 bridge->sysdata = pcie;
1670 bridge->ops = &advk_pcie_ops;
1672 ret = pci_host_probe(bridge);
1674 advk_pcie_remove_msi_irq_domain(pcie);
1675 advk_pcie_remove_irq_domain(pcie);
1682 static int advk_pcie_remove(struct platform_device *pdev)
1684 struct advk_pcie *pcie = platform_get_drvdata(pdev);
1685 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1688 pci_lock_rescan_remove();
1689 pci_stop_root_bus(bridge->bus);
1690 pci_remove_root_bus(bridge->bus);
1691 pci_unlock_rescan_remove();
1693 advk_pcie_remove_msi_irq_domain(pcie);
1694 advk_pcie_remove_irq_domain(pcie);
1696 /* Disable outbound address windows mapping */
1697 for (i = 0; i < OB_WIN_COUNT; i++)
1698 advk_pcie_disable_ob_win(pcie, i);
1703 static const struct of_device_id advk_pcie_of_match_table[] = {
1704 { .compatible = "marvell,armada-3700-pcie", },
1707 MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table);
1709 static struct platform_driver advk_pcie_driver = {
1711 .name = "advk-pcie",
1712 .of_match_table = advk_pcie_of_match_table,
1714 .probe = advk_pcie_probe,
1715 .remove = advk_pcie_remove,
1717 module_platform_driver(advk_pcie_driver);
1719 MODULE_DESCRIPTION("Aardvark PCIe controller");
1720 MODULE_LICENSE("GPL v2");