1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra194 SoC
5 * Copyright (C) 2019 NVIDIA Corporation.
7 * Author: Vidya Sagar <vidyas@nvidia.com>
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/phy/phy.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/random.h>
30 #include <linux/reset.h>
31 #include <linux/resource.h>
32 #include <linux/types.h>
33 #include "pcie-designware.h"
34 #include <soc/tegra/bpmp.h>
35 #include <soc/tegra/bpmp-abi.h>
36 #include "../../pci.h"
38 #define APPL_PINMUX 0x0
39 #define APPL_PINMUX_PEX_RST BIT(0)
40 #define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2)
41 #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3)
42 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4)
43 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5)
46 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6)
47 #define APPL_CTRL_LTSSM_EN BIT(7)
48 #define APPL_CTRL_HW_HOT_RST_EN BIT(20)
49 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
50 #define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22
51 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
53 #define APPL_INTR_EN_L0_0 0x8
54 #define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0)
55 #define APPL_INTR_EN_L0_0_MSI_RCV_INT_EN BIT(4)
56 #define APPL_INTR_EN_L0_0_INT_INT_EN BIT(8)
57 #define APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN BIT(15)
58 #define APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN BIT(19)
59 #define APPL_INTR_EN_L0_0_SYS_INTR_EN BIT(30)
60 #define APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN BIT(31)
62 #define APPL_INTR_STATUS_L0 0xC
63 #define APPL_INTR_STATUS_L0_LINK_STATE_INT BIT(0)
64 #define APPL_INTR_STATUS_L0_INT_INT BIT(8)
65 #define APPL_INTR_STATUS_L0_PCI_CMD_EN_INT BIT(15)
66 #define APPL_INTR_STATUS_L0_PEX_RST_INT BIT(16)
67 #define APPL_INTR_STATUS_L0_CDM_REG_CHK_INT BIT(18)
69 #define APPL_INTR_EN_L1_0_0 0x1C
70 #define APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN BIT(1)
71 #define APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN BIT(3)
72 #define APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN BIT(30)
74 #define APPL_INTR_STATUS_L1_0_0 0x20
75 #define APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED BIT(1)
76 #define APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED BIT(3)
77 #define APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE BIT(30)
79 #define APPL_INTR_STATUS_L1_1 0x2C
80 #define APPL_INTR_STATUS_L1_2 0x30
81 #define APPL_INTR_STATUS_L1_3 0x34
82 #define APPL_INTR_STATUS_L1_6 0x3C
83 #define APPL_INTR_STATUS_L1_7 0x40
84 #define APPL_INTR_STATUS_L1_15_CFG_BME_CHGED BIT(1)
86 #define APPL_INTR_EN_L1_8_0 0x44
87 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2)
88 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3)
89 #define APPL_INTR_EN_L1_8_INTX_EN BIT(11)
90 #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15)
92 #define APPL_INTR_STATUS_L1_8_0 0x4C
93 #define APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK GENMASK(11, 6)
94 #define APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS BIT(2)
95 #define APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS BIT(3)
97 #define APPL_INTR_STATUS_L1_9 0x54
98 #define APPL_INTR_STATUS_L1_10 0x58
99 #define APPL_INTR_STATUS_L1_11 0x64
100 #define APPL_INTR_STATUS_L1_13 0x74
101 #define APPL_INTR_STATUS_L1_14 0x78
102 #define APPL_INTR_STATUS_L1_15 0x7C
103 #define APPL_INTR_STATUS_L1_17 0x88
105 #define APPL_INTR_EN_L1_18 0x90
106 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMPLT BIT(2)
107 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
108 #define APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
110 #define APPL_INTR_STATUS_L1_18 0x94
111 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT BIT(2)
112 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR BIT(1)
113 #define APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR BIT(0)
115 #define APPL_MSI_CTRL_1 0xAC
117 #define APPL_MSI_CTRL_2 0xB0
119 #define APPL_LEGACY_INTX 0xB8
121 #define APPL_LTR_MSG_1 0xC4
122 #define LTR_MSG_REQ BIT(15)
123 #define LTR_MST_NO_SNOOP_SHIFT 16
125 #define APPL_LTR_MSG_2 0xC8
126 #define APPL_LTR_MSG_2_LTR_MSG_REQ_STATE BIT(3)
128 #define APPL_LINK_STATUS 0xCC
129 #define APPL_LINK_STATUS_RDLH_LINK_UP BIT(0)
131 #define APPL_DEBUG 0xD0
132 #define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21)
133 #define APPL_DEBUG_PM_LINKST_IN_L0 0x11
134 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)
135 #define APPL_DEBUG_LTSSM_STATE_SHIFT 3
136 #define LTSSM_STATE_PRE_DETECT 5
138 #define APPL_RADM_STATUS 0xE4
139 #define APPL_PM_XMT_TURNOFF_STATE BIT(0)
141 #define APPL_DM_TYPE 0x100
142 #define APPL_DM_TYPE_MASK GENMASK(3, 0)
143 #define APPL_DM_TYPE_RP 0x4
144 #define APPL_DM_TYPE_EP 0x0
146 #define APPL_CFG_BASE_ADDR 0x104
147 #define APPL_CFG_BASE_ADDR_MASK GENMASK(31, 12)
149 #define APPL_CFG_IATU_DMA_BASE_ADDR 0x108
150 #define APPL_CFG_IATU_DMA_BASE_ADDR_MASK GENMASK(31, 18)
152 #define APPL_CFG_MISC 0x110
153 #define APPL_CFG_MISC_SLV_EP_MODE BIT(14)
154 #define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10)
155 #define APPL_CFG_MISC_ARCACHE_SHIFT 10
156 #define APPL_CFG_MISC_ARCACHE_VAL 3
158 #define APPL_CFG_SLCG_OVERRIDE 0x114
159 #define APPL_CFG_SLCG_OVERRIDE_SLCG_EN_MASTER BIT(0)
161 #define APPL_CAR_RESET_OVRD 0x12C
162 #define APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N BIT(0)
164 #define IO_BASE_IO_DECODE BIT(0)
165 #define IO_BASE_IO_DECODE_BIT8 BIT(8)
167 #define CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE BIT(0)
168 #define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16)
170 #define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718
171 #define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19)
173 #define EVENT_COUNTER_ALL_CLEAR 0x3
174 #define EVENT_COUNTER_ENABLE_ALL 0x7
175 #define EVENT_COUNTER_ENABLE_SHIFT 2
176 #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
177 #define EVENT_COUNTER_EVENT_SEL_SHIFT 16
178 #define EVENT_COUNTER_EVENT_Tx_L0S 0x2
179 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3
180 #define EVENT_COUNTER_EVENT_L1 0x5
181 #define EVENT_COUNTER_EVENT_L1_1 0x7
182 #define EVENT_COUNTER_EVENT_L1_2 0x8
183 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24
184 #define EVENT_COUNTER_GROUP_5 0x5
189 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
191 #define GEN3_EQ_CONTROL_OFF 0x8a8
192 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8
193 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
194 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
196 #define GEN3_RELATED_OFF 0x890
197 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
198 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
199 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
200 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
202 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
203 #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
204 #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
205 #define AMBA_ERROR_RESPONSE_CRS_OKAY 0
206 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1
207 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2
209 #define MSIX_ADDR_MATCH_LOW_OFF 0x940
210 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0)
211 #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2)
213 #define MSIX_ADDR_MATCH_HIGH_OFF 0x944
214 #define MSIX_ADDR_MATCH_HIGH_OFF_MASK GENMASK(31, 0)
216 #define PORT_LOGIC_MSIX_DOORBELL 0x948
218 #define CAP_SPCIE_CAP_OFF 0x154
219 #define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0)
220 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8)
221 #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8
223 #define PME_ACK_TIMEOUT 10000
225 #define LTSSM_TIMEOUT 50000 /* 50ms */
227 #define GEN3_GEN4_EQ_PRESET_INIT 5
229 #define GEN1_CORE_CLK_FREQ 62500000
230 #define GEN2_CORE_CLK_FREQ 125000000
231 #define GEN3_CORE_CLK_FREQ 250000000
232 #define GEN4_CORE_CLK_FREQ 500000000
234 #define LTR_MSG_TIMEOUT (100 * 1000)
236 #define PERST_DEBOUNCE_TIME (5 * 1000)
238 #define EP_STATE_DISABLED 0
239 #define EP_STATE_ENABLED 1
241 static const unsigned int pcie_gen_freq[] = {
248 static const u32 event_cntr_ctrl_offset[] = {
257 static const u32 event_cntr_data_offset[] = {
266 struct tegra_pcie_dw {
268 struct resource *appl_res;
269 struct resource *dbi_res;
270 struct resource *atu_dma_res;
271 void __iomem *appl_base;
272 struct clk *core_clk;
273 struct reset_control *core_apb_rst;
274 struct reset_control *core_rst;
276 struct tegra_bpmp *bpmp;
278 enum dw_pcie_device_mode mode;
280 bool supports_clkreq;
281 bool enable_cdm_check;
283 bool update_fc_fixup;
288 u32 cfg_link_cap_l1sub;
292 u32 aspm_l0s_enter_lat;
294 struct regulator *pex_ctl_supply;
295 struct regulator *slot_ctl_3v3;
296 struct regulator *slot_ctl_12v;
298 unsigned int phy_count;
301 struct dentry *debugfs;
303 /* Endpoint mode specific */
304 struct gpio_desc *pex_rst_gpiod;
305 struct gpio_desc *pex_refclk_sel_gpiod;
306 unsigned int pex_rst_irq;
310 struct tegra_pcie_dw_of_data {
311 enum dw_pcie_device_mode mode;
314 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
316 return container_of(pci, struct tegra_pcie_dw, pci);
319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
322 writel_relaxed(value, pcie->appl_base + reg);
325 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
327 return readl_relaxed(pcie->appl_base + reg);
330 struct tegra_pcie_soc {
331 enum dw_pcie_device_mode mode;
334 static void apply_bad_link_workaround(struct pcie_port *pp)
336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
337 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
338 u32 current_link_width;
342 * NOTE:- Since this scenario is uncommon and link as such is not
343 * stable anyway, not waiting to confirm if link is really
344 * transitioning to Gen-2 speed
346 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
347 if (val & PCI_EXP_LNKSTA_LBMS) {
348 current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
349 PCI_EXP_LNKSTA_NLW_SHIFT;
350 if (pcie->init_link_width > current_link_width) {
351 dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
352 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
354 val &= ~PCI_EXP_LNKCTL2_TLS;
355 val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
356 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
357 PCI_EXP_LNKCTL2, val);
359 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
361 val |= PCI_EXP_LNKCTL_RL;
362 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
363 PCI_EXP_LNKCTL, val);
368 static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
370 struct tegra_pcie_dw *pcie = arg;
371 struct dw_pcie *pci = &pcie->pci;
372 struct pcie_port *pp = &pci->pp;
373 u32 val, status_l0, status_l1;
376 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
377 if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
378 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
379 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
380 if (status_l1 & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
381 /* SBR & Surprise Link Down WAR */
382 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
383 val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
384 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
386 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
387 val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
388 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
390 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
391 val |= PORT_LOGIC_SPEED_CHANGE;
392 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
396 if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
397 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
398 if (status_l1 & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
400 APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
401 APPL_INTR_STATUS_L1_8_0);
402 apply_bad_link_workaround(pp);
404 if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
406 APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
407 APPL_INTR_STATUS_L1_8_0);
409 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
411 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w &
416 if (status_l0 & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
417 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
418 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
419 if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
420 dev_info(pci->dev, "CDM check complete\n");
421 val |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
423 if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
424 dev_err(pci->dev, "CDM comparison mismatch\n");
425 val |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
427 if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
428 dev_err(pci->dev, "CDM Logic error\n");
429 val |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
431 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
432 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
433 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val);
439 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
443 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
444 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
458 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);
460 val = appl_readl(pcie, APPL_CTRL);
461 val |= APPL_CTRL_LTSSM_EN;
462 appl_writel(pcie, val, APPL_CTRL);
465 static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
467 struct tegra_pcie_dw *pcie = arg;
468 struct dw_pcie *pci = &pcie->pci;
471 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
473 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
475 /* If EP doesn't advertise L1SS, just return */
476 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
477 if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2)))
480 /* Check if BME is set to '1' */
481 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
482 if (val & PCI_COMMAND_MASTER) {
485 /* 110us for both snoop and no-snoop */
486 val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;
487 val |= (val << LTR_MST_NO_SNOOP_SHIFT);
488 appl_writel(pcie, val, APPL_LTR_MSG_1);
490 /* Send LTR upstream */
491 val = appl_readl(pcie, APPL_LTR_MSG_2);
492 val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
493 appl_writel(pcie, val, APPL_LTR_MSG_2);
495 timeout = ktime_add_us(ktime_get(), LTR_MSG_TIMEOUT);
497 val = appl_readl(pcie, APPL_LTR_MSG_2);
498 if (!(val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE))
500 if (ktime_after(ktime_get(), timeout))
502 usleep_range(1000, 1100);
504 if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE)
505 dev_err(pcie->dev, "Failed to send LTR message\n");
511 static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
513 struct tegra_pcie_dw *pcie = arg;
514 struct dw_pcie_ep *ep = &pcie->pci.ep;
516 u32 status_l0, status_l1, link_status;
518 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
519 if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
520 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
521 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
523 if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
524 pex_ep_event_hot_rst_done(pcie);
526 if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
527 link_status = appl_readl(pcie, APPL_LINK_STATUS);
528 if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) {
529 dev_dbg(pcie->dev, "Link is up with Host\n");
530 dw_pcie_ep_linkup(ep);
537 if (status_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
538 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
539 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
541 if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
542 return IRQ_WAKE_THREAD;
548 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
550 appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
556 static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
560 * This is an endpoint mode specific register happen to appear even
561 * when controller is operating in root port mode and system hangs
562 * when it is accessed with link being in ASPM-L1 state.
563 * So skip accessing it altogether
565 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) {
567 return PCIBIOS_SUCCESSFUL;
570 return pci_generic_config_read(bus, devfn, where, size, val);
573 static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
577 * This is an endpoint mode specific register happen to appear even
578 * when controller is operating in root port mode and system hangs
579 * when it is accessed with link being in ASPM-L1 state.
580 * So skip accessing it altogether
582 if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL)
583 return PCIBIOS_SUCCESSFUL;
585 return pci_generic_config_write(bus, devfn, where, size, val);
588 static struct pci_ops tegra_pci_ops = {
589 .map_bus = dw_pcie_own_conf_map_bus,
590 .read = tegra_pcie_dw_rd_own_conf,
591 .write = tegra_pcie_dw_wr_own_conf,
594 #if defined(CONFIG_PCIEASPM)
595 static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
599 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
600 val &= ~PCI_L1SS_CAP_ASPM_L1_1;
601 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
604 static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
608 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
609 val &= ~PCI_L1SS_CAP_ASPM_L1_2;
610 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
613 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
617 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
618 val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
619 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
620 val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
621 val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
622 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
623 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
628 static int aspm_state_cnt(struct seq_file *s, void *data)
630 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
631 dev_get_drvdata(s->private);
634 seq_printf(s, "Tx L0s entry count : %u\n",
635 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
637 seq_printf(s, "Rx L0s entry count : %u\n",
638 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
640 seq_printf(s, "Link L1 entry count : %u\n",
641 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
643 seq_printf(s, "Link L1.1 entry count : %u\n",
644 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
646 seq_printf(s, "Link L1.2 entry count : %u\n",
647 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
649 /* Clear all counters */
650 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
651 EVENT_COUNTER_ALL_CLEAR);
653 /* Re-enable counting */
654 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
655 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
656 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
661 static void init_host_aspm(struct tegra_pcie_dw *pcie)
663 struct dw_pcie *pci = &pcie->pci;
666 val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
667 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
669 /* Enable ASPM counters */
670 val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
671 val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
672 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
674 /* Program T_cmrt and T_pwr_on values */
675 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
676 val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
677 val |= (pcie->aspm_cmrt << 8);
678 val |= (pcie->aspm_pwr_on_t << 19);
679 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
681 /* Program L0s and L1 entrance latencies */
682 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
683 val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
684 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
685 val |= PORT_AFR_ENTER_ASPM;
686 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
689 static void init_debugfs(struct tegra_pcie_dw *pcie)
691 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
695 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
696 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
697 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
698 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
701 static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
703 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
704 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
708 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
709 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
710 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
712 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
713 val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
714 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
716 if (pcie->enable_cdm_check) {
717 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
718 val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
719 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
721 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
722 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
723 val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
724 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
727 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
729 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
730 PCI_EXP_LNKSTA_NLW_SHIFT;
732 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
734 val_w |= PCI_EXP_LNKCTL_LBMIE;
735 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
739 static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
741 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
742 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
745 /* Enable legacy interrupt generation */
746 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
747 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
748 val |= APPL_INTR_EN_L0_0_INT_INT_EN;
749 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
751 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
752 val |= APPL_INTR_EN_L1_8_INTX_EN;
753 val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
754 val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
755 if (IS_ENABLED(CONFIG_PCIEAER))
756 val |= APPL_INTR_EN_L1_8_AER_INT_EN;
757 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
760 static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
762 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
763 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
766 dw_pcie_msi_init(pp);
768 /* Enable MSI interrupt generation */
769 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
770 val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
771 val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
772 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
775 static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
777 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
778 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
780 /* Clear interrupt statuses before enabling interrupts */
781 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
782 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
797 tegra_pcie_enable_system_interrupts(pp);
798 tegra_pcie_enable_legacy_interrupts(pp);
799 if (IS_ENABLED(CONFIG_PCI_MSI))
800 tegra_pcie_enable_msi_interrupts(pp);
803 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
805 struct dw_pcie *pci = &pcie->pci;
808 /* Program init preset */
809 for (i = 0; i < pcie->num_lanes; i++) {
810 val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));
811 val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
812 val |= GEN3_GEN4_EQ_PRESET_INIT;
813 val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
814 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
815 CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
816 dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);
818 offset = dw_pcie_find_ext_capability(pci,
819 PCI_EXT_CAP_ID_PL_16GT) +
821 val = dw_pcie_readb_dbi(pci, offset + i);
822 val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
823 val |= GEN3_GEN4_EQ_PRESET_INIT;
824 val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
825 val |= (GEN3_GEN4_EQ_PRESET_INIT <<
826 PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
827 dw_pcie_writeb_dbi(pci, offset + i, val);
830 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
831 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
832 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
834 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
835 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
836 val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
837 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
838 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
840 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
841 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
842 val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
843 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
845 val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
846 val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
847 val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
848 val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
849 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
851 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
852 val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
853 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
856 static void tegra_pcie_prepare_host(struct pcie_port *pp)
858 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
859 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
862 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
863 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
864 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
866 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
867 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
868 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
869 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
871 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
873 /* Enable as 0xFFFF0001 response for CRS */
874 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
875 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
876 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
877 AMBA_ERROR_RESPONSE_CRS_SHIFT);
878 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
880 /* Configure Max lane width from DT */
881 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
882 val &= ~PCI_EXP_LNKCAP_MLW;
883 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
884 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
886 config_gen3_gen4_eq_presets(pcie);
888 init_host_aspm(pcie);
890 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
891 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
892 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
894 if (pcie->update_fc_fixup) {
895 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
896 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
897 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
900 dw_pcie_setup_rc(pp);
902 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
905 val = appl_readl(pcie, APPL_PINMUX);
906 val &= ~APPL_PINMUX_PEX_RST;
907 appl_writel(pcie, val, APPL_PINMUX);
909 usleep_range(100, 200);
912 val = appl_readl(pcie, APPL_CTRL);
913 val |= APPL_CTRL_LTSSM_EN;
914 appl_writel(pcie, val, APPL_CTRL);
917 val = appl_readl(pcie, APPL_PINMUX);
918 val |= APPL_PINMUX_PEX_RST;
919 appl_writel(pcie, val, APPL_PINMUX);
924 static int tegra_pcie_dw_host_init(struct pcie_port *pp)
926 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
927 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
928 u32 val, tmp, offset, speed;
930 pp->bridge->ops = &tegra_pci_ops;
932 tegra_pcie_prepare_host(pp);
934 if (dw_pcie_wait_for_link(pci)) {
936 * There are some endpoints which can't get the link up if
937 * root port has Data Link Feature (DLF) enabled.
938 * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info
939 * on Scaled Flow Control and DLF.
940 * So, need to confirm that is indeed the case here and attempt
941 * link up once again with DLF disabled.
943 val = appl_readl(pcie, APPL_DEBUG);
944 val &= APPL_DEBUG_LTSSM_STATE_MASK;
945 val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
946 tmp = appl_readl(pcie, APPL_LINK_STATUS);
947 tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
948 if (!(val == 0x11 && !tmp)) {
949 /* Link is down for all good reasons */
953 dev_info(pci->dev, "Link is down in DLL");
954 dev_info(pci->dev, "Trying again with DLFE disabled\n");
956 val = appl_readl(pcie, APPL_CTRL);
957 val &= ~APPL_CTRL_LTSSM_EN;
958 appl_writel(pcie, val, APPL_CTRL);
960 reset_control_assert(pcie->core_rst);
961 reset_control_deassert(pcie->core_rst);
963 offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
964 val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
965 val &= ~PCI_DLF_EXCHANGE_ENABLE;
966 dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
968 tegra_pcie_prepare_host(pp);
970 if (dw_pcie_wait_for_link(pci))
974 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
976 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
978 tegra_pcie_enable_interrupts(pp);
983 static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
985 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
986 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
988 return !!(val & PCI_EXP_LNKSTA_DLLLA);
991 static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp)
993 pp->num_vectors = MAX_MSI_IRQS;
996 static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
998 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1000 enable_irq(pcie->pex_rst_irq);
1005 static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)
1007 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1009 disable_irq(pcie->pex_rst_irq);
1012 static const struct dw_pcie_ops tegra_dw_pcie_ops = {
1013 .link_up = tegra_pcie_dw_link_up,
1014 .start_link = tegra_pcie_dw_start_link,
1015 .stop_link = tegra_pcie_dw_stop_link,
1018 static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
1019 .host_init = tegra_pcie_dw_host_init,
1020 .set_num_vectors = tegra_pcie_set_msi_vec_num,
1023 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
1025 unsigned int phy_count = pcie->phy_count;
1027 while (phy_count--) {
1028 phy_power_off(pcie->phys[phy_count]);
1029 phy_exit(pcie->phys[phy_count]);
1033 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
1038 for (i = 0; i < pcie->phy_count; i++) {
1039 ret = phy_init(pcie->phys[i]);
1043 ret = phy_power_on(pcie->phys[i]);
1052 phy_power_off(pcie->phys[i]);
1054 phy_exit(pcie->phys[i]);
1060 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
1062 struct device_node *np = pcie->dev->of_node;
1065 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
1067 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
1071 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
1072 &pcie->aspm_pwr_on_t);
1074 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
1077 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
1078 &pcie->aspm_l0s_enter_lat);
1081 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
1083 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
1085 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
1089 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
1091 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
1095 ret = of_property_count_strings(np, "phy-names");
1097 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
1101 pcie->phy_count = ret;
1103 if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
1104 pcie->update_fc_fixup = true;
1106 pcie->supports_clkreq =
1107 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
1109 pcie->enable_cdm_check =
1110 of_property_read_bool(np, "snps,enable-cdm-check");
1112 if (pcie->mode == DW_PCIE_RC_TYPE)
1115 /* Endpoint mode specific DT entries */
1116 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN);
1117 if (IS_ERR(pcie->pex_rst_gpiod)) {
1118 int err = PTR_ERR(pcie->pex_rst_gpiod);
1119 const char *level = KERN_ERR;
1121 if (err == -EPROBE_DEFER)
1124 dev_printk(level, pcie->dev,
1125 dev_fmt("Failed to get PERST GPIO: %d\n"),
1130 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
1131 "nvidia,refclk-select",
1133 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
1134 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
1135 const char *level = KERN_ERR;
1137 if (err == -EPROBE_DEFER)
1140 dev_printk(level, pcie->dev,
1141 dev_fmt("Failed to get REFCLK select GPIOs: %d\n"),
1143 pcie->pex_refclk_sel_gpiod = NULL;
1149 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
1152 struct mrq_uphy_response resp;
1153 struct tegra_bpmp_message msg;
1154 struct mrq_uphy_request req;
1156 /* Controller-5 doesn't need to have its state set by BPMP-FW */
1160 memset(&req, 0, sizeof(req));
1161 memset(&resp, 0, sizeof(resp));
1163 req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
1164 req.controller_state.pcie_controller = pcie->cid;
1165 req.controller_state.enable = enable;
1167 memset(&msg, 0, sizeof(msg));
1170 msg.tx.size = sizeof(req);
1171 msg.rx.data = &resp;
1172 msg.rx.size = sizeof(resp);
1174 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1177 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
1180 struct mrq_uphy_response resp;
1181 struct tegra_bpmp_message msg;
1182 struct mrq_uphy_request req;
1184 memset(&req, 0, sizeof(req));
1185 memset(&resp, 0, sizeof(resp));
1188 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT;
1189 req.ep_ctrlr_pll_init.ep_controller = pcie->cid;
1191 req.cmd = CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF;
1192 req.ep_ctrlr_pll_off.ep_controller = pcie->cid;
1195 memset(&msg, 0, sizeof(msg));
1198 msg.tx.size = sizeof(req);
1199 msg.rx.data = &resp;
1200 msg.rx.size = sizeof(resp);
1202 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1205 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
1207 struct pcie_port *pp = &pcie->pci.pp;
1208 struct pci_bus *child, *root_bus = NULL;
1209 struct pci_dev *pdev;
1212 * link doesn't go into L2 state with some of the endpoints with Tegra
1213 * if they are not in D0 state. So, need to make sure that immediate
1214 * downstream devices are in D0 state before sending PME_TurnOff to put
1215 * link into L2 state.
1216 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
1217 * 5.2 Link State Power Management (Page #428).
1220 list_for_each_entry(child, &pp->bridge->bus->children, node) {
1221 /* Bring downstream devices to D0 if they are not already in */
1222 if (child->parent == pp->bridge->bus) {
1229 dev_err(pcie->dev, "Failed to find downstream devices\n");
1233 list_for_each_entry(pdev, &root_bus->devices, bus_list) {
1234 if (PCI_SLOT(pdev->devfn) == 0) {
1235 if (pci_set_power_state(pdev, PCI_D0))
1237 "Failed to transition %s to D0 state\n",
1238 dev_name(&pdev->dev));
1243 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
1245 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1246 if (IS_ERR(pcie->slot_ctl_3v3)) {
1247 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1248 return PTR_ERR(pcie->slot_ctl_3v3);
1250 pcie->slot_ctl_3v3 = NULL;
1253 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1254 if (IS_ERR(pcie->slot_ctl_12v)) {
1255 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1256 return PTR_ERR(pcie->slot_ctl_12v);
1258 pcie->slot_ctl_12v = NULL;
1264 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
1268 if (pcie->slot_ctl_3v3) {
1269 ret = regulator_enable(pcie->slot_ctl_3v3);
1272 "Failed to enable 3.3V slot supply: %d\n", ret);
1277 if (pcie->slot_ctl_12v) {
1278 ret = regulator_enable(pcie->slot_ctl_12v);
1281 "Failed to enable 12V slot supply: %d\n", ret);
1282 goto fail_12v_enable;
1287 * According to PCI Express Card Electromechanical Specification
1288 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive)
1289 * should be a minimum of 100ms.
1291 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1297 if (pcie->slot_ctl_3v3)
1298 regulator_disable(pcie->slot_ctl_3v3);
1302 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
1304 if (pcie->slot_ctl_12v)
1305 regulator_disable(pcie->slot_ctl_12v);
1306 if (pcie->slot_ctl_3v3)
1307 regulator_disable(pcie->slot_ctl_3v3);
1310 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
1316 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1319 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1323 ret = tegra_pcie_enable_slot_regulators(pcie);
1325 goto fail_slot_reg_en;
1327 ret = regulator_enable(pcie->pex_ctl_supply);
1329 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1333 ret = clk_prepare_enable(pcie->core_clk);
1335 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1339 ret = reset_control_deassert(pcie->core_apb_rst);
1341 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1343 goto fail_core_apb_rst;
1346 if (en_hw_hot_rst) {
1347 /* Enable HW_HOT_RST mode */
1348 val = appl_readl(pcie, APPL_CTRL);
1349 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
1350 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
1351 val |= APPL_CTRL_HW_HOT_RST_EN;
1352 appl_writel(pcie, val, APPL_CTRL);
1355 ret = tegra_pcie_enable_phy(pcie);
1357 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1361 /* Update CFG base address */
1362 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1363 APPL_CFG_BASE_ADDR);
1365 /* Configure this core for RP mode operation */
1366 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1368 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1370 val = appl_readl(pcie, APPL_CTRL);
1371 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1373 val = appl_readl(pcie, APPL_CFG_MISC);
1374 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1375 appl_writel(pcie, val, APPL_CFG_MISC);
1377 if (!pcie->supports_clkreq) {
1378 val = appl_readl(pcie, APPL_PINMUX);
1379 val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
1380 val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
1381 appl_writel(pcie, val, APPL_PINMUX);
1384 /* Update iATU_DMA base address */
1386 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1387 APPL_CFG_IATU_DMA_BASE_ADDR);
1389 reset_control_deassert(pcie->core_rst);
1391 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1394 /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */
1395 if (!pcie->supports_clkreq) {
1396 disable_aspm_l11(pcie);
1397 disable_aspm_l12(pcie);
1403 reset_control_assert(pcie->core_apb_rst);
1405 clk_disable_unprepare(pcie->core_clk);
1407 regulator_disable(pcie->pex_ctl_supply);
1409 tegra_pcie_disable_slot_regulators(pcie);
1411 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1416 static int __deinit_controller(struct tegra_pcie_dw *pcie)
1420 ret = reset_control_assert(pcie->core_rst);
1422 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n",
1427 tegra_pcie_disable_phy(pcie);
1429 ret = reset_control_assert(pcie->core_apb_rst);
1431 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1435 clk_disable_unprepare(pcie->core_clk);
1437 ret = regulator_disable(pcie->pex_ctl_supply);
1439 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1443 tegra_pcie_disable_slot_regulators(pcie);
1445 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1447 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1455 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
1457 struct dw_pcie *pci = &pcie->pci;
1458 struct pcie_port *pp = &pci->pp;
1461 ret = tegra_pcie_config_controller(pcie, false);
1465 pp->ops = &tegra_pcie_dw_host_ops;
1467 ret = dw_pcie_host_init(pp);
1469 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1470 goto fail_host_init;
1476 return __deinit_controller(pcie);
1479 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
1483 if (!tegra_pcie_dw_link_up(&pcie->pci))
1486 val = appl_readl(pcie, APPL_RADM_STATUS);
1487 val |= APPL_PM_XMT_TURNOFF_STATE;
1488 appl_writel(pcie, val, APPL_RADM_STATUS);
1490 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1491 val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
1492 1, PME_ACK_TIMEOUT);
1495 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
1500 if (!tegra_pcie_dw_link_up(&pcie->pci)) {
1501 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1505 if (tegra_pcie_try_link_l2(pcie)) {
1506 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1508 * TX lane clock freq will reset to Gen1 only if link is in L2
1510 * So apply pex_rst to end point to force RP to go into detect
1513 data = appl_readl(pcie, APPL_PINMUX);
1514 data &= ~APPL_PINMUX_PEX_RST;
1515 appl_writel(pcie, data, APPL_PINMUX);
1517 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1520 APPL_DEBUG_LTSSM_STATE_MASK) >>
1521 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1522 LTSSM_STATE_PRE_DETECT,
1525 dev_info(pcie->dev, "Link didn't go to detect state\n");
1527 /* Disable LTSSM after link is in detect state */
1528 data = appl_readl(pcie, APPL_CTRL);
1529 data &= ~APPL_CTRL_LTSSM_EN;
1530 appl_writel(pcie, data, APPL_CTRL);
1534 * DBI registers may not be accessible after this as PLL-E would be
1535 * down depending on how CLKREQ is pulled by end point
1537 data = appl_readl(pcie, APPL_PINMUX);
1538 data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE);
1539 /* Cut REFCLK to slot */
1540 data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1541 data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1542 appl_writel(pcie, data, APPL_PINMUX);
1545 static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
1547 tegra_pcie_downstream_dev_to_D0(pcie);
1548 dw_pcie_host_deinit(&pcie->pci.pp);
1549 tegra_pcie_dw_pme_turnoff(pcie);
1551 return __deinit_controller(pcie);
1554 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
1556 struct pcie_port *pp = &pcie->pci.pp;
1557 struct device *dev = pcie->dev;
1561 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1562 pp->msi_irq = of_irq_get_byname(dev->of_node, "msi");
1564 dev_err(dev, "Failed to get MSI interrupt\n");
1569 pm_runtime_enable(dev);
1571 ret = pm_runtime_get_sync(dev);
1573 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1575 goto fail_pm_get_sync;
1578 ret = pinctrl_pm_select_default_state(dev);
1580 dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
1581 goto fail_pm_get_sync;
1584 tegra_pcie_init_controller(pcie);
1586 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
1587 if (!pcie->link_state) {
1589 goto fail_host_init;
1592 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1595 goto fail_host_init;
1598 pcie->debugfs = debugfs_create_dir(name, NULL);
1604 tegra_pcie_deinit_controller(pcie);
1606 pm_runtime_put_sync(dev);
1607 pm_runtime_disable(dev);
1611 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
1616 if (pcie->ep_state == EP_STATE_DISABLED)
1620 val = appl_readl(pcie, APPL_CTRL);
1621 val &= ~APPL_CTRL_LTSSM_EN;
1622 appl_writel(pcie, val, APPL_CTRL);
1624 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1625 ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>
1626 APPL_DEBUG_LTSSM_STATE_SHIFT) ==
1627 LTSSM_STATE_PRE_DETECT,
1630 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1632 reset_control_assert(pcie->core_rst);
1634 tegra_pcie_disable_phy(pcie);
1636 reset_control_assert(pcie->core_apb_rst);
1638 clk_disable_unprepare(pcie->core_clk);
1640 pm_runtime_put_sync(pcie->dev);
1642 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1644 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
1646 pcie->ep_state = EP_STATE_DISABLED;
1647 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
1650 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
1652 struct dw_pcie *pci = &pcie->pci;
1653 struct dw_pcie_ep *ep = &pci->ep;
1654 struct device *dev = pcie->dev;
1658 if (pcie->ep_state == EP_STATE_ENABLED)
1661 ret = pm_runtime_resume_and_get(dev);
1663 dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
1668 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1670 dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret);
1674 ret = clk_prepare_enable(pcie->core_clk);
1676 dev_err(dev, "Failed to enable core clock: %d\n", ret);
1677 goto fail_core_clk_enable;
1680 ret = reset_control_deassert(pcie->core_apb_rst);
1682 dev_err(dev, "Failed to deassert core APB reset: %d\n", ret);
1683 goto fail_core_apb_rst;
1686 ret = tegra_pcie_enable_phy(pcie);
1688 dev_err(dev, "Failed to enable PHY: %d\n", ret);
1692 /* Clear any stale interrupt statuses */
1693 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
1694 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
1695 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
1696 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
1697 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
1698 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
1699 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
1700 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
1701 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
1702 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
1703 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
1704 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
1705 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
1706 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
1707 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
1709 /* configure this core for EP mode operation */
1710 val = appl_readl(pcie, APPL_DM_TYPE);
1711 val &= ~APPL_DM_TYPE_MASK;
1712 val |= APPL_DM_TYPE_EP;
1713 appl_writel(pcie, val, APPL_DM_TYPE);
1715 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1717 val = appl_readl(pcie, APPL_CTRL);
1718 val |= APPL_CTRL_SYS_PRE_DET_STATE;
1719 val |= APPL_CTRL_HW_HOT_RST_EN;
1720 appl_writel(pcie, val, APPL_CTRL);
1722 val = appl_readl(pcie, APPL_CFG_MISC);
1723 val |= APPL_CFG_MISC_SLV_EP_MODE;
1724 val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
1725 appl_writel(pcie, val, APPL_CFG_MISC);
1727 val = appl_readl(pcie, APPL_PINMUX);
1728 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
1729 val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
1730 appl_writel(pcie, val, APPL_PINMUX);
1732 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1733 APPL_CFG_BASE_ADDR);
1735 appl_writel(pcie, pcie->atu_dma_res->start &
1736 APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1737 APPL_CFG_IATU_DMA_BASE_ADDR);
1739 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1740 val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
1741 val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
1742 val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
1743 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1745 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1746 val |= APPL_INTR_EN_L1_0_0_HOT_RESET_DONE_INT_EN;
1747 val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
1748 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1750 reset_control_deassert(pcie->core_rst);
1752 if (pcie->update_fc_fixup) {
1753 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
1754 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
1755 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
1758 config_gen3_gen4_eq_presets(pcie);
1760 init_host_aspm(pcie);
1762 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
1763 if (!pcie->supports_clkreq) {
1764 disable_aspm_l11(pcie);
1765 disable_aspm_l12(pcie);
1768 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
1769 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
1770 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
1772 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1774 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
1776 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
1777 val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
1778 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
1779 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
1780 dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
1782 ret = dw_pcie_ep_init_complete(ep);
1784 dev_err(dev, "Failed to complete initialization: %d\n", ret);
1785 goto fail_init_complete;
1788 dw_pcie_ep_init_notify(ep);
1791 val = appl_readl(pcie, APPL_CTRL);
1792 val |= APPL_CTRL_LTSSM_EN;
1793 appl_writel(pcie, val, APPL_CTRL);
1795 pcie->ep_state = EP_STATE_ENABLED;
1796 dev_dbg(dev, "Initialization of endpoint is completed\n");
1801 reset_control_assert(pcie->core_rst);
1802 tegra_pcie_disable_phy(pcie);
1804 reset_control_assert(pcie->core_apb_rst);
1806 clk_disable_unprepare(pcie->core_clk);
1807 fail_core_clk_enable:
1808 tegra_pcie_bpmp_set_pll_state(pcie, false);
1810 pm_runtime_put_sync(dev);
1813 static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
1815 struct tegra_pcie_dw *pcie = arg;
1817 if (gpiod_get_value(pcie->pex_rst_gpiod))
1818 pex_ep_event_pex_rst_assert(pcie);
1820 pex_ep_event_pex_rst_deassert(pcie);
1825 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)
1827 /* Tegra194 supports only INTA */
1831 appl_writel(pcie, 1, APPL_LEGACY_INTX);
1832 usleep_range(1000, 2000);
1833 appl_writel(pcie, 0, APPL_LEGACY_INTX);
1837 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
1839 if (unlikely(irq > 31))
1842 appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
1847 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
1849 struct dw_pcie_ep *ep = &pcie->pci.ep;
1851 writel(irq, ep->msi_mem);
1856 static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1857 enum pci_epc_irq_type type,
1860 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1861 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1864 case PCI_EPC_IRQ_LEGACY:
1865 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
1867 case PCI_EPC_IRQ_MSI:
1868 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1870 case PCI_EPC_IRQ_MSIX:
1871 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
1874 dev_err(pci->dev, "Unknown IRQ type\n");
1881 static const struct pci_epc_features tegra_pcie_epc_features = {
1882 .linkup_notifier = true,
1883 .core_init_notifier = true,
1884 .msi_capable = false,
1885 .msix_capable = false,
1886 .reserved_bar = 1 << BAR_2 | 1 << BAR_3 | 1 << BAR_4 | 1 << BAR_5,
1887 .bar_fixed_64bit = 1 << BAR_0,
1888 .bar_fixed_size[0] = SZ_1M,
1891 static const struct pci_epc_features*
1892 tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
1894 return &tegra_pcie_epc_features;
1897 static struct dw_pcie_ep_ops pcie_ep_ops = {
1898 .raise_irq = tegra_pcie_ep_raise_irq,
1899 .get_features = tegra_pcie_ep_get_features,
1902 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
1903 struct platform_device *pdev)
1905 struct dw_pcie *pci = &pcie->pci;
1906 struct device *dev = pcie->dev;
1907 struct dw_pcie_ep *ep;
1908 struct resource *res;
1913 ep->ops = &pcie_ep_ops;
1915 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
1919 ep->phys_base = res->start;
1920 ep->addr_size = resource_size(res);
1921 ep->page_size = SZ_64K;
1923 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
1925 dev_err(dev, "Failed to set PERST GPIO debounce time: %d\n",
1930 ret = gpiod_to_irq(pcie->pex_rst_gpiod);
1932 dev_err(dev, "Failed to get IRQ for PERST GPIO: %d\n", ret);
1935 pcie->pex_rst_irq = (unsigned int)ret;
1937 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_pex_rst_irq",
1940 dev_err(dev, "Failed to create PERST IRQ string\n");
1944 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
1946 pcie->ep_state = EP_STATE_DISABLED;
1948 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
1949 tegra_pcie_ep_pex_rst_irq,
1950 IRQF_TRIGGER_RISING |
1951 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1952 name, (void *)pcie);
1954 dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
1958 name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work",
1961 dev_err(dev, "Failed to create PCIe EP work thread string\n");
1965 pm_runtime_enable(dev);
1967 ret = dw_pcie_ep_init(ep);
1969 dev_err(dev, "Failed to initialize DWC Endpoint subsystem: %d\n",
1971 pm_runtime_disable(dev);
1978 static int tegra_pcie_dw_probe(struct platform_device *pdev)
1980 const struct tegra_pcie_dw_of_data *data;
1981 struct device *dev = &pdev->dev;
1982 struct resource *atu_dma_res;
1983 struct tegra_pcie_dw *pcie;
1984 struct resource *dbi_res;
1985 struct pcie_port *pp;
1986 struct dw_pcie *pci;
1992 data = of_device_get_match_data(dev);
1994 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1999 pci->dev = &pdev->dev;
2000 pci->ops = &tegra_dw_pcie_ops;
2001 pci->n_fts[0] = N_FTS_VAL;
2002 pci->n_fts[1] = FTS_VAL;
2005 pcie->dev = &pdev->dev;
2006 pcie->mode = (enum dw_pcie_device_mode)data->mode;
2008 ret = tegra_pcie_dw_parse_dt(pcie);
2010 const char *level = KERN_ERR;
2012 if (ret == -EPROBE_DEFER)
2015 dev_printk(level, dev,
2016 dev_fmt("Failed to parse device tree: %d\n"),
2021 ret = tegra_pcie_get_slot_regulators(pcie);
2023 const char *level = KERN_ERR;
2025 if (ret == -EPROBE_DEFER)
2028 dev_printk(level, dev,
2029 dev_fmt("Failed to get slot regulators: %d\n"),
2034 if (pcie->pex_refclk_sel_gpiod)
2035 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2037 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2038 if (IS_ERR(pcie->pex_ctl_supply)) {
2039 ret = PTR_ERR(pcie->pex_ctl_supply);
2040 if (ret != -EPROBE_DEFER)
2041 dev_err(dev, "Failed to get regulator: %ld\n",
2042 PTR_ERR(pcie->pex_ctl_supply));
2046 pcie->core_clk = devm_clk_get(dev, "core");
2047 if (IS_ERR(pcie->core_clk)) {
2048 dev_err(dev, "Failed to get core clock: %ld\n",
2049 PTR_ERR(pcie->core_clk));
2050 return PTR_ERR(pcie->core_clk);
2053 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2055 if (!pcie->appl_res) {
2056 dev_err(dev, "Failed to find \"appl\" region\n");
2060 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2061 if (IS_ERR(pcie->appl_base))
2062 return PTR_ERR(pcie->appl_base);
2064 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2065 if (IS_ERR(pcie->core_apb_rst)) {
2066 dev_err(dev, "Failed to get APB reset: %ld\n",
2067 PTR_ERR(pcie->core_apb_rst));
2068 return PTR_ERR(pcie->core_apb_rst);
2071 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2075 for (i = 0; i < pcie->phy_count; i++) {
2076 name = kasprintf(GFP_KERNEL, "p2u-%u", i);
2078 dev_err(dev, "Failed to create P2U string\n");
2081 phys[i] = devm_phy_get(dev, name);
2083 if (IS_ERR(phys[i])) {
2084 ret = PTR_ERR(phys[i]);
2085 if (ret != -EPROBE_DEFER)
2086 dev_err(dev, "Failed to get PHY: %d\n", ret);
2093 dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
2095 dev_err(dev, "Failed to find \"dbi\" region\n");
2098 pcie->dbi_res = dbi_res;
2100 pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
2101 if (IS_ERR(pci->dbi_base))
2102 return PTR_ERR(pci->dbi_base);
2104 /* Tegra HW locates DBI2 at a fixed offset from DBI */
2105 pci->dbi_base2 = pci->dbi_base + 0x1000;
2107 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2110 dev_err(dev, "Failed to find \"atu_dma\" region\n");
2113 pcie->atu_dma_res = atu_dma_res;
2115 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
2116 if (IS_ERR(pci->atu_base))
2117 return PTR_ERR(pci->atu_base);
2119 pcie->core_rst = devm_reset_control_get(dev, "core");
2120 if (IS_ERR(pcie->core_rst)) {
2121 dev_err(dev, "Failed to get core reset: %ld\n",
2122 PTR_ERR(pcie->core_rst));
2123 return PTR_ERR(pcie->core_rst);
2126 pp->irq = platform_get_irq_byname(pdev, "intr");
2130 pcie->bpmp = tegra_bpmp_get(dev);
2131 if (IS_ERR(pcie->bpmp))
2132 return PTR_ERR(pcie->bpmp);
2134 platform_set_drvdata(pdev, pcie);
2136 switch (pcie->mode) {
2137 case DW_PCIE_RC_TYPE:
2138 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
2139 IRQF_SHARED, "tegra-pcie-intr", pcie);
2141 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2146 ret = tegra_pcie_config_rp(pcie);
2147 if (ret && ret != -ENOMEDIUM)
2153 case DW_PCIE_EP_TYPE:
2154 ret = devm_request_threaded_irq(dev, pp->irq,
2155 tegra_pcie_ep_hard_irq,
2156 tegra_pcie_ep_irq_thread,
2157 IRQF_SHARED | IRQF_ONESHOT,
2158 "tegra-pcie-ep-intr", pcie);
2160 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2165 ret = tegra_pcie_config_ep(pcie, pdev);
2171 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode);
2175 tegra_bpmp_put(pcie->bpmp);
2179 static int tegra_pcie_dw_remove(struct platform_device *pdev)
2181 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2183 if (!pcie->link_state)
2186 debugfs_remove_recursive(pcie->debugfs);
2187 tegra_pcie_deinit_controller(pcie);
2188 pm_runtime_put_sync(pcie->dev);
2189 pm_runtime_disable(pcie->dev);
2190 tegra_bpmp_put(pcie->bpmp);
2191 if (pcie->pex_refclk_sel_gpiod)
2192 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
2197 static int tegra_pcie_dw_suspend_late(struct device *dev)
2199 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2202 if (!pcie->link_state)
2205 /* Enable HW_HOT_RST mode */
2206 val = appl_readl(pcie, APPL_CTRL);
2207 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2208 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
2209 val |= APPL_CTRL_HW_HOT_RST_EN;
2210 appl_writel(pcie, val, APPL_CTRL);
2215 static int tegra_pcie_dw_suspend_noirq(struct device *dev)
2217 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2219 if (!pcie->link_state)
2222 /* Save MSI interrupt vector */
2223 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
2224 PORT_LOGIC_MSI_CTRL_INT_0_EN);
2225 tegra_pcie_downstream_dev_to_D0(pcie);
2226 tegra_pcie_dw_pme_turnoff(pcie);
2228 return __deinit_controller(pcie);
2231 static int tegra_pcie_dw_resume_noirq(struct device *dev)
2233 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2236 if (!pcie->link_state)
2239 ret = tegra_pcie_config_controller(pcie, true);
2243 ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
2245 dev_err(dev, "Failed to init host: %d\n", ret);
2246 goto fail_host_init;
2249 /* Restore MSI interrupt vector */
2250 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
2251 pcie->msi_ctrl_int);
2256 return __deinit_controller(pcie);
2259 static int tegra_pcie_dw_resume_early(struct device *dev)
2261 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2264 if (!pcie->link_state)
2267 /* Disable HW_HOT_RST mode */
2268 val = appl_readl(pcie, APPL_CTRL);
2269 val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
2270 APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
2271 val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
2272 APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
2273 val &= ~APPL_CTRL_HW_HOT_RST_EN;
2274 appl_writel(pcie, val, APPL_CTRL);
2279 static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
2281 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2283 if (!pcie->link_state)
2286 debugfs_remove_recursive(pcie->debugfs);
2287 tegra_pcie_downstream_dev_to_D0(pcie);
2289 disable_irq(pcie->pci.pp.irq);
2290 if (IS_ENABLED(CONFIG_PCI_MSI))
2291 disable_irq(pcie->pci.pp.msi_irq);
2293 tegra_pcie_dw_pme_turnoff(pcie);
2294 __deinit_controller(pcie);
2297 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = {
2298 .mode = DW_PCIE_RC_TYPE,
2301 static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = {
2302 .mode = DW_PCIE_EP_TYPE,
2305 static const struct of_device_id tegra_pcie_dw_of_match[] = {
2307 .compatible = "nvidia,tegra194-pcie",
2308 .data = &tegra_pcie_dw_rc_of_data,
2311 .compatible = "nvidia,tegra194-pcie-ep",
2312 .data = &tegra_pcie_dw_ep_of_data,
2317 static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
2318 .suspend_late = tegra_pcie_dw_suspend_late,
2319 .suspend_noirq = tegra_pcie_dw_suspend_noirq,
2320 .resume_noirq = tegra_pcie_dw_resume_noirq,
2321 .resume_early = tegra_pcie_dw_resume_early,
2324 static struct platform_driver tegra_pcie_dw_driver = {
2325 .probe = tegra_pcie_dw_probe,
2326 .remove = tegra_pcie_dw_remove,
2327 .shutdown = tegra_pcie_dw_shutdown,
2329 .name = "tegra194-pcie",
2330 .pm = &tegra_pcie_dw_pm_ops,
2331 .of_match_table = tegra_pcie_dw_of_match,
2334 module_platform_driver(tegra_pcie_dw_driver);
2336 MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
2338 MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
2339 MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
2340 MODULE_LICENSE("GPL v2");