1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
30 #include "../../pci.h"
31 #include "pcie-designware.h"
33 #define PCIE20_PARF_SYS_CTRL 0x00
34 #define MST_WAKEUP_EN BIT(13)
35 #define SLV_WAKEUP_EN BIT(12)
36 #define MSTR_ACLK_CGC_DIS BIT(10)
37 #define SLV_ACLK_CGC_DIS BIT(9)
38 #define CORE_CLK_CGC_DIS BIT(6)
39 #define AUX_PWR_DET BIT(4)
40 #define L23_CLK_RMV_DIS BIT(2)
41 #define L1_CLK_RMV_DIS BIT(1)
43 #define PCIE20_PARF_PHY_CTRL 0x40
44 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
45 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
47 #define PCIE20_PARF_PHY_REFCLK 0x4C
48 #define PHY_REFCLK_SSP_EN BIT(16)
49 #define PHY_REFCLK_USE_PAD BIT(12)
51 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
52 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
53 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
54 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
55 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
56 #define PCIE20_PARF_LTSSM 0x1B0
57 #define PCIE20_PARF_SID_OFFSET 0x234
58 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
59 #define PCIE20_PARF_DEVICE_TYPE 0x1000
61 #define PCIE20_ELBI_SYS_CTRL 0x04
62 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
64 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
65 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
66 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
67 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
68 #define CFG_BRIDGE_SB_INIT BIT(0)
70 #define PCIE_CAP_LINK1_VAL 0x2FD7F
72 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
74 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
75 #define DBI_RO_WR_EN 1
77 #define PERST_DELAY_US 1000
79 #define PCIE20_PARF_PCS_DEEMPH 0x34
80 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
81 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
82 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
84 #define PCIE20_PARF_PCS_SWING 0x38
85 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
86 #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
88 #define PCIE20_PARF_CONFIG_BITS 0x50
89 #define PHY_RX0_EQ(x) ((x) << 24)
91 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
92 #define SLV_ADDR_SPACE_SZ 0x10000000
94 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
96 #define DEVICE_TYPE_RC 0x4
98 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
99 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
100 struct qcom_pcie_resources_2_1_0 {
101 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
102 struct reset_control *pci_reset;
103 struct reset_control *axi_reset;
104 struct reset_control *ahb_reset;
105 struct reset_control *por_reset;
106 struct reset_control *phy_reset;
107 struct reset_control *ext_reset;
108 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
111 struct qcom_pcie_resources_1_0_0 {
114 struct clk *master_bus;
115 struct clk *slave_bus;
116 struct reset_control *core;
117 struct regulator *vdda;
120 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
121 struct qcom_pcie_resources_2_3_2 {
123 struct clk *master_clk;
124 struct clk *slave_clk;
126 struct clk *pipe_clk;
127 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
130 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
131 struct qcom_pcie_resources_2_4_0 {
132 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
134 struct reset_control *axi_m_reset;
135 struct reset_control *axi_s_reset;
136 struct reset_control *pipe_reset;
137 struct reset_control *axi_m_vmid_reset;
138 struct reset_control *axi_s_xpu_reset;
139 struct reset_control *parf_reset;
140 struct reset_control *phy_reset;
141 struct reset_control *axi_m_sticky_reset;
142 struct reset_control *pipe_sticky_reset;
143 struct reset_control *pwr_reset;
144 struct reset_control *ahb_reset;
145 struct reset_control *phy_ahb_reset;
148 struct qcom_pcie_resources_2_3_3 {
150 struct clk *axi_m_clk;
151 struct clk *axi_s_clk;
154 struct reset_control *rst[7];
157 struct qcom_pcie_resources_2_7_0 {
158 struct clk_bulk_data clks[6];
159 struct regulator_bulk_data supplies[2];
160 struct reset_control *pci_reset;
161 struct clk *pipe_clk;
164 union qcom_pcie_resources {
165 struct qcom_pcie_resources_1_0_0 v1_0_0;
166 struct qcom_pcie_resources_2_1_0 v2_1_0;
167 struct qcom_pcie_resources_2_3_2 v2_3_2;
168 struct qcom_pcie_resources_2_3_3 v2_3_3;
169 struct qcom_pcie_resources_2_4_0 v2_4_0;
170 struct qcom_pcie_resources_2_7_0 v2_7_0;
175 struct qcom_pcie_ops {
176 int (*get_resources)(struct qcom_pcie *pcie);
177 int (*init)(struct qcom_pcie *pcie);
178 int (*post_init)(struct qcom_pcie *pcie);
179 void (*deinit)(struct qcom_pcie *pcie);
180 void (*post_deinit)(struct qcom_pcie *pcie);
181 void (*ltssm_enable)(struct qcom_pcie *pcie);
186 void __iomem *parf; /* DT parf */
187 void __iomem *elbi; /* DT elbi */
188 union qcom_pcie_resources res;
190 struct gpio_desc *reset;
191 const struct qcom_pcie_ops *ops;
194 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
196 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
198 gpiod_set_value_cansleep(pcie->reset, 1);
199 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
202 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
204 /* Ensure that PERST has been asserted for at least 100 ms */
206 gpiod_set_value_cansleep(pcie->reset, 0);
207 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
210 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
212 struct dw_pcie *pci = pcie->pci;
214 if (dw_pcie_link_up(pci))
217 /* Enable Link Training state machine */
218 if (pcie->ops->ltssm_enable)
219 pcie->ops->ltssm_enable(pcie);
221 return dw_pcie_wait_for_link(pci);
224 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
228 /* enable link training */
229 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
230 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
231 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
234 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
236 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
237 struct dw_pcie *pci = pcie->pci;
238 struct device *dev = pci->dev;
241 res->supplies[0].supply = "vdda";
242 res->supplies[1].supply = "vdda_phy";
243 res->supplies[2].supply = "vdda_refclk";
244 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
249 res->clks[0].id = "iface";
250 res->clks[1].id = "core";
251 res->clks[2].id = "phy";
252 res->clks[3].id = "aux";
253 res->clks[4].id = "ref";
255 /* iface, core, phy are required */
256 ret = devm_clk_bulk_get(dev, 3, res->clks);
260 /* aux, ref are optional */
261 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
265 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
266 if (IS_ERR(res->pci_reset))
267 return PTR_ERR(res->pci_reset);
269 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
270 if (IS_ERR(res->axi_reset))
271 return PTR_ERR(res->axi_reset);
273 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
274 if (IS_ERR(res->ahb_reset))
275 return PTR_ERR(res->ahb_reset);
277 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
278 if (IS_ERR(res->por_reset))
279 return PTR_ERR(res->por_reset);
281 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
282 if (IS_ERR(res->ext_reset))
283 return PTR_ERR(res->ext_reset);
285 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
286 return PTR_ERR_OR_ZERO(res->phy_reset);
289 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
291 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
293 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
294 reset_control_assert(res->pci_reset);
295 reset_control_assert(res->axi_reset);
296 reset_control_assert(res->ahb_reset);
297 reset_control_assert(res->por_reset);
298 reset_control_assert(res->ext_reset);
299 reset_control_assert(res->phy_reset);
301 writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
303 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
306 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
308 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
309 struct dw_pcie *pci = pcie->pci;
310 struct device *dev = pci->dev;
311 struct device_node *node = dev->of_node;
315 /* reset the PCIe interface as uboot can leave it undefined state */
316 reset_control_assert(res->pci_reset);
317 reset_control_assert(res->axi_reset);
318 reset_control_assert(res->ahb_reset);
319 reset_control_assert(res->por_reset);
320 reset_control_assert(res->ext_reset);
321 reset_control_assert(res->phy_reset);
323 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
325 dev_err(dev, "cannot enable regulators\n");
329 ret = reset_control_deassert(res->ahb_reset);
331 dev_err(dev, "cannot deassert ahb reset\n");
332 goto err_deassert_ahb;
335 ret = reset_control_deassert(res->ext_reset);
337 dev_err(dev, "cannot deassert ext reset\n");
338 goto err_deassert_ext;
341 ret = reset_control_deassert(res->phy_reset);
343 dev_err(dev, "cannot deassert phy reset\n");
344 goto err_deassert_phy;
347 ret = reset_control_deassert(res->pci_reset);
349 dev_err(dev, "cannot deassert pci reset\n");
350 goto err_deassert_pci;
353 ret = reset_control_deassert(res->por_reset);
355 dev_err(dev, "cannot deassert por reset\n");
356 goto err_deassert_por;
359 ret = reset_control_deassert(res->axi_reset);
361 dev_err(dev, "cannot deassert axi reset\n");
362 goto err_deassert_axi;
365 /* enable PCIe clocks and resets */
366 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
368 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
370 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
374 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
375 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
376 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
377 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
378 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
379 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
380 writel(PCS_SWING_TX_SWING_FULL(120) |
381 PCS_SWING_TX_SWING_LOW(120),
382 pcie->parf + PCIE20_PARF_PCS_SWING);
383 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
386 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
387 /* set TX termination offset */
388 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
389 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
390 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
391 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
394 /* enable external reference clock */
395 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
396 /* USE_PAD is required only for ipq806x */
397 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
398 val &= ~PHY_REFCLK_USE_PAD;
399 val |= PHY_REFCLK_SSP_EN;
400 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
402 /* wait for clock acquisition */
403 usleep_range(1000, 1500);
405 /* Set the Max TLP size to 2K, instead of using default of 4K */
406 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
407 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
408 writel(CFG_BRIDGE_SB_INIT,
409 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
414 reset_control_assert(res->axi_reset);
416 reset_control_assert(res->por_reset);
418 reset_control_assert(res->pci_reset);
420 reset_control_assert(res->phy_reset);
422 reset_control_assert(res->ext_reset);
424 reset_control_assert(res->ahb_reset);
426 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
431 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
433 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
434 struct dw_pcie *pci = pcie->pci;
435 struct device *dev = pci->dev;
437 res->vdda = devm_regulator_get(dev, "vdda");
438 if (IS_ERR(res->vdda))
439 return PTR_ERR(res->vdda);
441 res->iface = devm_clk_get(dev, "iface");
442 if (IS_ERR(res->iface))
443 return PTR_ERR(res->iface);
445 res->aux = devm_clk_get(dev, "aux");
446 if (IS_ERR(res->aux))
447 return PTR_ERR(res->aux);
449 res->master_bus = devm_clk_get(dev, "master_bus");
450 if (IS_ERR(res->master_bus))
451 return PTR_ERR(res->master_bus);
453 res->slave_bus = devm_clk_get(dev, "slave_bus");
454 if (IS_ERR(res->slave_bus))
455 return PTR_ERR(res->slave_bus);
457 res->core = devm_reset_control_get_exclusive(dev, "core");
458 return PTR_ERR_OR_ZERO(res->core);
461 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
463 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
465 reset_control_assert(res->core);
466 clk_disable_unprepare(res->slave_bus);
467 clk_disable_unprepare(res->master_bus);
468 clk_disable_unprepare(res->iface);
469 clk_disable_unprepare(res->aux);
470 regulator_disable(res->vdda);
473 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
475 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
476 struct dw_pcie *pci = pcie->pci;
477 struct device *dev = pci->dev;
480 ret = reset_control_deassert(res->core);
482 dev_err(dev, "cannot deassert core reset\n");
486 ret = clk_prepare_enable(res->aux);
488 dev_err(dev, "cannot prepare/enable aux clock\n");
492 ret = clk_prepare_enable(res->iface);
494 dev_err(dev, "cannot prepare/enable iface clock\n");
498 ret = clk_prepare_enable(res->master_bus);
500 dev_err(dev, "cannot prepare/enable master_bus clock\n");
504 ret = clk_prepare_enable(res->slave_bus);
506 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
510 ret = regulator_enable(res->vdda);
512 dev_err(dev, "cannot enable vdda regulator\n");
516 /* change DBI base address */
517 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
519 if (IS_ENABLED(CONFIG_PCI_MSI)) {
520 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
523 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
528 clk_disable_unprepare(res->slave_bus);
530 clk_disable_unprepare(res->master_bus);
532 clk_disable_unprepare(res->iface);
534 clk_disable_unprepare(res->aux);
536 reset_control_assert(res->core);
541 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
545 /* enable link training */
546 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
548 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
551 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
553 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
554 struct dw_pcie *pci = pcie->pci;
555 struct device *dev = pci->dev;
558 res->supplies[0].supply = "vdda";
559 res->supplies[1].supply = "vddpe-3v3";
560 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
565 res->aux_clk = devm_clk_get(dev, "aux");
566 if (IS_ERR(res->aux_clk))
567 return PTR_ERR(res->aux_clk);
569 res->cfg_clk = devm_clk_get(dev, "cfg");
570 if (IS_ERR(res->cfg_clk))
571 return PTR_ERR(res->cfg_clk);
573 res->master_clk = devm_clk_get(dev, "bus_master");
574 if (IS_ERR(res->master_clk))
575 return PTR_ERR(res->master_clk);
577 res->slave_clk = devm_clk_get(dev, "bus_slave");
578 if (IS_ERR(res->slave_clk))
579 return PTR_ERR(res->slave_clk);
581 res->pipe_clk = devm_clk_get(dev, "pipe");
582 return PTR_ERR_OR_ZERO(res->pipe_clk);
585 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
587 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
589 clk_disable_unprepare(res->slave_clk);
590 clk_disable_unprepare(res->master_clk);
591 clk_disable_unprepare(res->cfg_clk);
592 clk_disable_unprepare(res->aux_clk);
594 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
597 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
599 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
601 clk_disable_unprepare(res->pipe_clk);
604 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
606 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
607 struct dw_pcie *pci = pcie->pci;
608 struct device *dev = pci->dev;
612 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
614 dev_err(dev, "cannot enable regulators\n");
618 ret = clk_prepare_enable(res->aux_clk);
620 dev_err(dev, "cannot prepare/enable aux clock\n");
624 ret = clk_prepare_enable(res->cfg_clk);
626 dev_err(dev, "cannot prepare/enable cfg clock\n");
630 ret = clk_prepare_enable(res->master_clk);
632 dev_err(dev, "cannot prepare/enable master clock\n");
636 ret = clk_prepare_enable(res->slave_clk);
638 dev_err(dev, "cannot prepare/enable slave clock\n");
642 /* enable PCIe clocks and resets */
643 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
645 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
647 /* change DBI base address */
648 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
650 /* MAC PHY_POWERDOWN MUX DISABLE */
651 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
653 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
655 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
657 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
659 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
661 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
666 clk_disable_unprepare(res->master_clk);
668 clk_disable_unprepare(res->cfg_clk);
670 clk_disable_unprepare(res->aux_clk);
673 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
678 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
680 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
681 struct dw_pcie *pci = pcie->pci;
682 struct device *dev = pci->dev;
685 ret = clk_prepare_enable(res->pipe_clk);
687 dev_err(dev, "cannot prepare/enable pipe clock\n");
694 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
696 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
697 struct dw_pcie *pci = pcie->pci;
698 struct device *dev = pci->dev;
699 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
702 res->clks[0].id = "aux";
703 res->clks[1].id = "master_bus";
704 res->clks[2].id = "slave_bus";
705 res->clks[3].id = "iface";
707 /* qcom,pcie-ipq4019 is defined without "iface" */
708 res->num_clks = is_ipq ? 3 : 4;
710 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
714 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
715 if (IS_ERR(res->axi_m_reset))
716 return PTR_ERR(res->axi_m_reset);
718 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
719 if (IS_ERR(res->axi_s_reset))
720 return PTR_ERR(res->axi_s_reset);
724 * These resources relates to the PHY or are secure clocks, but
725 * are controlled here for IPQ4019
727 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
728 if (IS_ERR(res->pipe_reset))
729 return PTR_ERR(res->pipe_reset);
731 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
733 if (IS_ERR(res->axi_m_vmid_reset))
734 return PTR_ERR(res->axi_m_vmid_reset);
736 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
738 if (IS_ERR(res->axi_s_xpu_reset))
739 return PTR_ERR(res->axi_s_xpu_reset);
741 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
742 if (IS_ERR(res->parf_reset))
743 return PTR_ERR(res->parf_reset);
745 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
746 if (IS_ERR(res->phy_reset))
747 return PTR_ERR(res->phy_reset);
750 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
752 if (IS_ERR(res->axi_m_sticky_reset))
753 return PTR_ERR(res->axi_m_sticky_reset);
755 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
757 if (IS_ERR(res->pipe_sticky_reset))
758 return PTR_ERR(res->pipe_sticky_reset);
760 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
761 if (IS_ERR(res->pwr_reset))
762 return PTR_ERR(res->pwr_reset);
764 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
765 if (IS_ERR(res->ahb_reset))
766 return PTR_ERR(res->ahb_reset);
769 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
770 if (IS_ERR(res->phy_ahb_reset))
771 return PTR_ERR(res->phy_ahb_reset);
777 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
779 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
781 reset_control_assert(res->axi_m_reset);
782 reset_control_assert(res->axi_s_reset);
783 reset_control_assert(res->pipe_reset);
784 reset_control_assert(res->pipe_sticky_reset);
785 reset_control_assert(res->phy_reset);
786 reset_control_assert(res->phy_ahb_reset);
787 reset_control_assert(res->axi_m_sticky_reset);
788 reset_control_assert(res->pwr_reset);
789 reset_control_assert(res->ahb_reset);
790 clk_bulk_disable_unprepare(res->num_clks, res->clks);
793 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
795 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
796 struct dw_pcie *pci = pcie->pci;
797 struct device *dev = pci->dev;
801 ret = reset_control_assert(res->axi_m_reset);
803 dev_err(dev, "cannot assert axi master reset\n");
807 ret = reset_control_assert(res->axi_s_reset);
809 dev_err(dev, "cannot assert axi slave reset\n");
813 usleep_range(10000, 12000);
815 ret = reset_control_assert(res->pipe_reset);
817 dev_err(dev, "cannot assert pipe reset\n");
821 ret = reset_control_assert(res->pipe_sticky_reset);
823 dev_err(dev, "cannot assert pipe sticky reset\n");
827 ret = reset_control_assert(res->phy_reset);
829 dev_err(dev, "cannot assert phy reset\n");
833 ret = reset_control_assert(res->phy_ahb_reset);
835 dev_err(dev, "cannot assert phy ahb reset\n");
839 usleep_range(10000, 12000);
841 ret = reset_control_assert(res->axi_m_sticky_reset);
843 dev_err(dev, "cannot assert axi master sticky reset\n");
847 ret = reset_control_assert(res->pwr_reset);
849 dev_err(dev, "cannot assert power reset\n");
853 ret = reset_control_assert(res->ahb_reset);
855 dev_err(dev, "cannot assert ahb reset\n");
859 usleep_range(10000, 12000);
861 ret = reset_control_deassert(res->phy_ahb_reset);
863 dev_err(dev, "cannot deassert phy ahb reset\n");
867 ret = reset_control_deassert(res->phy_reset);
869 dev_err(dev, "cannot deassert phy reset\n");
873 ret = reset_control_deassert(res->pipe_reset);
875 dev_err(dev, "cannot deassert pipe reset\n");
879 ret = reset_control_deassert(res->pipe_sticky_reset);
881 dev_err(dev, "cannot deassert pipe sticky reset\n");
882 goto err_rst_pipe_sticky;
885 usleep_range(10000, 12000);
887 ret = reset_control_deassert(res->axi_m_reset);
889 dev_err(dev, "cannot deassert axi master reset\n");
893 ret = reset_control_deassert(res->axi_m_sticky_reset);
895 dev_err(dev, "cannot deassert axi master sticky reset\n");
896 goto err_rst_axi_m_sticky;
899 ret = reset_control_deassert(res->axi_s_reset);
901 dev_err(dev, "cannot deassert axi slave reset\n");
905 ret = reset_control_deassert(res->pwr_reset);
907 dev_err(dev, "cannot deassert power reset\n");
911 ret = reset_control_deassert(res->ahb_reset);
913 dev_err(dev, "cannot deassert ahb reset\n");
917 usleep_range(10000, 12000);
919 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
923 /* enable PCIe clocks and resets */
924 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
926 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
928 /* change DBI base address */
929 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
931 /* MAC PHY_POWERDOWN MUX DISABLE */
932 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
934 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
936 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
938 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
940 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
942 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
947 reset_control_assert(res->ahb_reset);
949 reset_control_assert(res->pwr_reset);
951 reset_control_assert(res->axi_s_reset);
953 reset_control_assert(res->axi_m_sticky_reset);
954 err_rst_axi_m_sticky:
955 reset_control_assert(res->axi_m_reset);
957 reset_control_assert(res->pipe_sticky_reset);
959 reset_control_assert(res->pipe_reset);
961 reset_control_assert(res->phy_reset);
963 reset_control_assert(res->phy_ahb_reset);
967 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
969 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
970 struct dw_pcie *pci = pcie->pci;
971 struct device *dev = pci->dev;
973 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
974 "axi_m_sticky", "sticky",
977 res->iface = devm_clk_get(dev, "iface");
978 if (IS_ERR(res->iface))
979 return PTR_ERR(res->iface);
981 res->axi_m_clk = devm_clk_get(dev, "axi_m");
982 if (IS_ERR(res->axi_m_clk))
983 return PTR_ERR(res->axi_m_clk);
985 res->axi_s_clk = devm_clk_get(dev, "axi_s");
986 if (IS_ERR(res->axi_s_clk))
987 return PTR_ERR(res->axi_s_clk);
989 res->ahb_clk = devm_clk_get(dev, "ahb");
990 if (IS_ERR(res->ahb_clk))
991 return PTR_ERR(res->ahb_clk);
993 res->aux_clk = devm_clk_get(dev, "aux");
994 if (IS_ERR(res->aux_clk))
995 return PTR_ERR(res->aux_clk);
997 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
998 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
999 if (IS_ERR(res->rst[i]))
1000 return PTR_ERR(res->rst[i]);
1006 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1008 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1010 clk_disable_unprepare(res->iface);
1011 clk_disable_unprepare(res->axi_m_clk);
1012 clk_disable_unprepare(res->axi_s_clk);
1013 clk_disable_unprepare(res->ahb_clk);
1014 clk_disable_unprepare(res->aux_clk);
1017 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1019 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1020 struct dw_pcie *pci = pcie->pci;
1021 struct device *dev = pci->dev;
1022 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1026 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1027 ret = reset_control_assert(res->rst[i]);
1029 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1034 usleep_range(2000, 2500);
1036 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1037 ret = reset_control_deassert(res->rst[i]);
1039 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1046 * Don't have a way to see if the reset has completed.
1047 * Wait for some time.
1049 usleep_range(2000, 2500);
1051 ret = clk_prepare_enable(res->iface);
1053 dev_err(dev, "cannot prepare/enable core clock\n");
1057 ret = clk_prepare_enable(res->axi_m_clk);
1059 dev_err(dev, "cannot prepare/enable core clock\n");
1063 ret = clk_prepare_enable(res->axi_s_clk);
1065 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1069 ret = clk_prepare_enable(res->ahb_clk);
1071 dev_err(dev, "cannot prepare/enable ahb clock\n");
1075 ret = clk_prepare_enable(res->aux_clk);
1077 dev_err(dev, "cannot prepare/enable aux clock\n");
1081 writel(SLV_ADDR_SPACE_SZ,
1082 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1084 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1086 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1088 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1090 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1091 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1092 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1093 pcie->parf + PCIE20_PARF_SYS_CTRL);
1094 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1096 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
1097 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1098 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1100 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1101 val &= ~PCI_EXP_LNKCAP_ASPMS;
1102 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1104 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1110 clk_disable_unprepare(res->ahb_clk);
1112 clk_disable_unprepare(res->axi_s_clk);
1114 clk_disable_unprepare(res->axi_m_clk);
1116 clk_disable_unprepare(res->iface);
1119 * Not checking for failure, will anyway return
1120 * the original failure in 'ret'.
1122 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1123 reset_control_assert(res->rst[i]);
1128 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
1130 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1131 struct dw_pcie *pci = pcie->pci;
1132 struct device *dev = pci->dev;
1135 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
1136 if (IS_ERR(res->pci_reset))
1137 return PTR_ERR(res->pci_reset);
1139 res->supplies[0].supply = "vdda";
1140 res->supplies[1].supply = "vddpe-3v3";
1141 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
1146 res->clks[0].id = "aux";
1147 res->clks[1].id = "cfg";
1148 res->clks[2].id = "bus_master";
1149 res->clks[3].id = "bus_slave";
1150 res->clks[4].id = "slave_q2a";
1151 res->clks[5].id = "tbu";
1153 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1157 res->pipe_clk = devm_clk_get(dev, "pipe");
1158 return PTR_ERR_OR_ZERO(res->pipe_clk);
1161 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
1163 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1164 struct dw_pcie *pci = pcie->pci;
1165 struct device *dev = pci->dev;
1169 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
1171 dev_err(dev, "cannot enable regulators\n");
1175 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
1177 goto err_disable_regulators;
1179 ret = reset_control_assert(res->pci_reset);
1181 dev_err(dev, "cannot deassert pci reset\n");
1182 goto err_disable_clocks;
1185 usleep_range(1000, 1500);
1187 ret = reset_control_deassert(res->pci_reset);
1189 dev_err(dev, "cannot deassert pci reset\n");
1190 goto err_disable_clocks;
1193 /* configure PCIe to RC mode */
1194 writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
1196 /* enable PCIe clocks and resets */
1197 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1199 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1201 /* change DBI base address */
1202 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1204 /* MAC PHY_POWERDOWN MUX DISABLE */
1205 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
1207 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
1209 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1211 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
1213 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1214 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1216 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
1221 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1222 err_disable_regulators:
1223 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1228 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1230 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1232 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1233 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1236 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1238 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1240 return clk_prepare_enable(res->pipe_clk);
1243 static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
1245 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1247 clk_disable_unprepare(res->pipe_clk);
1250 static int qcom_pcie_link_up(struct dw_pcie *pci)
1252 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1253 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1255 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1258 static int qcom_pcie_host_init(struct pcie_port *pp)
1260 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1261 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1264 qcom_ep_reset_assert(pcie);
1266 ret = pcie->ops->init(pcie);
1270 ret = phy_power_on(pcie->phy);
1274 if (pcie->ops->post_init) {
1275 ret = pcie->ops->post_init(pcie);
1277 goto err_disable_phy;
1280 dw_pcie_setup_rc(pp);
1281 dw_pcie_msi_init(pp);
1283 qcom_ep_reset_deassert(pcie);
1285 ret = qcom_pcie_establish_link(pcie);
1291 qcom_ep_reset_assert(pcie);
1292 if (pcie->ops->post_deinit)
1293 pcie->ops->post_deinit(pcie);
1295 phy_power_off(pcie->phy);
1297 pcie->ops->deinit(pcie);
1302 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1303 .host_init = qcom_pcie_host_init,
1306 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1307 static const struct qcom_pcie_ops ops_2_1_0 = {
1308 .get_resources = qcom_pcie_get_resources_2_1_0,
1309 .init = qcom_pcie_init_2_1_0,
1310 .deinit = qcom_pcie_deinit_2_1_0,
1311 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1314 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1315 static const struct qcom_pcie_ops ops_1_0_0 = {
1316 .get_resources = qcom_pcie_get_resources_1_0_0,
1317 .init = qcom_pcie_init_1_0_0,
1318 .deinit = qcom_pcie_deinit_1_0_0,
1319 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1322 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1323 static const struct qcom_pcie_ops ops_2_3_2 = {
1324 .get_resources = qcom_pcie_get_resources_2_3_2,
1325 .init = qcom_pcie_init_2_3_2,
1326 .post_init = qcom_pcie_post_init_2_3_2,
1327 .deinit = qcom_pcie_deinit_2_3_2,
1328 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1329 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1332 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1333 static const struct qcom_pcie_ops ops_2_4_0 = {
1334 .get_resources = qcom_pcie_get_resources_2_4_0,
1335 .init = qcom_pcie_init_2_4_0,
1336 .deinit = qcom_pcie_deinit_2_4_0,
1337 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1340 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1341 static const struct qcom_pcie_ops ops_2_3_3 = {
1342 .get_resources = qcom_pcie_get_resources_2_3_3,
1343 .init = qcom_pcie_init_2_3_3,
1344 .deinit = qcom_pcie_deinit_2_3_3,
1345 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1348 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1349 static const struct qcom_pcie_ops ops_2_7_0 = {
1350 .get_resources = qcom_pcie_get_resources_2_7_0,
1351 .init = qcom_pcie_init_2_7_0,
1352 .deinit = qcom_pcie_deinit_2_7_0,
1353 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1354 .post_init = qcom_pcie_post_init_2_7_0,
1355 .post_deinit = qcom_pcie_post_deinit_2_7_0,
1358 static const struct dw_pcie_ops dw_pcie_ops = {
1359 .link_up = qcom_pcie_link_up,
1362 static int qcom_pcie_probe(struct platform_device *pdev)
1364 struct device *dev = &pdev->dev;
1365 struct resource *res;
1366 struct pcie_port *pp;
1367 struct dw_pcie *pci;
1368 struct qcom_pcie *pcie;
1371 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1375 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1379 pm_runtime_enable(dev);
1380 ret = pm_runtime_get_sync(dev);
1382 goto err_pm_runtime_put;
1385 pci->ops = &dw_pcie_ops;
1390 pcie->ops = of_device_get_match_data(dev);
1392 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1393 if (IS_ERR(pcie->reset)) {
1394 ret = PTR_ERR(pcie->reset);
1395 goto err_pm_runtime_put;
1398 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1399 if (IS_ERR(pcie->parf)) {
1400 ret = PTR_ERR(pcie->parf);
1401 goto err_pm_runtime_put;
1404 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1405 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1406 if (IS_ERR(pci->dbi_base)) {
1407 ret = PTR_ERR(pci->dbi_base);
1408 goto err_pm_runtime_put;
1411 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1412 if (IS_ERR(pcie->elbi)) {
1413 ret = PTR_ERR(pcie->elbi);
1414 goto err_pm_runtime_put;
1417 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1418 if (IS_ERR(pcie->phy)) {
1419 ret = PTR_ERR(pcie->phy);
1420 goto err_pm_runtime_put;
1423 ret = pcie->ops->get_resources(pcie);
1425 goto err_pm_runtime_put;
1427 pp->ops = &qcom_pcie_dw_ops;
1429 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1430 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1431 if (pp->msi_irq < 0) {
1433 goto err_pm_runtime_put;
1437 ret = phy_init(pcie->phy);
1439 goto err_pm_runtime_put;
1441 platform_set_drvdata(pdev, pcie);
1443 ret = dw_pcie_host_init(pp);
1445 dev_err(dev, "cannot initialize host\n");
1452 phy_exit(pcie->phy);
1454 pm_runtime_put(dev);
1455 pm_runtime_disable(dev);
1460 static const struct of_device_id qcom_pcie_match[] = {
1461 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1462 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1463 { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
1464 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1465 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1466 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1467 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1468 { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
1469 { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
1473 static void qcom_fixup_class(struct pci_dev *dev)
1475 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
1477 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1478 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1479 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1480 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1481 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1482 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1483 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1485 static struct platform_driver qcom_pcie_driver = {
1486 .probe = qcom_pcie_probe,
1488 .name = "qcom-pcie",
1489 .suppress_bind_attrs = true,
1490 .of_match_table = qcom_pcie_match,
1493 builtin_platform_driver(qcom_pcie_driver);