1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
30 #include "pcie-designware.h"
32 #define PCIE20_PARF_SYS_CTRL 0x00
33 #define MST_WAKEUP_EN BIT(13)
34 #define SLV_WAKEUP_EN BIT(12)
35 #define MSTR_ACLK_CGC_DIS BIT(10)
36 #define SLV_ACLK_CGC_DIS BIT(9)
37 #define CORE_CLK_CGC_DIS BIT(6)
38 #define AUX_PWR_DET BIT(4)
39 #define L23_CLK_RMV_DIS BIT(2)
40 #define L1_CLK_RMV_DIS BIT(1)
42 #define PCIE20_COMMAND_STATUS 0x04
43 #define CMD_BME_VAL 0x4
44 #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
45 #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
47 #define PCIE20_PARF_PHY_CTRL 0x40
48 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
49 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
51 #define PCIE20_PARF_PHY_REFCLK 0x4C
52 #define PHY_REFCLK_SSP_EN BIT(16)
53 #define PHY_REFCLK_USE_PAD BIT(12)
55 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
56 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
57 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
58 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
59 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
60 #define PCIE20_PARF_LTSSM 0x1B0
61 #define PCIE20_PARF_SID_OFFSET 0x234
62 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
64 #define PCIE20_ELBI_SYS_CTRL 0x04
65 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
67 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
68 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
69 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
70 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
71 #define CFG_BRIDGE_SB_INIT BIT(0)
73 #define PCIE20_CAP 0x70
74 #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
75 #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
76 #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
77 #define PCIE_CAP_LINK1_VAL 0x2FD7F
79 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
81 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
82 #define DBI_RO_WR_EN 1
84 #define PERST_DELAY_US 1000
86 #define PCIE20_PARF_PCS_DEEMPH 0x34
87 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
88 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
89 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
91 #define PCIE20_PARF_PCS_SWING 0x38
92 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
93 #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
95 #define PCIE20_PARF_CONFIG_BITS 0x50
96 #define PHY_RX0_EQ(x) ((x) << 24)
98 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
99 #define SLV_ADDR_SPACE_SZ 0x10000000
101 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
102 struct qcom_pcie_resources_2_1_0 {
103 struct clk *iface_clk;
104 struct clk *core_clk;
106 struct reset_control *pci_reset;
107 struct reset_control *axi_reset;
108 struct reset_control *ahb_reset;
109 struct reset_control *por_reset;
110 struct reset_control *phy_reset;
111 struct reset_control *ext_reset;
112 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
115 struct qcom_pcie_resources_1_0_0 {
118 struct clk *master_bus;
119 struct clk *slave_bus;
120 struct reset_control *core;
121 struct regulator *vdda;
124 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
125 struct qcom_pcie_resources_2_3_2 {
127 struct clk *master_clk;
128 struct clk *slave_clk;
130 struct clk *pipe_clk;
131 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
134 struct qcom_pcie_resources_2_4_0 {
136 struct clk *master_clk;
137 struct clk *slave_clk;
138 struct reset_control *axi_m_reset;
139 struct reset_control *axi_s_reset;
140 struct reset_control *pipe_reset;
141 struct reset_control *axi_m_vmid_reset;
142 struct reset_control *axi_s_xpu_reset;
143 struct reset_control *parf_reset;
144 struct reset_control *phy_reset;
145 struct reset_control *axi_m_sticky_reset;
146 struct reset_control *pipe_sticky_reset;
147 struct reset_control *pwr_reset;
148 struct reset_control *ahb_reset;
149 struct reset_control *phy_ahb_reset;
152 struct qcom_pcie_resources_2_3_3 {
154 struct clk *axi_m_clk;
155 struct clk *axi_s_clk;
158 struct reset_control *rst[7];
161 union qcom_pcie_resources {
162 struct qcom_pcie_resources_1_0_0 v1_0_0;
163 struct qcom_pcie_resources_2_1_0 v2_1_0;
164 struct qcom_pcie_resources_2_3_2 v2_3_2;
165 struct qcom_pcie_resources_2_3_3 v2_3_3;
166 struct qcom_pcie_resources_2_4_0 v2_4_0;
171 struct qcom_pcie_ops {
172 int (*get_resources)(struct qcom_pcie *pcie);
173 int (*init)(struct qcom_pcie *pcie);
174 int (*post_init)(struct qcom_pcie *pcie);
175 void (*deinit)(struct qcom_pcie *pcie);
176 void (*post_deinit)(struct qcom_pcie *pcie);
177 void (*ltssm_enable)(struct qcom_pcie *pcie);
182 void __iomem *parf; /* DT parf */
183 void __iomem *elbi; /* DT elbi */
184 union qcom_pcie_resources res;
186 struct gpio_desc *reset;
187 const struct qcom_pcie_ops *ops;
190 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
192 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
194 gpiod_set_value_cansleep(pcie->reset, 1);
195 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
198 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
200 /* Ensure that PERST has been asserted for at least 100 ms */
202 gpiod_set_value_cansleep(pcie->reset, 0);
203 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
206 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
208 struct dw_pcie *pci = pcie->pci;
210 if (dw_pcie_link_up(pci))
213 /* Enable Link Training state machine */
214 if (pcie->ops->ltssm_enable)
215 pcie->ops->ltssm_enable(pcie);
217 return dw_pcie_wait_for_link(pci);
220 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
224 /* enable link training */
225 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
226 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
227 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
230 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
232 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
233 struct dw_pcie *pci = pcie->pci;
234 struct device *dev = pci->dev;
237 res->supplies[0].supply = "vdda";
238 res->supplies[1].supply = "vdda_phy";
239 res->supplies[2].supply = "vdda_refclk";
240 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
245 res->iface_clk = devm_clk_get(dev, "iface");
246 if (IS_ERR(res->iface_clk))
247 return PTR_ERR(res->iface_clk);
249 res->core_clk = devm_clk_get(dev, "core");
250 if (IS_ERR(res->core_clk))
251 return PTR_ERR(res->core_clk);
253 res->phy_clk = devm_clk_get(dev, "phy");
254 if (IS_ERR(res->phy_clk))
255 return PTR_ERR(res->phy_clk);
257 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
258 if (IS_ERR(res->pci_reset))
259 return PTR_ERR(res->pci_reset);
261 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
262 if (IS_ERR(res->axi_reset))
263 return PTR_ERR(res->axi_reset);
265 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
266 if (IS_ERR(res->ahb_reset))
267 return PTR_ERR(res->ahb_reset);
269 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
270 if (IS_ERR(res->por_reset))
271 return PTR_ERR(res->por_reset);
273 res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
274 if (IS_ERR(res->ext_reset))
275 return PTR_ERR(res->ext_reset);
277 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
278 return PTR_ERR_OR_ZERO(res->phy_reset);
281 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
283 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
285 reset_control_assert(res->pci_reset);
286 reset_control_assert(res->axi_reset);
287 reset_control_assert(res->ahb_reset);
288 reset_control_assert(res->por_reset);
289 reset_control_assert(res->ext_reset);
290 reset_control_assert(res->pci_reset);
291 clk_disable_unprepare(res->iface_clk);
292 clk_disable_unprepare(res->core_clk);
293 clk_disable_unprepare(res->phy_clk);
294 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
297 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
299 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
300 struct dw_pcie *pci = pcie->pci;
301 struct device *dev = pci->dev;
302 struct device_node *node = dev->of_node;
306 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
308 dev_err(dev, "cannot enable regulators\n");
312 ret = reset_control_assert(res->ahb_reset);
314 dev_err(dev, "cannot assert ahb reset\n");
318 ret = clk_prepare_enable(res->iface_clk);
320 dev_err(dev, "cannot prepare/enable iface clock\n");
324 ret = clk_prepare_enable(res->phy_clk);
326 dev_err(dev, "cannot prepare/enable phy clock\n");
330 ret = clk_prepare_enable(res->core_clk);
332 dev_err(dev, "cannot prepare/enable core clock\n");
336 ret = reset_control_deassert(res->ahb_reset);
338 dev_err(dev, "cannot deassert ahb reset\n");
339 goto err_deassert_ahb;
342 ret = reset_control_deassert(res->ext_reset);
344 dev_err(dev, "cannot deassert ext reset\n");
345 goto err_deassert_ahb;
348 /* enable PCIe clocks and resets */
349 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
351 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
353 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
354 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
355 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
356 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
357 pcie->parf + PCIE20_PARF_PCS_DEEMPH);
358 writel(PCS_SWING_TX_SWING_FULL(120) |
359 PCS_SWING_TX_SWING_LOW(120),
360 pcie->parf + PCIE20_PARF_PCS_SWING);
361 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
364 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
365 /* set TX termination offset */
366 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
367 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
368 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
369 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
372 /* enable external reference clock */
373 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
374 /* USE_PAD is required only for ipq806x */
375 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
376 val &= ~PHY_REFCLK_USE_PAD;
377 val |= PHY_REFCLK_SSP_EN;
378 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
380 ret = reset_control_deassert(res->phy_reset);
382 dev_err(dev, "cannot deassert phy reset\n");
386 ret = reset_control_deassert(res->pci_reset);
388 dev_err(dev, "cannot deassert pci reset\n");
392 ret = reset_control_deassert(res->por_reset);
394 dev_err(dev, "cannot deassert por reset\n");
398 ret = reset_control_deassert(res->axi_reset);
400 dev_err(dev, "cannot deassert axi reset\n");
404 /* wait for clock acquisition */
405 usleep_range(1000, 1500);
408 /* Set the Max TLP size to 2K, instead of using default of 4K */
409 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
410 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
411 writel(CFG_BRIDGE_SB_INIT,
412 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
417 clk_disable_unprepare(res->core_clk);
419 clk_disable_unprepare(res->phy_clk);
421 clk_disable_unprepare(res->iface_clk);
423 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
428 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
430 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
431 struct dw_pcie *pci = pcie->pci;
432 struct device *dev = pci->dev;
434 res->vdda = devm_regulator_get(dev, "vdda");
435 if (IS_ERR(res->vdda))
436 return PTR_ERR(res->vdda);
438 res->iface = devm_clk_get(dev, "iface");
439 if (IS_ERR(res->iface))
440 return PTR_ERR(res->iface);
442 res->aux = devm_clk_get(dev, "aux");
443 if (IS_ERR(res->aux))
444 return PTR_ERR(res->aux);
446 res->master_bus = devm_clk_get(dev, "master_bus");
447 if (IS_ERR(res->master_bus))
448 return PTR_ERR(res->master_bus);
450 res->slave_bus = devm_clk_get(dev, "slave_bus");
451 if (IS_ERR(res->slave_bus))
452 return PTR_ERR(res->slave_bus);
454 res->core = devm_reset_control_get_exclusive(dev, "core");
455 return PTR_ERR_OR_ZERO(res->core);
458 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
460 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
462 reset_control_assert(res->core);
463 clk_disable_unprepare(res->slave_bus);
464 clk_disable_unprepare(res->master_bus);
465 clk_disable_unprepare(res->iface);
466 clk_disable_unprepare(res->aux);
467 regulator_disable(res->vdda);
470 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
472 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
473 struct dw_pcie *pci = pcie->pci;
474 struct device *dev = pci->dev;
477 ret = reset_control_deassert(res->core);
479 dev_err(dev, "cannot deassert core reset\n");
483 ret = clk_prepare_enable(res->aux);
485 dev_err(dev, "cannot prepare/enable aux clock\n");
489 ret = clk_prepare_enable(res->iface);
491 dev_err(dev, "cannot prepare/enable iface clock\n");
495 ret = clk_prepare_enable(res->master_bus);
497 dev_err(dev, "cannot prepare/enable master_bus clock\n");
501 ret = clk_prepare_enable(res->slave_bus);
503 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
507 ret = regulator_enable(res->vdda);
509 dev_err(dev, "cannot enable vdda regulator\n");
513 /* change DBI base address */
514 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
516 if (IS_ENABLED(CONFIG_PCI_MSI)) {
517 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
520 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
525 clk_disable_unprepare(res->slave_bus);
527 clk_disable_unprepare(res->master_bus);
529 clk_disable_unprepare(res->iface);
531 clk_disable_unprepare(res->aux);
533 reset_control_assert(res->core);
538 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
542 /* enable link training */
543 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
545 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
548 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
550 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
551 struct dw_pcie *pci = pcie->pci;
552 struct device *dev = pci->dev;
555 res->supplies[0].supply = "vdda";
556 res->supplies[1].supply = "vddpe-3v3";
557 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
562 res->aux_clk = devm_clk_get(dev, "aux");
563 if (IS_ERR(res->aux_clk))
564 return PTR_ERR(res->aux_clk);
566 res->cfg_clk = devm_clk_get(dev, "cfg");
567 if (IS_ERR(res->cfg_clk))
568 return PTR_ERR(res->cfg_clk);
570 res->master_clk = devm_clk_get(dev, "bus_master");
571 if (IS_ERR(res->master_clk))
572 return PTR_ERR(res->master_clk);
574 res->slave_clk = devm_clk_get(dev, "bus_slave");
575 if (IS_ERR(res->slave_clk))
576 return PTR_ERR(res->slave_clk);
578 res->pipe_clk = devm_clk_get(dev, "pipe");
579 return PTR_ERR_OR_ZERO(res->pipe_clk);
582 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
584 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
586 clk_disable_unprepare(res->slave_clk);
587 clk_disable_unprepare(res->master_clk);
588 clk_disable_unprepare(res->cfg_clk);
589 clk_disable_unprepare(res->aux_clk);
591 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
594 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
596 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
598 clk_disable_unprepare(res->pipe_clk);
601 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
603 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
604 struct dw_pcie *pci = pcie->pci;
605 struct device *dev = pci->dev;
609 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
611 dev_err(dev, "cannot enable regulators\n");
615 ret = clk_prepare_enable(res->aux_clk);
617 dev_err(dev, "cannot prepare/enable aux clock\n");
621 ret = clk_prepare_enable(res->cfg_clk);
623 dev_err(dev, "cannot prepare/enable cfg clock\n");
627 ret = clk_prepare_enable(res->master_clk);
629 dev_err(dev, "cannot prepare/enable master clock\n");
633 ret = clk_prepare_enable(res->slave_clk);
635 dev_err(dev, "cannot prepare/enable slave clock\n");
639 /* enable PCIe clocks and resets */
640 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
642 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
644 /* change DBI base address */
645 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
647 /* MAC PHY_POWERDOWN MUX DISABLE */
648 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
650 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
652 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
654 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
656 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
658 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
663 clk_disable_unprepare(res->master_clk);
665 clk_disable_unprepare(res->cfg_clk);
667 clk_disable_unprepare(res->aux_clk);
670 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
675 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
677 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
678 struct dw_pcie *pci = pcie->pci;
679 struct device *dev = pci->dev;
682 ret = clk_prepare_enable(res->pipe_clk);
684 dev_err(dev, "cannot prepare/enable pipe clock\n");
691 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
693 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
694 struct dw_pcie *pci = pcie->pci;
695 struct device *dev = pci->dev;
697 res->aux_clk = devm_clk_get(dev, "aux");
698 if (IS_ERR(res->aux_clk))
699 return PTR_ERR(res->aux_clk);
701 res->master_clk = devm_clk_get(dev, "master_bus");
702 if (IS_ERR(res->master_clk))
703 return PTR_ERR(res->master_clk);
705 res->slave_clk = devm_clk_get(dev, "slave_bus");
706 if (IS_ERR(res->slave_clk))
707 return PTR_ERR(res->slave_clk);
709 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
710 if (IS_ERR(res->axi_m_reset))
711 return PTR_ERR(res->axi_m_reset);
713 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
714 if (IS_ERR(res->axi_s_reset))
715 return PTR_ERR(res->axi_s_reset);
717 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
718 if (IS_ERR(res->pipe_reset))
719 return PTR_ERR(res->pipe_reset);
721 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
723 if (IS_ERR(res->axi_m_vmid_reset))
724 return PTR_ERR(res->axi_m_vmid_reset);
726 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
728 if (IS_ERR(res->axi_s_xpu_reset))
729 return PTR_ERR(res->axi_s_xpu_reset);
731 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
732 if (IS_ERR(res->parf_reset))
733 return PTR_ERR(res->parf_reset);
735 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
736 if (IS_ERR(res->phy_reset))
737 return PTR_ERR(res->phy_reset);
739 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
741 if (IS_ERR(res->axi_m_sticky_reset))
742 return PTR_ERR(res->axi_m_sticky_reset);
744 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
746 if (IS_ERR(res->pipe_sticky_reset))
747 return PTR_ERR(res->pipe_sticky_reset);
749 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
750 if (IS_ERR(res->pwr_reset))
751 return PTR_ERR(res->pwr_reset);
753 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
754 if (IS_ERR(res->ahb_reset))
755 return PTR_ERR(res->ahb_reset);
757 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
758 if (IS_ERR(res->phy_ahb_reset))
759 return PTR_ERR(res->phy_ahb_reset);
764 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
766 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
768 reset_control_assert(res->axi_m_reset);
769 reset_control_assert(res->axi_s_reset);
770 reset_control_assert(res->pipe_reset);
771 reset_control_assert(res->pipe_sticky_reset);
772 reset_control_assert(res->phy_reset);
773 reset_control_assert(res->phy_ahb_reset);
774 reset_control_assert(res->axi_m_sticky_reset);
775 reset_control_assert(res->pwr_reset);
776 reset_control_assert(res->ahb_reset);
777 clk_disable_unprepare(res->aux_clk);
778 clk_disable_unprepare(res->master_clk);
779 clk_disable_unprepare(res->slave_clk);
782 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
784 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
785 struct dw_pcie *pci = pcie->pci;
786 struct device *dev = pci->dev;
790 ret = reset_control_assert(res->axi_m_reset);
792 dev_err(dev, "cannot assert axi master reset\n");
796 ret = reset_control_assert(res->axi_s_reset);
798 dev_err(dev, "cannot assert axi slave reset\n");
802 usleep_range(10000, 12000);
804 ret = reset_control_assert(res->pipe_reset);
806 dev_err(dev, "cannot assert pipe reset\n");
810 ret = reset_control_assert(res->pipe_sticky_reset);
812 dev_err(dev, "cannot assert pipe sticky reset\n");
816 ret = reset_control_assert(res->phy_reset);
818 dev_err(dev, "cannot assert phy reset\n");
822 ret = reset_control_assert(res->phy_ahb_reset);
824 dev_err(dev, "cannot assert phy ahb reset\n");
828 usleep_range(10000, 12000);
830 ret = reset_control_assert(res->axi_m_sticky_reset);
832 dev_err(dev, "cannot assert axi master sticky reset\n");
836 ret = reset_control_assert(res->pwr_reset);
838 dev_err(dev, "cannot assert power reset\n");
842 ret = reset_control_assert(res->ahb_reset);
844 dev_err(dev, "cannot assert ahb reset\n");
848 usleep_range(10000, 12000);
850 ret = reset_control_deassert(res->phy_ahb_reset);
852 dev_err(dev, "cannot deassert phy ahb reset\n");
856 ret = reset_control_deassert(res->phy_reset);
858 dev_err(dev, "cannot deassert phy reset\n");
862 ret = reset_control_deassert(res->pipe_reset);
864 dev_err(dev, "cannot deassert pipe reset\n");
868 ret = reset_control_deassert(res->pipe_sticky_reset);
870 dev_err(dev, "cannot deassert pipe sticky reset\n");
871 goto err_rst_pipe_sticky;
874 usleep_range(10000, 12000);
876 ret = reset_control_deassert(res->axi_m_reset);
878 dev_err(dev, "cannot deassert axi master reset\n");
882 ret = reset_control_deassert(res->axi_m_sticky_reset);
884 dev_err(dev, "cannot deassert axi master sticky reset\n");
885 goto err_rst_axi_m_sticky;
888 ret = reset_control_deassert(res->axi_s_reset);
890 dev_err(dev, "cannot deassert axi slave reset\n");
894 ret = reset_control_deassert(res->pwr_reset);
896 dev_err(dev, "cannot deassert power reset\n");
900 ret = reset_control_deassert(res->ahb_reset);
902 dev_err(dev, "cannot deassert ahb reset\n");
906 usleep_range(10000, 12000);
908 ret = clk_prepare_enable(res->aux_clk);
910 dev_err(dev, "cannot prepare/enable iface clock\n");
914 ret = clk_prepare_enable(res->master_clk);
916 dev_err(dev, "cannot prepare/enable core clock\n");
920 ret = clk_prepare_enable(res->slave_clk);
922 dev_err(dev, "cannot prepare/enable phy clock\n");
926 /* enable PCIe clocks and resets */
927 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
929 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
931 /* change DBI base address */
932 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
934 /* MAC PHY_POWERDOWN MUX DISABLE */
935 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
937 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
939 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
941 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
943 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
945 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
950 clk_disable_unprepare(res->master_clk);
952 clk_disable_unprepare(res->aux_clk);
954 reset_control_assert(res->ahb_reset);
956 reset_control_assert(res->pwr_reset);
958 reset_control_assert(res->axi_s_reset);
960 reset_control_assert(res->axi_m_sticky_reset);
961 err_rst_axi_m_sticky:
962 reset_control_assert(res->axi_m_reset);
964 reset_control_assert(res->pipe_sticky_reset);
966 reset_control_assert(res->pipe_reset);
968 reset_control_assert(res->phy_reset);
970 reset_control_assert(res->phy_ahb_reset);
974 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
976 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
977 struct dw_pcie *pci = pcie->pci;
978 struct device *dev = pci->dev;
980 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
981 "axi_m_sticky", "sticky",
984 res->iface = devm_clk_get(dev, "iface");
985 if (IS_ERR(res->iface))
986 return PTR_ERR(res->iface);
988 res->axi_m_clk = devm_clk_get(dev, "axi_m");
989 if (IS_ERR(res->axi_m_clk))
990 return PTR_ERR(res->axi_m_clk);
992 res->axi_s_clk = devm_clk_get(dev, "axi_s");
993 if (IS_ERR(res->axi_s_clk))
994 return PTR_ERR(res->axi_s_clk);
996 res->ahb_clk = devm_clk_get(dev, "ahb");
997 if (IS_ERR(res->ahb_clk))
998 return PTR_ERR(res->ahb_clk);
1000 res->aux_clk = devm_clk_get(dev, "aux");
1001 if (IS_ERR(res->aux_clk))
1002 return PTR_ERR(res->aux_clk);
1004 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
1005 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
1006 if (IS_ERR(res->rst[i]))
1007 return PTR_ERR(res->rst[i]);
1013 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
1015 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1017 clk_disable_unprepare(res->iface);
1018 clk_disable_unprepare(res->axi_m_clk);
1019 clk_disable_unprepare(res->axi_s_clk);
1020 clk_disable_unprepare(res->ahb_clk);
1021 clk_disable_unprepare(res->aux_clk);
1024 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
1026 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
1027 struct dw_pcie *pci = pcie->pci;
1028 struct device *dev = pci->dev;
1032 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1033 ret = reset_control_assert(res->rst[i]);
1035 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
1040 usleep_range(2000, 2500);
1042 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
1043 ret = reset_control_deassert(res->rst[i]);
1045 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
1052 * Don't have a way to see if the reset has completed.
1053 * Wait for some time.
1055 usleep_range(2000, 2500);
1057 ret = clk_prepare_enable(res->iface);
1059 dev_err(dev, "cannot prepare/enable core clock\n");
1063 ret = clk_prepare_enable(res->axi_m_clk);
1065 dev_err(dev, "cannot prepare/enable core clock\n");
1069 ret = clk_prepare_enable(res->axi_s_clk);
1071 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1075 ret = clk_prepare_enable(res->ahb_clk);
1077 dev_err(dev, "cannot prepare/enable ahb clock\n");
1081 ret = clk_prepare_enable(res->aux_clk);
1083 dev_err(dev, "cannot prepare/enable aux clock\n");
1087 writel(SLV_ADDR_SPACE_SZ,
1088 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1090 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1092 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1094 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1096 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1097 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1098 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1099 pcie->parf + PCIE20_PARF_SYS_CTRL);
1100 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1102 writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1103 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1104 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
1106 val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1107 val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1108 writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1110 writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1111 PCIE20_DEVICE_CONTROL2_STATUS2);
1116 clk_disable_unprepare(res->ahb_clk);
1118 clk_disable_unprepare(res->axi_s_clk);
1120 clk_disable_unprepare(res->axi_m_clk);
1122 clk_disable_unprepare(res->iface);
1125 * Not checking for failure, will anyway return
1126 * the original failure in 'ret'.
1128 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1129 reset_control_assert(res->rst[i]);
1134 static int qcom_pcie_link_up(struct dw_pcie *pci)
1136 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
1138 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1141 static int qcom_pcie_host_init(struct pcie_port *pp)
1143 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1144 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1147 qcom_ep_reset_assert(pcie);
1149 ret = pcie->ops->init(pcie);
1153 ret = phy_power_on(pcie->phy);
1157 if (pcie->ops->post_init) {
1158 ret = pcie->ops->post_init(pcie);
1160 goto err_disable_phy;
1163 dw_pcie_setup_rc(pp);
1165 if (IS_ENABLED(CONFIG_PCI_MSI))
1166 dw_pcie_msi_init(pp);
1168 qcom_ep_reset_deassert(pcie);
1170 ret = qcom_pcie_establish_link(pcie);
1176 qcom_ep_reset_assert(pcie);
1177 if (pcie->ops->post_deinit)
1178 pcie->ops->post_deinit(pcie);
1180 phy_power_off(pcie->phy);
1182 pcie->ops->deinit(pcie);
1187 static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
1190 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1192 /* the device class is not reported correctly from the register */
1193 if (where == PCI_CLASS_REVISION && size == 4) {
1194 *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
1195 *val &= 0xff; /* keep revision id */
1196 *val |= PCI_CLASS_BRIDGE_PCI << 16;
1197 return PCIBIOS_SUCCESSFUL;
1200 return dw_pcie_read(pci->dbi_base + where, size, val);
1203 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1204 .host_init = qcom_pcie_host_init,
1205 .rd_own_conf = qcom_pcie_rd_own_conf,
1208 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1209 static const struct qcom_pcie_ops ops_2_1_0 = {
1210 .get_resources = qcom_pcie_get_resources_2_1_0,
1211 .init = qcom_pcie_init_2_1_0,
1212 .deinit = qcom_pcie_deinit_2_1_0,
1213 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1216 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1217 static const struct qcom_pcie_ops ops_1_0_0 = {
1218 .get_resources = qcom_pcie_get_resources_1_0_0,
1219 .init = qcom_pcie_init_1_0_0,
1220 .deinit = qcom_pcie_deinit_1_0_0,
1221 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1224 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1225 static const struct qcom_pcie_ops ops_2_3_2 = {
1226 .get_resources = qcom_pcie_get_resources_2_3_2,
1227 .init = qcom_pcie_init_2_3_2,
1228 .post_init = qcom_pcie_post_init_2_3_2,
1229 .deinit = qcom_pcie_deinit_2_3_2,
1230 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1231 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1234 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1235 static const struct qcom_pcie_ops ops_2_4_0 = {
1236 .get_resources = qcom_pcie_get_resources_2_4_0,
1237 .init = qcom_pcie_init_2_4_0,
1238 .deinit = qcom_pcie_deinit_2_4_0,
1239 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1242 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1243 static const struct qcom_pcie_ops ops_2_3_3 = {
1244 .get_resources = qcom_pcie_get_resources_2_3_3,
1245 .init = qcom_pcie_init_2_3_3,
1246 .deinit = qcom_pcie_deinit_2_3_3,
1247 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1250 static const struct dw_pcie_ops dw_pcie_ops = {
1251 .link_up = qcom_pcie_link_up,
1254 static int qcom_pcie_probe(struct platform_device *pdev)
1256 struct device *dev = &pdev->dev;
1257 struct resource *res;
1258 struct pcie_port *pp;
1259 struct dw_pcie *pci;
1260 struct qcom_pcie *pcie;
1263 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1267 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1271 pm_runtime_enable(dev);
1272 ret = pm_runtime_get_sync(dev);
1274 pm_runtime_disable(dev);
1279 pci->ops = &dw_pcie_ops;
1284 pcie->ops = of_device_get_match_data(dev);
1286 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1287 if (IS_ERR(pcie->reset)) {
1288 ret = PTR_ERR(pcie->reset);
1289 goto err_pm_runtime_put;
1292 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
1293 pcie->parf = devm_ioremap_resource(dev, res);
1294 if (IS_ERR(pcie->parf)) {
1295 ret = PTR_ERR(pcie->parf);
1296 goto err_pm_runtime_put;
1299 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1300 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1301 if (IS_ERR(pci->dbi_base)) {
1302 ret = PTR_ERR(pci->dbi_base);
1303 goto err_pm_runtime_put;
1306 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
1307 pcie->elbi = devm_ioremap_resource(dev, res);
1308 if (IS_ERR(pcie->elbi)) {
1309 ret = PTR_ERR(pcie->elbi);
1310 goto err_pm_runtime_put;
1313 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1314 if (IS_ERR(pcie->phy)) {
1315 ret = PTR_ERR(pcie->phy);
1316 goto err_pm_runtime_put;
1319 ret = pcie->ops->get_resources(pcie);
1321 goto err_pm_runtime_put;
1323 pp->ops = &qcom_pcie_dw_ops;
1325 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1326 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1327 if (pp->msi_irq < 0) {
1329 goto err_pm_runtime_put;
1333 ret = phy_init(pcie->phy);
1335 goto err_pm_runtime_put;
1337 platform_set_drvdata(pdev, pcie);
1339 ret = dw_pcie_host_init(pp);
1341 dev_err(dev, "cannot initialize host\n");
1348 phy_exit(pcie->phy);
1350 pm_runtime_put(dev);
1351 pm_runtime_disable(dev);
1356 static const struct of_device_id qcom_pcie_match[] = {
1357 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1358 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1359 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1360 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1361 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1362 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1366 static struct platform_driver qcom_pcie_driver = {
1367 .probe = qcom_pcie_probe,
1369 .name = "qcom-pcie",
1370 .suppress_bind_attrs = true,
1371 .of_match_table = qcom_pcie_match,
1374 builtin_platform_driver(qcom_pcie_driver);