1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Author: Jingoo Han <jg1.han@samsung.com>
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/of_address.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci_regs.h>
16 #include <linux/platform_device.h>
18 #include "../../pci.h"
19 #include "pcie-designware.h"
21 static struct pci_ops dw_pcie_ops;
23 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
28 if (pp->ops->rd_own_conf)
29 return pp->ops->rd_own_conf(pp, where, size, val);
31 pci = to_dw_pcie_from_pp(pp);
32 return dw_pcie_read(pci->dbi_base + where, size, val);
35 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
40 if (pp->ops->wr_own_conf)
41 return pp->ops->wr_own_conf(pp, where, size, val);
43 pci = to_dw_pcie_from_pp(pp);
44 return dw_pcie_write(pci->dbi_base + where, size, val);
47 static void dw_msi_ack_irq(struct irq_data *d)
49 irq_chip_ack_parent(d);
52 static void dw_msi_mask_irq(struct irq_data *d)
55 irq_chip_mask_parent(d);
58 static void dw_msi_unmask_irq(struct irq_data *d)
60 pci_msi_unmask_irq(d);
61 irq_chip_unmask_parent(d);
64 static struct irq_chip dw_pcie_msi_irq_chip = {
66 .irq_ack = dw_msi_ack_irq,
67 .irq_mask = dw_msi_mask_irq,
68 .irq_unmask = dw_msi_unmask_irq,
71 static struct msi_domain_info dw_pcie_msi_domain_info = {
72 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
73 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
74 .chip = &dw_pcie_msi_irq_chip,
78 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
82 u32 status, num_ctrls;
83 irqreturn_t ret = IRQ_NONE;
85 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
87 for (i = 0; i < num_ctrls; i++) {
88 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
89 (i * MSI_REG_CTRL_BLOCK_SIZE),
97 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
98 pos)) != MAX_MSI_IRQS_PER_CTRL) {
99 irq = irq_find_mapping(pp->irq_domain,
100 (i * MAX_MSI_IRQS_PER_CTRL) +
102 generic_handle_irq(irq);
110 /* Chained MSI interrupt service routine */
111 static void dw_chained_msi_isr(struct irq_desc *desc)
113 struct irq_chip *chip = irq_desc_get_chip(desc);
114 struct pcie_port *pp;
116 chained_irq_enter(chip, desc);
118 pp = irq_desc_get_handler_data(desc);
119 dw_handle_msi_irq(pp);
121 chained_irq_exit(chip, desc);
124 static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg)
126 struct pcie_port *pp = irq_data_get_irq_chip_data(data);
127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
130 if (pp->ops->get_msi_addr)
131 msi_target = pp->ops->get_msi_addr(pp);
133 msi_target = (u64)pp->msi_data;
135 msg->address_lo = lower_32_bits(msi_target);
136 msg->address_hi = upper_32_bits(msi_target);
138 if (pp->ops->get_msi_data)
139 msg->data = pp->ops->get_msi_data(pp, data->hwirq);
141 msg->data = data->hwirq;
143 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
144 (int)data->hwirq, msg->address_hi, msg->address_lo);
147 static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
148 const struct cpumask *mask, bool force)
153 static void dw_pci_bottom_mask(struct irq_data *data)
155 struct pcie_port *pp = irq_data_get_irq_chip_data(data);
156 unsigned int res, bit, ctrl;
159 raw_spin_lock_irqsave(&pp->lock, flags);
161 if (pp->ops->msi_clear_irq) {
162 pp->ops->msi_clear_irq(pp, data->hwirq);
164 ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
165 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
166 bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
168 pp->irq_status[ctrl] &= ~(1 << bit);
169 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
170 ~pp->irq_status[ctrl]);
173 raw_spin_unlock_irqrestore(&pp->lock, flags);
176 static void dw_pci_bottom_unmask(struct irq_data *data)
178 struct pcie_port *pp = irq_data_get_irq_chip_data(data);
179 unsigned int res, bit, ctrl;
182 raw_spin_lock_irqsave(&pp->lock, flags);
184 if (pp->ops->msi_set_irq) {
185 pp->ops->msi_set_irq(pp, data->hwirq);
187 ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
188 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
189 bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
191 pp->irq_status[ctrl] |= 1 << bit;
192 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
193 ~pp->irq_status[ctrl]);
196 raw_spin_unlock_irqrestore(&pp->lock, flags);
199 static void dw_pci_bottom_ack(struct irq_data *d)
201 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
202 unsigned int res, bit, ctrl;
205 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
206 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
207 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
209 raw_spin_lock_irqsave(&pp->lock, flags);
211 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit);
213 if (pp->ops->msi_irq_ack)
214 pp->ops->msi_irq_ack(d->hwirq, pp);
216 raw_spin_unlock_irqrestore(&pp->lock, flags);
219 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
221 .irq_ack = dw_pci_bottom_ack,
222 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
223 .irq_set_affinity = dw_pci_msi_set_affinity,
224 .irq_mask = dw_pci_bottom_mask,
225 .irq_unmask = dw_pci_bottom_unmask,
228 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
229 unsigned int virq, unsigned int nr_irqs,
232 struct pcie_port *pp = domain->host_data;
237 raw_spin_lock_irqsave(&pp->lock, flags);
239 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
240 order_base_2(nr_irqs));
242 raw_spin_unlock_irqrestore(&pp->lock, flags);
247 for (i = 0; i < nr_irqs; i++)
248 irq_domain_set_info(domain, virq + i, bit + i,
249 &dw_pci_msi_bottom_irq_chip,
256 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
257 unsigned int virq, unsigned int nr_irqs)
259 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
260 struct pcie_port *pp = irq_data_get_irq_chip_data(data);
263 raw_spin_lock_irqsave(&pp->lock, flags);
265 bitmap_release_region(pp->msi_irq_in_use, data->hwirq,
266 order_base_2(nr_irqs));
268 raw_spin_unlock_irqrestore(&pp->lock, flags);
271 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
272 .alloc = dw_pcie_irq_domain_alloc,
273 .free = dw_pcie_irq_domain_free,
276 int dw_pcie_allocate_domains(struct pcie_port *pp)
278 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
279 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
281 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
282 &dw_pcie_msi_domain_ops, pp);
283 if (!pp->irq_domain) {
284 dev_err(pci->dev, "Failed to create IRQ domain\n");
288 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
290 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
291 &dw_pcie_msi_domain_info,
293 if (!pp->msi_domain) {
294 dev_err(pci->dev, "Failed to create MSI domain\n");
295 irq_domain_remove(pp->irq_domain);
302 void dw_pcie_free_msi(struct pcie_port *pp)
304 irq_set_chained_handler(pp->msi_irq, NULL);
305 irq_set_handler_data(pp->msi_irq, NULL);
307 irq_domain_remove(pp->msi_domain);
308 irq_domain_remove(pp->irq_domain);
311 __free_page(pp->msi_page);
314 void dw_pcie_msi_init(struct pcie_port *pp)
316 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
317 struct device *dev = pci->dev;
320 pp->msi_page = alloc_page(GFP_KERNEL);
321 pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
323 if (dma_mapping_error(dev, pp->msi_data)) {
324 dev_err(dev, "Failed to map MSI data\n");
325 __free_page(pp->msi_page);
329 msi_target = (u64)pp->msi_data;
331 /* Program the msi_data */
332 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
333 lower_32_bits(msi_target));
334 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
335 upper_32_bits(msi_target));
338 int dw_pcie_host_init(struct pcie_port *pp)
340 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
341 struct device *dev = pci->dev;
342 struct device_node *np = dev->of_node;
343 struct platform_device *pdev = to_platform_device(dev);
344 struct resource_entry *win, *tmp;
345 struct pci_bus *bus, *child;
346 struct pci_host_bridge *bridge;
347 struct resource *cfg_res;
350 raw_spin_lock_init(&pci->pp.lock);
352 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
354 pp->cfg0_size = resource_size(cfg_res) >> 1;
355 pp->cfg1_size = resource_size(cfg_res) >> 1;
356 pp->cfg0_base = cfg_res->start;
357 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
358 } else if (!pp->va_cfg0_base) {
359 dev_err(dev, "Missing *config* reg space\n");
362 bridge = devm_pci_alloc_host_bridge(dev, 0);
366 ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
367 &bridge->windows, &pp->io_base);
371 ret = devm_request_pci_bus_resources(dev, &bridge->windows);
375 /* Get the I/O and memory ranges from DT */
376 resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
377 switch (resource_type(win->res)) {
379 ret = devm_pci_remap_iospace(dev, win->res,
382 dev_warn(dev, "Error %d: failed to map resource %pR\n",
384 resource_list_destroy_entry(win);
387 pp->io->name = "I/O";
388 pp->io_size = resource_size(pp->io);
389 pp->io_bus_addr = pp->io->start - win->offset;
394 pp->mem->name = "MEM";
395 pp->mem_size = resource_size(pp->mem);
396 pp->mem_bus_addr = pp->mem->start - win->offset;
400 pp->cfg0_size = resource_size(pp->cfg) >> 1;
401 pp->cfg1_size = resource_size(pp->cfg) >> 1;
402 pp->cfg0_base = pp->cfg->start;
403 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
411 if (!pci->dbi_base) {
412 pci->dbi_base = devm_pci_remap_cfgspace(dev,
414 resource_size(pp->cfg));
415 if (!pci->dbi_base) {
416 dev_err(dev, "Error with ioremap\n");
421 pp->mem_base = pp->mem->start;
423 if (!pp->va_cfg0_base) {
424 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
425 pp->cfg0_base, pp->cfg0_size);
426 if (!pp->va_cfg0_base) {
427 dev_err(dev, "Error with ioremap in function\n");
432 if (!pp->va_cfg1_base) {
433 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
436 if (!pp->va_cfg1_base) {
437 dev_err(dev, "Error with ioremap\n");
442 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
444 pci->num_viewport = 2;
446 if (pci_msi_enabled()) {
448 * If a specific SoC driver needs to change the
449 * default number of vectors, it needs to implement
450 * the set_num_vectors callback.
452 if (!pp->ops->set_num_vectors) {
453 pp->num_vectors = MSI_DEF_NUM_VECTORS;
455 pp->ops->set_num_vectors(pp);
457 if (pp->num_vectors > MAX_MSI_IRQS ||
458 pp->num_vectors == 0) {
460 "Invalid number of vectors\n");
465 if (!pp->ops->msi_host_init) {
466 ret = dw_pcie_allocate_domains(pp);
471 irq_set_chained_handler_and_data(pp->msi_irq,
475 ret = pp->ops->msi_host_init(pp);
481 if (pp->ops->host_init) {
482 ret = pp->ops->host_init(pp);
487 pp->root_bus_nr = pp->busn->start;
489 bridge->dev.parent = dev;
490 bridge->sysdata = pp;
491 bridge->busnr = pp->root_bus_nr;
492 bridge->ops = &dw_pcie_ops;
493 bridge->map_irq = of_irq_parse_and_map_pci;
494 bridge->swizzle_irq = pci_common_swizzle;
496 ret = pci_scan_root_bus_bridge(bridge);
502 if (pp->ops->scan_bus)
503 pp->ops->scan_bus(pp);
505 pci_bus_size_bridges(bus);
506 pci_bus_assign_resources(bus);
508 list_for_each_entry(child, &bus->children, node)
509 pcie_bus_configure_settings(child);
511 pci_bus_add_devices(bus);
515 if (pci_msi_enabled() && !pp->ops->msi_host_init)
516 dw_pcie_free_msi(pp);
520 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
521 u32 devfn, int where, int size, u32 *val)
524 u32 busdev, cfg_size;
526 void __iomem *va_cfg_base;
527 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
529 if (pp->ops->rd_other_conf)
530 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
532 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
533 PCIE_ATU_FUNC(PCI_FUNC(devfn));
535 if (bus->parent->number == pp->root_bus_nr) {
536 type = PCIE_ATU_TYPE_CFG0;
537 cpu_addr = pp->cfg0_base;
538 cfg_size = pp->cfg0_size;
539 va_cfg_base = pp->va_cfg0_base;
541 type = PCIE_ATU_TYPE_CFG1;
542 cpu_addr = pp->cfg1_base;
543 cfg_size = pp->cfg1_size;
544 va_cfg_base = pp->va_cfg1_base;
547 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
550 ret = dw_pcie_read(va_cfg_base + where, size, val);
551 if (pci->num_viewport <= 2)
552 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
553 PCIE_ATU_TYPE_IO, pp->io_base,
554 pp->io_bus_addr, pp->io_size);
559 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
560 u32 devfn, int where, int size, u32 val)
563 u32 busdev, cfg_size;
565 void __iomem *va_cfg_base;
566 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
568 if (pp->ops->wr_other_conf)
569 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
571 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
572 PCIE_ATU_FUNC(PCI_FUNC(devfn));
574 if (bus->parent->number == pp->root_bus_nr) {
575 type = PCIE_ATU_TYPE_CFG0;
576 cpu_addr = pp->cfg0_base;
577 cfg_size = pp->cfg0_size;
578 va_cfg_base = pp->va_cfg0_base;
580 type = PCIE_ATU_TYPE_CFG1;
581 cpu_addr = pp->cfg1_base;
582 cfg_size = pp->cfg1_size;
583 va_cfg_base = pp->va_cfg1_base;
586 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
589 ret = dw_pcie_write(va_cfg_base + where, size, val);
590 if (pci->num_viewport <= 2)
591 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
592 PCIE_ATU_TYPE_IO, pp->io_base,
593 pp->io_bus_addr, pp->io_size);
598 static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
601 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
603 /* If there is no link, then there is no device */
604 if (bus->number != pp->root_bus_nr) {
605 if (!dw_pcie_link_up(pci))
609 /* Access only one slot on each root port */
610 if (bus->number == pp->root_bus_nr && dev > 0)
616 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
619 struct pcie_port *pp = bus->sysdata;
621 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
623 return PCIBIOS_DEVICE_NOT_FOUND;
626 if (bus->number == pp->root_bus_nr)
627 return dw_pcie_rd_own_conf(pp, where, size, val);
629 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
632 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
633 int where, int size, u32 val)
635 struct pcie_port *pp = bus->sysdata;
637 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
638 return PCIBIOS_DEVICE_NOT_FOUND;
640 if (bus->number == pp->root_bus_nr)
641 return dw_pcie_wr_own_conf(pp, where, size, val);
643 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
646 static struct pci_ops dw_pcie_ops = {
647 .read = dw_pcie_rd_conf,
648 .write = dw_pcie_wr_conf,
651 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
655 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
656 if (val == 0xffffffff)
662 void dw_pcie_setup_rc(struct pcie_port *pp)
664 u32 val, ctrl, num_ctrls;
665 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
669 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
671 /* Initialize IRQ Status array */
672 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
673 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
674 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
676 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
677 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
679 pp->irq_status[ctrl] = 0;
683 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
684 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
686 /* Setup interrupt pins */
687 dw_pcie_dbi_ro_wr_en(pci);
688 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
691 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
692 dw_pcie_dbi_ro_wr_dis(pci);
694 /* Setup bus numbers */
695 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
698 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
700 /* Setup command register */
701 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
703 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
704 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
705 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
708 * If the platform provides ->rd_other_conf, it means the platform
709 * uses its own address translation component rather than ATU, so
710 * we should not program the ATU here.
712 if (!pp->ops->rd_other_conf) {
713 /* Get iATU unroll support */
714 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
715 dev_dbg(pci->dev, "iATU unroll: %s\n",
716 pci->iatu_unroll_enabled ? "enabled" : "disabled");
718 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
719 PCIE_ATU_TYPE_MEM, pp->mem_base,
720 pp->mem_bus_addr, pp->mem_size);
721 if (pci->num_viewport > 2)
722 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
723 PCIE_ATU_TYPE_IO, pp->io_base,
724 pp->io_bus_addr, pp->io_size);
727 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
729 /* Enable write permission for the DBI read-only register */
730 dw_pcie_dbi_ro_wr_en(pci);
731 /* Program correct class for RC */
732 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
733 /* Better disable write permission right after the update */
734 dw_pcie_dbi_ro_wr_dis(pci);
736 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
737 val |= PORT_LOGIC_SPEED_CHANGE;
738 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);