1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
4 * such as Graviton and Alpine)
6 * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
8 * Author: Jonathan Chocron <jonnyc@amazon.com>
11 #include <linux/pci.h>
12 #include <linux/pci-ecam.h>
13 #include <linux/pci-acpi.h>
14 #include "../../pci.h"
16 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
19 void __iomem *dbi_base;
22 static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
25 struct pci_config_window *cfg = bus->sysdata;
26 struct al_pcie_acpi *pcie = cfg->priv;
27 void __iomem *dbi_base = pcie->dbi_base;
29 if (bus->number == cfg->busr.start) {
31 * The DW PCIe core doesn't filter out transactions to other
32 * devices/functions on the root bus num, so we do this here.
34 if (PCI_SLOT(devfn) > 0)
37 return dbi_base + where;
40 return pci_ecam_map_bus(bus, devfn, where);
43 static int al_pcie_init(struct pci_config_window *cfg)
45 struct device *dev = cfg->parent;
46 struct acpi_device *adev = to_acpi_device(dev);
47 struct acpi_pci_root *root = acpi_driver_data(adev);
48 struct al_pcie_acpi *al_pcie;
52 al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
56 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
60 ret = acpi_get_rc_resources(dev, "AMZN0001", root->segment, res);
62 dev_err(dev, "can't get rc dbi base address for SEG %d\n",
67 dev_dbg(dev, "Root port dbi res: %pR\n", res);
69 al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res);
70 if (IS_ERR(al_pcie->dbi_base))
71 return PTR_ERR(al_pcie->dbi_base);
78 const struct pci_ecam_ops al_pcie_ops = {
82 .map_bus = al_pcie_map_bus,
83 .read = pci_generic_config_read,
84 .write = pci_generic_config_write,
88 #endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
92 #include <linux/of_pci.h>
93 #include "pcie-designware.h"
95 #define AL_PCIE_REV_ID_2 2
96 #define AL_PCIE_REV_ID_3 3
97 #define AL_PCIE_REV_ID_4 4
99 #define AXI_BASE_OFFSET 0x0
101 #define DEVICE_ID_OFFSET 0x16c
103 #define DEVICE_REV_ID 0x0
104 #define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
106 #define DEVICE_REV_ID_DEV_ID_X4 0
107 #define DEVICE_REV_ID_DEV_ID_X8 2
108 #define DEVICE_REV_ID_DEV_ID_X16 4
110 #define OB_CTRL_REV1_2_OFFSET 0x0040
111 #define OB_CTRL_REV3_5_OFFSET 0x0030
113 #define CFG_TARGET_BUS 0x0
114 #define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
115 #define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
117 #define CFG_CONTROL 0x4
118 #define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
119 #define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
121 struct al_pcie_reg_offsets {
122 unsigned int ob_ctrl;
125 struct al_pcie_target_bus_cfg {
133 void __iomem *controller_base; /* base of PCIe unit (not DW core) */
135 resource_size_t ecam_size;
136 unsigned int controller_rev_id;
137 struct al_pcie_reg_offsets reg_offsets;
138 struct al_pcie_target_bus_cfg target_bus_cfg;
141 #define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
143 #define to_al_pcie(x) dev_get_drvdata((x)->dev)
145 static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset)
147 return readl_relaxed(pcie->controller_base + offset);
150 static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset,
153 writel_relaxed(val, pcie->controller_base + offset);
156 static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
161 dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET +
164 dev_id_val = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK, dev_rev_id_val);
166 switch (dev_id_val) {
167 case DEVICE_REV_ID_DEV_ID_X4:
168 *rev_id = AL_PCIE_REV_ID_2;
170 case DEVICE_REV_ID_DEV_ID_X8:
171 *rev_id = AL_PCIE_REV_ID_3;
173 case DEVICE_REV_ID_DEV_ID_X16:
174 *rev_id = AL_PCIE_REV_ID_4;
177 dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n",
182 dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val);
187 static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
189 switch (pcie->controller_rev_id) {
190 case AL_PCIE_REV_ID_2:
191 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
193 case AL_PCIE_REV_ID_3:
194 case AL_PCIE_REV_ID_4:
195 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
198 dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
199 pcie->controller_rev_id);
206 static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
212 reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
213 FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
215 al_pcie_controller_writel(pcie, AXI_BASE_OFFSET +
216 pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,
220 static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus,
221 unsigned int devfn, int where)
223 struct pcie_port *pp = bus->sysdata;
224 struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
225 unsigned int busnr = bus->number;
226 struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
227 unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
228 unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
229 void __iomem *pci_base_addr;
231 pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
233 PCIE_ECAM_DEVFN(devfn));
235 if (busnr_reg != target_bus_cfg->reg_val) {
236 dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
237 target_bus_cfg->reg_val, busnr_reg);
238 target_bus_cfg->reg_val = busnr_reg;
239 al_pcie_target_bus_set(pcie,
240 target_bus_cfg->reg_val,
241 target_bus_cfg->reg_mask);
244 return pci_base_addr + where;
247 static struct pci_ops al_child_pci_ops = {
248 .map_bus = al_pcie_conf_addr_map_bus,
249 .read = pci_generic_config_read,
250 .write = pci_generic_config_write,
253 static void al_pcie_config_prepare(struct al_pcie *pcie)
255 struct al_pcie_target_bus_cfg *target_bus_cfg;
256 struct pcie_port *pp = &pcie->pci->pp;
257 unsigned int ecam_bus_mask;
258 u32 cfg_control_offset;
263 struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;
265 target_bus_cfg = &pcie->target_bus_cfg;
267 ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
268 if (ecam_bus_mask > 255) {
269 dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
273 /* This portion is taken from the transaction address */
274 target_bus_cfg->ecam_mask = ecam_bus_mask;
275 /* This portion is taken from the cfg_target_bus reg */
276 target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
277 target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;
279 al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
280 target_bus_cfg->reg_mask);
282 secondary_bus = bus->start + 1;
283 subordinate_bus = bus->end;
285 /* Set the valid values of secondary and subordinate buses */
286 cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
289 cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
292 ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
294 reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
295 FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
297 al_pcie_controller_writel(pcie, cfg_control_offset, reg);
300 static int al_pcie_host_init(struct pcie_port *pp)
302 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
303 struct al_pcie *pcie = to_al_pcie(pci);
306 pp->bridge->child_ops = &al_child_pci_ops;
308 rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
312 rc = al_pcie_reg_offsets_set(pcie);
316 al_pcie_config_prepare(pcie);
321 static const struct dw_pcie_host_ops al_pcie_host_ops = {
322 .host_init = al_pcie_host_init,
325 static int al_add_pcie_port(struct pcie_port *pp,
326 struct platform_device *pdev)
328 struct device *dev = &pdev->dev;
331 pp->ops = &al_pcie_host_ops;
333 ret = dw_pcie_host_init(pp);
335 dev_err(dev, "failed to initialize host\n");
342 static const struct dw_pcie_ops dw_pcie_ops = {
345 static int al_pcie_probe(struct platform_device *pdev)
347 struct device *dev = &pdev->dev;
348 struct resource *controller_res;
349 struct resource *ecam_res;
350 struct resource *dbi_res;
351 struct al_pcie *al_pcie;
354 al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
358 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
363 pci->ops = &dw_pcie_ops;
368 dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
369 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
370 if (IS_ERR(pci->dbi_base))
371 return PTR_ERR(pci->dbi_base);
373 ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
375 dev_err(dev, "couldn't find 'config' reg in DT\n");
378 al_pcie->ecam_size = resource_size(ecam_res);
380 controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
382 al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
383 if (IS_ERR(al_pcie->controller_base)) {
384 dev_err(dev, "couldn't remap controller base %pR\n",
386 return PTR_ERR(al_pcie->controller_base);
389 dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
390 dbi_res, controller_res);
392 platform_set_drvdata(pdev, al_pcie);
394 return al_add_pcie_port(&pci->pp, pdev);
397 static const struct of_device_id al_pcie_of_match[] = {
398 { .compatible = "amazon,al-alpine-v2-pcie",
400 { .compatible = "amazon,al-alpine-v3-pcie",
405 static struct platform_driver al_pcie_driver = {
408 .of_match_table = al_pcie_of_match,
409 .suppress_bind_attrs = true,
411 .probe = al_pcie_probe,
413 builtin_platform_driver(al_pcie_driver);
415 #endif /* CONFIG_PCIE_AL*/