1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
9 #include <linux/delay.h>
10 #include <linux/gpio/consumer.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of_device.h>
16 #include <linux/of_irq.h>
17 #include <linux/pci.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
21 #include "../../pci.h"
22 #include "pcie-cadence.h"
24 #define ENABLE_REG_SYS_2 0x108
25 #define STATUS_REG_SYS_2 0x508
26 #define STATUS_CLR_REG_SYS_2 0x708
27 #define LINK_DOWN BIT(1)
28 #define J7200_LINK_DOWN BIT(10)
30 #define J721E_PCIE_USER_CMD_STATUS 0x4
31 #define LINK_TRAINING_ENABLE BIT(0)
33 #define J721E_PCIE_USER_LINKSTATUS 0x14
34 #define LINK_STATUS GENMASK(1, 0)
37 NO_RECEIVERS_DETECTED,
38 LINK_TRAINING_IN_PROGRESS,
39 LINK_UP_DL_IN_PROGRESS,
43 #define J721E_MODE_RC BIT(7)
44 #define LANE_COUNT_MASK BIT(8)
45 #define LANE_COUNT(n) ((n) << 8)
47 #define GENERATION_SEL_MASK GENMASK(1, 0)
55 struct cdns_pcie *cdns_pcie;
56 void __iomem *user_cfg_base;
57 void __iomem *intd_cfg_base;
58 u32 linkdown_irq_regfield;
61 enum j721e_pcie_mode {
66 struct j721e_pcie_data {
67 enum j721e_pcie_mode mode;
68 unsigned int quirk_retrain_flag:1;
69 unsigned int quirk_detect_quiet_flag:1;
70 u32 linkdown_irq_regfield;
71 unsigned int byte_access_allowed:1;
74 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
76 return readl(pcie->user_cfg_base + offset);
79 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
82 writel(value, pcie->user_cfg_base + offset);
85 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
87 return readl(pcie->intd_cfg_base + offset);
90 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
93 writel(value, pcie->intd_cfg_base + offset);
96 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
98 struct j721e_pcie *pcie = priv;
99 struct device *dev = pcie->dev;
102 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
103 if (!(reg & pcie->linkdown_irq_regfield))
106 dev_err(dev, "LINK DOWN!\n");
108 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
112 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
116 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
117 reg |= pcie->linkdown_irq_regfield;
118 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
121 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
123 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
126 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
127 reg |= LINK_TRAINING_ENABLE;
128 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
133 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
135 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
138 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
139 reg &= ~LINK_TRAINING_ENABLE;
140 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
143 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
145 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
148 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
150 if (reg == LINK_UP_DL_COMPLETED)
156 static const struct cdns_pcie_ops j721e_pcie_ops = {
157 .start_link = j721e_pcie_start_link,
158 .stop_link = j721e_pcie_stop_link,
159 .link_up = j721e_pcie_link_up,
162 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
164 struct device *dev = pcie->dev;
165 u32 mask = J721E_MODE_RC;
166 u32 mode = pcie->mode;
170 if (mode == PCI_MODE_RC)
173 ret = regmap_update_bits(syscon, 0, mask, val);
175 dev_err(dev, "failed to set pcie mode\n");
180 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
181 struct regmap *syscon)
183 struct device *dev = pcie->dev;
184 struct device_node *np = dev->of_node;
189 link_speed = of_pci_get_max_link_speed(np);
193 val = link_speed - 1;
194 ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);
196 dev_err(dev, "failed to set link speed\n");
201 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
202 struct regmap *syscon)
204 struct device *dev = pcie->dev;
205 u32 lanes = pcie->num_lanes;
209 val = LANE_COUNT(lanes - 1);
210 ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);
212 dev_err(dev, "failed to set link count\n");
217 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
219 struct device *dev = pcie->dev;
220 struct device_node *node = dev->of_node;
221 struct regmap *syscon;
224 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
225 if (IS_ERR(syscon)) {
226 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
227 return PTR_ERR(syscon);
230 ret = j721e_pcie_set_mode(pcie, syscon);
232 dev_err(dev, "Failed to set pci mode\n");
236 ret = j721e_pcie_set_link_speed(pcie, syscon);
238 dev_err(dev, "Failed to set link speed\n");
242 ret = j721e_pcie_set_lane_count(pcie, syscon);
244 dev_err(dev, "Failed to set num-lanes\n");
251 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
252 int where, int size, u32 *value)
254 if (pci_is_root_bus(bus))
255 return pci_generic_config_read32(bus, devfn, where, size,
258 return pci_generic_config_read(bus, devfn, where, size, value);
261 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
262 int where, int size, u32 value)
264 if (pci_is_root_bus(bus))
265 return pci_generic_config_write32(bus, devfn, where, size,
268 return pci_generic_config_write(bus, devfn, where, size, value);
271 static struct pci_ops cdns_ti_pcie_host_ops = {
272 .map_bus = cdns_pci_map_bus,
273 .read = cdns_ti_pcie_config_read,
274 .write = cdns_ti_pcie_config_write,
277 static const struct j721e_pcie_data j721e_pcie_rc_data = {
279 .quirk_retrain_flag = true,
280 .byte_access_allowed = false,
281 .linkdown_irq_regfield = LINK_DOWN,
284 static const struct j721e_pcie_data j721e_pcie_ep_data = {
286 .linkdown_irq_regfield = LINK_DOWN,
289 static const struct j721e_pcie_data j7200_pcie_rc_data = {
291 .quirk_detect_quiet_flag = true,
292 .linkdown_irq_regfield = J7200_LINK_DOWN,
293 .byte_access_allowed = true,
296 static const struct j721e_pcie_data j7200_pcie_ep_data = {
298 .quirk_detect_quiet_flag = true,
301 static const struct j721e_pcie_data am64_pcie_rc_data = {
303 .linkdown_irq_regfield = J7200_LINK_DOWN,
304 .byte_access_allowed = true,
307 static const struct j721e_pcie_data am64_pcie_ep_data = {
309 .linkdown_irq_regfield = J7200_LINK_DOWN,
312 static const struct of_device_id of_j721e_pcie_match[] = {
314 .compatible = "ti,j721e-pcie-host",
315 .data = &j721e_pcie_rc_data,
318 .compatible = "ti,j721e-pcie-ep",
319 .data = &j721e_pcie_ep_data,
322 .compatible = "ti,j7200-pcie-host",
323 .data = &j7200_pcie_rc_data,
326 .compatible = "ti,j7200-pcie-ep",
327 .data = &j7200_pcie_ep_data,
330 .compatible = "ti,am64-pcie-host",
331 .data = &am64_pcie_rc_data,
334 .compatible = "ti,am64-pcie-ep",
335 .data = &am64_pcie_ep_data,
340 static int j721e_pcie_probe(struct platform_device *pdev)
342 struct device *dev = &pdev->dev;
343 struct device_node *node = dev->of_node;
344 struct pci_host_bridge *bridge;
345 struct j721e_pcie_data *data;
346 struct cdns_pcie *cdns_pcie;
347 struct j721e_pcie *pcie;
348 struct cdns_pcie_rc *rc;
349 struct cdns_pcie_ep *ep;
350 struct gpio_desc *gpiod;
357 data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
361 mode = (u32)data->mode;
363 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
369 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
371 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
373 return PTR_ERR(base);
374 pcie->intd_cfg_base = base;
376 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
378 return PTR_ERR(base);
379 pcie->user_cfg_base = base;
381 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
382 if (ret || num_lanes > MAX_LANES)
384 pcie->num_lanes = num_lanes;
386 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
389 irq = platform_get_irq_byname(pdev, "link_state");
393 dev_set_drvdata(dev, pcie);
394 pm_runtime_enable(dev);
395 ret = pm_runtime_get_sync(dev);
397 dev_err(dev, "pm_runtime_get_sync failed\n");
401 ret = j721e_pcie_ctrl_init(pcie);
403 dev_err(dev, "pm_runtime_get_sync failed\n");
407 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
408 "j721e-pcie-link-down-irq", pcie);
410 dev_err(dev, "failed to request link state IRQ %d\n", irq);
414 j721e_pcie_config_link_irq(pcie);
418 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) {
423 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
429 if (!data->byte_access_allowed)
430 bridge->ops = &cdns_ti_pcie_host_ops;
431 rc = pci_host_bridge_priv(bridge);
432 rc->quirk_retrain_flag = data->quirk_retrain_flag;
433 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
435 cdns_pcie = &rc->pcie;
436 cdns_pcie->dev = dev;
437 cdns_pcie->ops = &j721e_pcie_ops;
438 pcie->cdns_pcie = cdns_pcie;
440 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
442 ret = PTR_ERR(gpiod);
443 if (ret != -EPROBE_DEFER)
444 dev_err(dev, "Failed to get reset GPIO\n");
448 ret = cdns_pcie_init_phy(dev, cdns_pcie);
450 dev_err(dev, "Failed to init phy\n");
455 * "Power Sequencing and Reset Signal Timings" table in
456 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
457 * indicates PERST# should be deasserted after minimum of 100us
458 * once REFCLK is stable. The REFCLK to the connector in RC
459 * mode is selected while enabling the PHY. So deassert PERST#
463 usleep_range(100, 200);
464 gpiod_set_value_cansleep(gpiod, 1);
467 ret = cdns_pcie_host_setup(rc);
473 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) {
478 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
483 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
485 cdns_pcie = &ep->pcie;
486 cdns_pcie->dev = dev;
487 cdns_pcie->ops = &j721e_pcie_ops;
488 pcie->cdns_pcie = cdns_pcie;
490 ret = cdns_pcie_init_phy(dev, cdns_pcie);
492 dev_err(dev, "Failed to init phy\n");
496 ret = cdns_pcie_ep_setup(ep);
502 dev_err(dev, "INVALID device type %d\n", mode);
508 cdns_pcie_disable_phy(cdns_pcie);
512 pm_runtime_disable(dev);
517 static int j721e_pcie_remove(struct platform_device *pdev)
519 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
520 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
521 struct device *dev = &pdev->dev;
523 cdns_pcie_disable_phy(cdns_pcie);
525 pm_runtime_disable(dev);
530 static struct platform_driver j721e_pcie_driver = {
531 .probe = j721e_pcie_probe,
532 .remove = j721e_pcie_remove,
534 .name = "j721e-pcie",
535 .of_match_table = of_j721e_pcie_match,
536 .suppress_bind_attrs = true,
539 builtin_platform_driver(j721e_pcie_driver);