1 #include <linux/delay.h>
3 #include <linux/module.h>
4 #include <linux/sched/signal.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
16 DEFINE_RAW_SPINLOCK(pci_lock);
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
28 #ifdef CONFIG_PCI_LOCKLESS_CONFIG
29 # define pci_lock_config(f) do { (void)(f); } while (0)
30 # define pci_unlock_config(f) do { (void)(f); } while (0)
32 # define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
33 # define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
36 #define PCI_OP_READ(size, type, len) \
37 int pci_bus_read_config_##size \
38 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
41 unsigned long flags; \
43 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
44 pci_lock_config(flags); \
45 res = bus->ops->read(bus, devfn, pos, len, &data); \
46 *value = (type)data; \
47 pci_unlock_config(flags); \
51 #define PCI_OP_WRITE(size, type, len) \
52 int pci_bus_write_config_##size \
53 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
56 unsigned long flags; \
57 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
58 pci_lock_config(flags); \
59 res = bus->ops->write(bus, devfn, pos, len, value); \
60 pci_unlock_config(flags); \
64 PCI_OP_READ(byte, u8, 1)
65 PCI_OP_READ(word, u16, 2)
66 PCI_OP_READ(dword, u32, 4)
67 PCI_OP_WRITE(byte, u8, 1)
68 PCI_OP_WRITE(word, u16, 2)
69 PCI_OP_WRITE(dword, u32, 4)
71 EXPORT_SYMBOL(pci_bus_read_config_byte);
72 EXPORT_SYMBOL(pci_bus_read_config_word);
73 EXPORT_SYMBOL(pci_bus_read_config_dword);
74 EXPORT_SYMBOL(pci_bus_write_config_byte);
75 EXPORT_SYMBOL(pci_bus_write_config_word);
76 EXPORT_SYMBOL(pci_bus_write_config_dword);
78 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 *val)
83 addr = bus->ops->map_bus(bus, devfn, where);
86 return PCIBIOS_DEVICE_NOT_FOUND;
96 return PCIBIOS_SUCCESSFUL;
98 EXPORT_SYMBOL_GPL(pci_generic_config_read);
100 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val)
105 addr = bus->ops->map_bus(bus, devfn, where);
107 return PCIBIOS_DEVICE_NOT_FOUND;
116 return PCIBIOS_SUCCESSFUL;
118 EXPORT_SYMBOL_GPL(pci_generic_config_write);
120 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
125 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
128 return PCIBIOS_DEVICE_NOT_FOUND;
134 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
136 return PCIBIOS_SUCCESSFUL;
138 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
140 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 val)
146 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
148 return PCIBIOS_DEVICE_NOT_FOUND;
152 return PCIBIOS_SUCCESSFUL;
156 * In general, hardware that supports only 32-bit writes on PCI is
157 * not spec-compliant. For example, software may perform a 16-bit
158 * write. If the hardware only supports 32-bit accesses, we must
159 * do a 32-bit read, merge in the 16 bits we intend to write,
160 * followed by a 32-bit write. If the 16 bits we *don't* intend to
161 * write happen to have any RW1C (write-one-to-clear) bits set, we
162 * just inadvertently cleared something we shouldn't have.
164 dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
165 size, pci_domain_nr(bus), bus->number,
166 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
168 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
169 tmp = readl(addr) & mask;
170 tmp |= val << ((where & 0x3) * 8);
173 return PCIBIOS_SUCCESSFUL;
175 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
178 * pci_bus_set_ops - Set raw operations of pci bus
179 * @bus: pci bus struct
180 * @ops: new raw operations
182 * Return previous raw operations
184 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
186 struct pci_ops *old_ops;
189 raw_spin_lock_irqsave(&pci_lock, flags);
192 raw_spin_unlock_irqrestore(&pci_lock, flags);
195 EXPORT_SYMBOL(pci_bus_set_ops);
198 * The following routines are to prevent the user from accessing PCI config
199 * space when it's unsafe to do so. Some devices require this during BIST and
200 * we're required to prevent it during D-state transitions.
202 * We have a bit per device to indicate it's blocked and a global wait queue
203 * for callers to sleep on until devices are unblocked.
205 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
207 static noinline void pci_wait_cfg(struct pci_dev *dev)
208 __must_hold(&pci_lock)
211 raw_spin_unlock_irq(&pci_lock);
212 wait_event(pci_cfg_wait, !dev->block_cfg_access);
213 raw_spin_lock_irq(&pci_lock);
214 } while (dev->block_cfg_access);
217 /* Returns 0 on success, negative values indicate error. */
218 #define PCI_USER_READ_CONFIG(size, type) \
219 int pci_user_read_config_##size \
220 (struct pci_dev *dev, int pos, type *val) \
222 int ret = PCIBIOS_SUCCESSFUL; \
224 if (PCI_##size##_BAD) \
226 raw_spin_lock_irq(&pci_lock); \
227 if (unlikely(dev->block_cfg_access)) \
229 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
230 pos, sizeof(type), &data); \
231 raw_spin_unlock_irq(&pci_lock); \
233 return pcibios_err_to_errno(ret); \
235 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
237 /* Returns 0 on success, negative values indicate error. */
238 #define PCI_USER_WRITE_CONFIG(size, type) \
239 int pci_user_write_config_##size \
240 (struct pci_dev *dev, int pos, type val) \
242 int ret = PCIBIOS_SUCCESSFUL; \
243 if (PCI_##size##_BAD) \
245 raw_spin_lock_irq(&pci_lock); \
246 if (unlikely(dev->block_cfg_access)) \
248 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
249 pos, sizeof(type), val); \
250 raw_spin_unlock_irq(&pci_lock); \
251 return pcibios_err_to_errno(ret); \
253 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
255 PCI_USER_READ_CONFIG(byte, u8)
256 PCI_USER_READ_CONFIG(word, u16)
257 PCI_USER_READ_CONFIG(dword, u32)
258 PCI_USER_WRITE_CONFIG(byte, u8)
259 PCI_USER_WRITE_CONFIG(word, u16)
260 PCI_USER_WRITE_CONFIG(dword, u32)
262 /* VPD access through PCI 2.2+ VPD capability */
265 * pci_read_vpd - Read one entry from Vital Product Data
266 * @dev: pci device struct
267 * @pos: offset in vpd space
268 * @count: number of bytes to read
269 * @buf: pointer to where to store result
271 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
273 if (!dev->vpd || !dev->vpd->ops)
275 return dev->vpd->ops->read(dev, pos, count, buf);
277 EXPORT_SYMBOL(pci_read_vpd);
280 * pci_write_vpd - Write entry to Vital Product Data
281 * @dev: pci device struct
282 * @pos: offset in vpd space
283 * @count: number of bytes to write
284 * @buf: buffer containing write data
286 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
288 if (!dev->vpd || !dev->vpd->ops)
290 return dev->vpd->ops->write(dev, pos, count, buf);
292 EXPORT_SYMBOL(pci_write_vpd);
295 * pci_set_vpd_size - Set size of Vital Product Data space
296 * @dev: pci device struct
297 * @len: size of vpd space
299 int pci_set_vpd_size(struct pci_dev *dev, size_t len)
301 if (!dev->vpd || !dev->vpd->ops)
303 return dev->vpd->ops->set_size(dev, len);
305 EXPORT_SYMBOL(pci_set_vpd_size);
307 #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
310 * pci_vpd_size - determine actual size of Vital Product Data
311 * @dev: pci device struct
312 * @old_size: current assumed size, also maximum allowed size
314 static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
317 unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
319 while (off < old_size &&
320 pci_read_vpd(dev, off, 1, header) == 1) {
323 if (header[0] & PCI_VPD_LRDT) {
324 /* Large Resource Data Type Tag */
325 tag = pci_vpd_lrdt_tag(header);
326 /* Only read length from known tag items */
327 if ((tag == PCI_VPD_LTIN_ID_STRING) ||
328 (tag == PCI_VPD_LTIN_RO_DATA) ||
329 (tag == PCI_VPD_LTIN_RW_DATA)) {
330 if (pci_read_vpd(dev, off+1, 2,
333 "invalid large VPD tag %02x size at offset %zu",
337 off += PCI_VPD_LRDT_TAG_SIZE +
338 pci_vpd_lrdt_size(header);
341 /* Short Resource Data Type Tag */
342 off += PCI_VPD_SRDT_TAG_SIZE +
343 pci_vpd_srdt_size(header);
344 tag = pci_vpd_srdt_tag(header);
347 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
350 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
351 (tag != PCI_VPD_LTIN_RO_DATA) &&
352 (tag != PCI_VPD_LTIN_RW_DATA)) {
354 "invalid %s VPD tag %02x at offset %zu",
355 (header[0] & PCI_VPD_LRDT) ? "large" : "short",
364 * Wait for last operation to complete.
365 * This code has to spin since there is no other notification from the PCI
366 * hardware. Since the VPD is often implemented by serial attachment to an
367 * EEPROM, it may take many milliseconds to complete.
369 * Returns 0 on success, negative values indicate error.
371 static int pci_vpd_wait(struct pci_dev *dev)
373 struct pci_vpd *vpd = dev->vpd;
374 unsigned long timeout = jiffies + msecs_to_jiffies(125);
375 unsigned long max_sleep = 16;
382 while (time_before(jiffies, timeout)) {
383 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
388 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
393 if (fatal_signal_pending(current))
396 usleep_range(10, max_sleep);
397 if (max_sleep < 1024)
401 dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
405 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
408 struct pci_vpd *vpd = dev->vpd;
410 loff_t end = pos + count;
418 vpd->len = pci_vpd_size(dev, vpd->len);
427 if (end > vpd->len) {
432 if (mutex_lock_killable(&vpd->lock))
435 ret = pci_vpd_wait(dev);
441 unsigned int i, skip;
443 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
448 vpd->flag = PCI_VPD_ADDR_F;
449 ret = pci_vpd_wait(dev);
453 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
458 for (i = 0; i < sizeof(u32); i++) {
468 mutex_unlock(&vpd->lock);
469 return ret ? ret : count;
472 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
475 struct pci_vpd *vpd = dev->vpd;
477 loff_t end = pos + count;
480 if (pos < 0 || (pos & 3) || (count & 3))
485 vpd->len = pci_vpd_size(dev, vpd->len);
494 if (mutex_lock_killable(&vpd->lock))
497 ret = pci_vpd_wait(dev);
509 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
512 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
513 pos | PCI_VPD_ADDR_F);
519 ret = pci_vpd_wait(dev);
526 mutex_unlock(&vpd->lock);
527 return ret ? ret : count;
530 static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
532 struct pci_vpd *vpd = dev->vpd;
534 if (len == 0 || len > PCI_VPD_MAX_SIZE)
543 static const struct pci_vpd_ops pci_vpd_ops = {
544 .read = pci_vpd_read,
545 .write = pci_vpd_write,
546 .set_size = pci_vpd_set_size,
549 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
552 struct pci_dev *tdev = pci_get_slot(dev->bus,
553 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
559 ret = pci_read_vpd(tdev, pos, count, arg);
564 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
567 struct pci_dev *tdev = pci_get_slot(dev->bus,
568 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
574 ret = pci_write_vpd(tdev, pos, count, arg);
579 static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
581 struct pci_dev *tdev = pci_get_slot(dev->bus,
582 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
588 ret = pci_set_vpd_size(tdev, len);
593 static const struct pci_vpd_ops pci_vpd_f0_ops = {
594 .read = pci_vpd_f0_read,
595 .write = pci_vpd_f0_write,
596 .set_size = pci_vpd_f0_set_size,
599 int pci_vpd_init(struct pci_dev *dev)
604 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
608 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
612 vpd->len = PCI_VPD_MAX_SIZE;
613 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
614 vpd->ops = &pci_vpd_f0_ops;
616 vpd->ops = &pci_vpd_ops;
617 mutex_init(&vpd->lock);
625 void pci_vpd_release(struct pci_dev *dev)
631 * pci_cfg_access_lock - Lock PCI config reads/writes
632 * @dev: pci device struct
634 * When access is locked, any userspace reads or writes to config
635 * space and concurrent lock requests will sleep until access is
636 * allowed via pci_cfg_access_unlock() again.
638 void pci_cfg_access_lock(struct pci_dev *dev)
642 raw_spin_lock_irq(&pci_lock);
643 if (dev->block_cfg_access)
645 dev->block_cfg_access = 1;
646 raw_spin_unlock_irq(&pci_lock);
648 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
651 * pci_cfg_access_trylock - try to lock PCI config reads/writes
652 * @dev: pci device struct
654 * Same as pci_cfg_access_lock, but will return 0 if access is
655 * already locked, 1 otherwise. This function can be used from
658 bool pci_cfg_access_trylock(struct pci_dev *dev)
663 raw_spin_lock_irqsave(&pci_lock, flags);
664 if (dev->block_cfg_access)
667 dev->block_cfg_access = 1;
668 raw_spin_unlock_irqrestore(&pci_lock, flags);
672 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
675 * pci_cfg_access_unlock - Unlock PCI config reads/writes
676 * @dev: pci device struct
678 * This function allows PCI config accesses to resume.
680 void pci_cfg_access_unlock(struct pci_dev *dev)
684 raw_spin_lock_irqsave(&pci_lock, flags);
686 /* This indicates a problem in the caller, but we don't need
687 * to kill them, unlike a double-block above. */
688 WARN_ON(!dev->block_cfg_access);
690 dev->block_cfg_access = 0;
691 raw_spin_unlock_irqrestore(&pci_lock, flags);
693 wake_up_all(&pci_cfg_wait);
695 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
697 static inline int pcie_cap_version(const struct pci_dev *dev)
699 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
702 static bool pcie_downstream_port(const struct pci_dev *dev)
704 int type = pci_pcie_type(dev);
706 return type == PCI_EXP_TYPE_ROOT_PORT ||
707 type == PCI_EXP_TYPE_DOWNSTREAM ||
708 type == PCI_EXP_TYPE_PCIE_BRIDGE;
711 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
713 int type = pci_pcie_type(dev);
715 return type == PCI_EXP_TYPE_ENDPOINT ||
716 type == PCI_EXP_TYPE_LEG_END ||
717 type == PCI_EXP_TYPE_ROOT_PORT ||
718 type == PCI_EXP_TYPE_UPSTREAM ||
719 type == PCI_EXP_TYPE_DOWNSTREAM ||
720 type == PCI_EXP_TYPE_PCI_BRIDGE ||
721 type == PCI_EXP_TYPE_PCIE_BRIDGE;
724 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
726 return pcie_downstream_port(dev) &&
727 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
730 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
732 int type = pci_pcie_type(dev);
734 return type == PCI_EXP_TYPE_ROOT_PORT ||
735 type == PCI_EXP_TYPE_RC_EC;
738 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
740 if (!pci_is_pcie(dev))
753 return pcie_cap_has_lnkctl(dev);
757 return pcie_cap_has_sltctl(dev);
761 return pcie_cap_has_rtctl(dev);
762 case PCI_EXP_DEVCAP2:
763 case PCI_EXP_DEVCTL2:
764 case PCI_EXP_LNKCAP2:
765 case PCI_EXP_LNKCTL2:
766 case PCI_EXP_LNKSTA2:
767 return pcie_cap_version(dev) > 1;
774 * Note that these accessor functions are only for the "PCI Express
775 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
776 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
778 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
786 if (pcie_capability_reg_implemented(dev, pos)) {
787 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
789 * Reset *val to 0 if pci_read_config_word() fails, it may
790 * have been written as 0xFFFF if hardware error happens
791 * during pci_read_config_word().
799 * For Functions that do not implement the Slot Capabilities,
800 * Slot Status, and Slot Control registers, these spaces must
801 * be hardwired to 0b, with the exception of the Presence Detect
802 * State bit in the Slot Status register of Downstream Ports,
803 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
805 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
806 pos == PCI_EXP_SLTSTA)
807 *val = PCI_EXP_SLTSTA_PDS;
811 EXPORT_SYMBOL(pcie_capability_read_word);
813 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
821 if (pcie_capability_reg_implemented(dev, pos)) {
822 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
824 * Reset *val to 0 if pci_read_config_dword() fails, it may
825 * have been written as 0xFFFFFFFF if hardware error happens
826 * during pci_read_config_dword().
833 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
834 pos == PCI_EXP_SLTSTA)
835 *val = PCI_EXP_SLTSTA_PDS;
839 EXPORT_SYMBOL(pcie_capability_read_dword);
841 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
846 if (!pcie_capability_reg_implemented(dev, pos))
849 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
851 EXPORT_SYMBOL(pcie_capability_write_word);
853 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
858 if (!pcie_capability_reg_implemented(dev, pos))
861 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
863 EXPORT_SYMBOL(pcie_capability_write_dword);
865 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
871 ret = pcie_capability_read_word(dev, pos, &val);
875 ret = pcie_capability_write_word(dev, pos, val);
880 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
882 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
888 ret = pcie_capability_read_dword(dev, pos, &val);
892 ret = pcie_capability_write_dword(dev, pos, val);
897 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
899 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
901 if (pci_dev_is_disconnected(dev)) {
903 return PCIBIOS_DEVICE_NOT_FOUND;
905 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
907 EXPORT_SYMBOL(pci_read_config_byte);
909 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
911 if (pci_dev_is_disconnected(dev)) {
913 return PCIBIOS_DEVICE_NOT_FOUND;
915 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
917 EXPORT_SYMBOL(pci_read_config_word);
919 int pci_read_config_dword(const struct pci_dev *dev, int where,
922 if (pci_dev_is_disconnected(dev)) {
924 return PCIBIOS_DEVICE_NOT_FOUND;
926 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
928 EXPORT_SYMBOL(pci_read_config_dword);
930 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
932 if (pci_dev_is_disconnected(dev))
933 return PCIBIOS_DEVICE_NOT_FOUND;
934 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
936 EXPORT_SYMBOL(pci_write_config_byte);
938 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
940 if (pci_dev_is_disconnected(dev))
941 return PCIBIOS_DEVICE_NOT_FOUND;
942 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
944 EXPORT_SYMBOL(pci_write_config_word);
946 int pci_write_config_dword(const struct pci_dev *dev, int where,
949 if (pci_dev_is_disconnected(dev))
950 return PCIBIOS_DEVICE_NOT_FOUND;
951 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
953 EXPORT_SYMBOL(pci_write_config_dword);