1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/module.h>
4 #include <linux/slab.h>
5 #include <linux/ioport.h>
6 #include <linux/wait.h>
11 * This interrupt-safe spinlock protects all accesses to PCI
12 * configuration space.
15 DEFINE_RAW_SPINLOCK(pci_lock);
18 * Wrappers for all PCI configuration access functions. They just check
19 * alignment, do locking and call the low-level functions pointed to
23 #define PCI_byte_BAD 0
24 #define PCI_word_BAD (pos & 1)
25 #define PCI_dword_BAD (pos & 3)
27 #ifdef CONFIG_PCI_LOCKLESS_CONFIG
28 # define pci_lock_config(f) do { (void)(f); } while (0)
29 # define pci_unlock_config(f) do { (void)(f); } while (0)
31 # define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
32 # define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
35 #define PCI_OP_READ(size, type, len) \
36 int noinline pci_bus_read_config_##size \
37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
40 unsigned long flags; \
42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
43 pci_lock_config(flags); \
44 res = bus->ops->read(bus, devfn, pos, len, &data); \
45 *value = (type)data; \
46 pci_unlock_config(flags); \
50 #define PCI_OP_WRITE(size, type, len) \
51 int noinline pci_bus_write_config_##size \
52 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
55 unsigned long flags; \
56 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
57 pci_lock_config(flags); \
58 res = bus->ops->write(bus, devfn, pos, len, value); \
59 pci_unlock_config(flags); \
63 PCI_OP_READ(byte, u8, 1)
64 PCI_OP_READ(word, u16, 2)
65 PCI_OP_READ(dword, u32, 4)
66 PCI_OP_WRITE(byte, u8, 1)
67 PCI_OP_WRITE(word, u16, 2)
68 PCI_OP_WRITE(dword, u32, 4)
70 EXPORT_SYMBOL(pci_bus_read_config_byte);
71 EXPORT_SYMBOL(pci_bus_read_config_word);
72 EXPORT_SYMBOL(pci_bus_read_config_dword);
73 EXPORT_SYMBOL(pci_bus_write_config_byte);
74 EXPORT_SYMBOL(pci_bus_write_config_word);
75 EXPORT_SYMBOL(pci_bus_write_config_dword);
77 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
78 int where, int size, u32 *val)
82 addr = bus->ops->map_bus(bus, devfn, where);
85 return PCIBIOS_DEVICE_NOT_FOUND;
95 return PCIBIOS_SUCCESSFUL;
97 EXPORT_SYMBOL_GPL(pci_generic_config_read);
99 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
100 int where, int size, u32 val)
104 addr = bus->ops->map_bus(bus, devfn, where);
106 return PCIBIOS_DEVICE_NOT_FOUND;
115 return PCIBIOS_SUCCESSFUL;
117 EXPORT_SYMBOL_GPL(pci_generic_config_write);
119 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
120 int where, int size, u32 *val)
124 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
127 return PCIBIOS_DEVICE_NOT_FOUND;
133 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
135 return PCIBIOS_SUCCESSFUL;
137 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
139 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
140 int where, int size, u32 val)
145 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
147 return PCIBIOS_DEVICE_NOT_FOUND;
151 return PCIBIOS_SUCCESSFUL;
155 * In general, hardware that supports only 32-bit writes on PCI is
156 * not spec-compliant. For example, software may perform a 16-bit
157 * write. If the hardware only supports 32-bit accesses, we must
158 * do a 32-bit read, merge in the 16 bits we intend to write,
159 * followed by a 32-bit write. If the 16 bits we *don't* intend to
160 * write happen to have any RW1C (write-one-to-clear) bits set, we
161 * just inadvertently cleared something we shouldn't have.
163 if (!bus->unsafe_warn) {
164 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
165 size, pci_domain_nr(bus), bus->number,
166 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
167 bus->unsafe_warn = 1;
170 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
171 tmp = readl(addr) & mask;
172 tmp |= val << ((where & 0x3) * 8);
175 return PCIBIOS_SUCCESSFUL;
177 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
180 * pci_bus_set_ops - Set raw operations of pci bus
181 * @bus: pci bus struct
182 * @ops: new raw operations
184 * Return previous raw operations
186 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
188 struct pci_ops *old_ops;
191 raw_spin_lock_irqsave(&pci_lock, flags);
194 raw_spin_unlock_irqrestore(&pci_lock, flags);
197 EXPORT_SYMBOL(pci_bus_set_ops);
200 * The following routines are to prevent the user from accessing PCI config
201 * space when it's unsafe to do so. Some devices require this during BIST and
202 * we're required to prevent it during D-state transitions.
204 * We have a bit per device to indicate it's blocked and a global wait queue
205 * for callers to sleep on until devices are unblocked.
207 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
209 static noinline void pci_wait_cfg(struct pci_dev *dev)
210 __must_hold(&pci_lock)
213 raw_spin_unlock_irq(&pci_lock);
214 wait_event(pci_cfg_wait, !dev->block_cfg_access);
215 raw_spin_lock_irq(&pci_lock);
216 } while (dev->block_cfg_access);
219 /* Returns 0 on success, negative values indicate error. */
220 #define PCI_USER_READ_CONFIG(size, type) \
221 int pci_user_read_config_##size \
222 (struct pci_dev *dev, int pos, type *val) \
224 int ret = PCIBIOS_SUCCESSFUL; \
226 if (PCI_##size##_BAD) \
228 raw_spin_lock_irq(&pci_lock); \
229 if (unlikely(dev->block_cfg_access)) \
231 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
232 pos, sizeof(type), &data); \
233 raw_spin_unlock_irq(&pci_lock); \
235 return pcibios_err_to_errno(ret); \
237 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
239 /* Returns 0 on success, negative values indicate error. */
240 #define PCI_USER_WRITE_CONFIG(size, type) \
241 int pci_user_write_config_##size \
242 (struct pci_dev *dev, int pos, type val) \
244 int ret = PCIBIOS_SUCCESSFUL; \
245 if (PCI_##size##_BAD) \
247 raw_spin_lock_irq(&pci_lock); \
248 if (unlikely(dev->block_cfg_access)) \
250 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
251 pos, sizeof(type), val); \
252 raw_spin_unlock_irq(&pci_lock); \
253 return pcibios_err_to_errno(ret); \
255 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
257 PCI_USER_READ_CONFIG(byte, u8)
258 PCI_USER_READ_CONFIG(word, u16)
259 PCI_USER_READ_CONFIG(dword, u32)
260 PCI_USER_WRITE_CONFIG(byte, u8)
261 PCI_USER_WRITE_CONFIG(word, u16)
262 PCI_USER_WRITE_CONFIG(dword, u32)
265 * pci_cfg_access_lock - Lock PCI config reads/writes
266 * @dev: pci device struct
268 * When access is locked, any userspace reads or writes to config
269 * space and concurrent lock requests will sleep until access is
270 * allowed via pci_cfg_access_unlock() again.
272 void pci_cfg_access_lock(struct pci_dev *dev)
276 raw_spin_lock_irq(&pci_lock);
277 if (dev->block_cfg_access)
279 dev->block_cfg_access = 1;
280 raw_spin_unlock_irq(&pci_lock);
282 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
285 * pci_cfg_access_trylock - try to lock PCI config reads/writes
286 * @dev: pci device struct
288 * Same as pci_cfg_access_lock, but will return 0 if access is
289 * already locked, 1 otherwise. This function can be used from
292 bool pci_cfg_access_trylock(struct pci_dev *dev)
297 raw_spin_lock_irqsave(&pci_lock, flags);
298 if (dev->block_cfg_access)
301 dev->block_cfg_access = 1;
302 raw_spin_unlock_irqrestore(&pci_lock, flags);
306 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
309 * pci_cfg_access_unlock - Unlock PCI config reads/writes
310 * @dev: pci device struct
312 * This function allows PCI config accesses to resume.
314 void pci_cfg_access_unlock(struct pci_dev *dev)
318 raw_spin_lock_irqsave(&pci_lock, flags);
321 * This indicates a problem in the caller, but we don't need
322 * to kill them, unlike a double-block above.
324 WARN_ON(!dev->block_cfg_access);
326 dev->block_cfg_access = 0;
327 raw_spin_unlock_irqrestore(&pci_lock, flags);
329 wake_up_all(&pci_cfg_wait);
331 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
333 static inline int pcie_cap_version(const struct pci_dev *dev)
335 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
338 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
340 int type = pci_pcie_type(dev);
342 return type == PCI_EXP_TYPE_ENDPOINT ||
343 type == PCI_EXP_TYPE_LEG_END ||
344 type == PCI_EXP_TYPE_ROOT_PORT ||
345 type == PCI_EXP_TYPE_UPSTREAM ||
346 type == PCI_EXP_TYPE_DOWNSTREAM ||
347 type == PCI_EXP_TYPE_PCI_BRIDGE ||
348 type == PCI_EXP_TYPE_PCIE_BRIDGE;
351 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
353 return pcie_downstream_port(dev) &&
354 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
357 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
359 int type = pci_pcie_type(dev);
361 return type == PCI_EXP_TYPE_ROOT_PORT ||
362 type == PCI_EXP_TYPE_RC_EC;
365 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
367 if (!pci_is_pcie(dev))
380 return pcie_cap_has_lnkctl(dev);
384 return pcie_cap_has_sltctl(dev);
388 return pcie_cap_has_rtctl(dev);
389 case PCI_EXP_DEVCAP2:
390 case PCI_EXP_DEVCTL2:
391 case PCI_EXP_LNKCAP2:
392 case PCI_EXP_LNKCTL2:
393 case PCI_EXP_LNKSTA2:
394 return pcie_cap_version(dev) > 1;
401 * Note that these accessor functions are only for the "PCI Express
402 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
403 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
405 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
413 if (pcie_capability_reg_implemented(dev, pos)) {
414 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
416 * Reset *val to 0 if pci_read_config_word() fails, it may
417 * have been written as 0xFFFF if hardware error happens
418 * during pci_read_config_word().
426 * For Functions that do not implement the Slot Capabilities,
427 * Slot Status, and Slot Control registers, these spaces must
428 * be hardwired to 0b, with the exception of the Presence Detect
429 * State bit in the Slot Status register of Downstream Ports,
430 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
432 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
433 pos == PCI_EXP_SLTSTA)
434 *val = PCI_EXP_SLTSTA_PDS;
438 EXPORT_SYMBOL(pcie_capability_read_word);
440 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
448 if (pcie_capability_reg_implemented(dev, pos)) {
449 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
451 * Reset *val to 0 if pci_read_config_dword() fails, it may
452 * have been written as 0xFFFFFFFF if hardware error happens
453 * during pci_read_config_dword().
460 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
461 pos == PCI_EXP_SLTSTA)
462 *val = PCI_EXP_SLTSTA_PDS;
466 EXPORT_SYMBOL(pcie_capability_read_dword);
468 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
473 if (!pcie_capability_reg_implemented(dev, pos))
476 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
478 EXPORT_SYMBOL(pcie_capability_write_word);
480 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
485 if (!pcie_capability_reg_implemented(dev, pos))
488 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
490 EXPORT_SYMBOL(pcie_capability_write_dword);
492 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
498 ret = pcie_capability_read_word(dev, pos, &val);
502 ret = pcie_capability_write_word(dev, pos, val);
507 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
509 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
515 ret = pcie_capability_read_dword(dev, pos, &val);
519 ret = pcie_capability_write_dword(dev, pos, val);
524 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
526 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
528 if (pci_dev_is_disconnected(dev)) {
530 return PCIBIOS_DEVICE_NOT_FOUND;
532 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
534 EXPORT_SYMBOL(pci_read_config_byte);
536 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
538 if (pci_dev_is_disconnected(dev)) {
540 return PCIBIOS_DEVICE_NOT_FOUND;
542 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
544 EXPORT_SYMBOL(pci_read_config_word);
546 int pci_read_config_dword(const struct pci_dev *dev, int where,
549 if (pci_dev_is_disconnected(dev)) {
551 return PCIBIOS_DEVICE_NOT_FOUND;
553 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
555 EXPORT_SYMBOL(pci_read_config_dword);
557 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
559 if (pci_dev_is_disconnected(dev))
560 return PCIBIOS_DEVICE_NOT_FOUND;
561 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
563 EXPORT_SYMBOL(pci_write_config_byte);
565 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
567 if (pci_dev_is_disconnected(dev))
568 return PCIBIOS_DEVICE_NOT_FOUND;
569 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
571 EXPORT_SYMBOL(pci_write_config_word);
573 int pci_write_config_dword(const struct pci_dev *dev, int where,
576 if (pci_dev_is_disconnected(dev))
577 return PCIBIOS_DEVICE_NOT_FOUND;
578 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
580 EXPORT_SYMBOL(pci_write_config_dword);