2 ** System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6 ** (c) Copyright 2000-2004 Hewlett-Packard Company
8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17 ** J5000/J7000/N-class/L-class machines and their successors.
19 ** FIXME: add DMA hint support programming in both sba and lba modules.
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
29 #include <linux/string.h>
30 #include <linux/pci.h>
31 #include <linux/scatterlist.h>
32 #include <linux/iommu-helper.h>
34 #include <asm/byteorder.h>
36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
40 #include <linux/proc_fs.h>
41 #include <linux/seq_file.h>
42 #include <linux/module.h>
44 #include <asm/ropes.h>
45 #include <asm/mckinley.h> /* for proc_mckinley_root */
46 #include <asm/runway.h> /* for proc_runway_root */
47 #include <asm/page.h> /* for PAGE0 */
48 #include <asm/pdc.h> /* for PDC_MODEL_* */
49 #include <asm/pdcpat.h> /* for is_pdc_pat() */
50 #include <asm/parisc-device.h>
52 #define MODULE_NAME "SBA"
55 ** The number of debug flags is a clue - this code is fragile.
56 ** Don't even think about messing with it unless you have
57 ** plenty of 710's to sacrifice to the computer gods. :^)
61 #undef DEBUG_SBA_RUN_SG
62 #undef DEBUG_SBA_RESOURCE
63 #undef ASSERT_PDIR_SANITY
64 #undef DEBUG_LARGE_SG_ENTRIES
68 #define DBG_INIT(x...) printk(x)
70 #define DBG_INIT(x...)
74 #define DBG_RUN(x...) printk(x)
79 #ifdef DEBUG_SBA_RUN_SG
80 #define DBG_RUN_SG(x...) printk(x)
82 #define DBG_RUN_SG(x...)
86 #ifdef DEBUG_SBA_RESOURCE
87 #define DBG_RES(x...) printk(x)
92 #define SBA_INLINE __inline__
94 #define DEFAULT_DMA_HINT_REG 0
96 struct sba_device *sba_list;
97 EXPORT_SYMBOL_GPL(sba_list);
99 static unsigned long ioc_needs_fdc = 0;
101 /* global count of IOMMUs in the system */
102 static unsigned int global_ioc_cnt = 0;
104 /* PA8700 (Piranha 2.2) bug workaround */
105 static unsigned long piranha_bad_128k = 0;
107 /* Looks nice and keeps the compiler happy */
108 #define SBA_DEV(d) ((struct sba_device *) (d))
110 #ifdef CONFIG_AGP_PARISC
111 #define SBA_AGP_SUPPORT
112 #endif /*CONFIG_AGP_PARISC*/
114 #ifdef SBA_AGP_SUPPORT
115 static int sba_reserve_agpgart = 1;
116 module_param(sba_reserve_agpgart, int, 0444);
117 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
121 /************************************
122 ** SBA register read and write support
124 ** BE WARNED: register writes are posted.
125 ** (ie follow writes which must reach HW with a read)
127 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
129 #define READ_REG32(addr) readl(addr)
130 #define READ_REG64(addr) readq(addr)
131 #define WRITE_REG32(val, addr) writel((val), (addr))
132 #define WRITE_REG64(val, addr) writeq((val), (addr))
135 #define READ_REG(addr) READ_REG64(addr)
136 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
138 #define READ_REG(addr) READ_REG32(addr)
139 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
142 #ifdef DEBUG_SBA_INIT
144 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
147 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
148 * @hpa: base address of the sba
150 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
151 * IO Adapter (aka Bus Converter).
154 sba_dump_ranges(void __iomem *hpa)
156 DBG_INIT("SBA at 0x%p\n", hpa);
157 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
158 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
159 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
161 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
162 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
163 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
167 * sba_dump_tlb - debugging only - print IOMMU operating parameters
168 * @hpa: base address of the IOMMU
170 * Print the size/location of the IO MMU PDIR.
172 static void sba_dump_tlb(void __iomem *hpa)
174 DBG_INIT("IO TLB at 0x%p\n", hpa);
175 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
176 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
177 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
178 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
182 #define sba_dump_ranges(x)
183 #define sba_dump_tlb(x)
184 #endif /* DEBUG_SBA_INIT */
187 #ifdef ASSERT_PDIR_SANITY
190 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
191 * @ioc: IO MMU structure which owns the pdir we are interested in.
192 * @msg: text to print ont the output line.
195 * Print one entry of the IO MMU PDIR in human readable form.
198 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
200 /* start printing from lowest pde in rval */
201 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
202 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
205 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
207 rptr, pide & (BITS_PER_LONG - 1), *rptr);
210 while (rcnt < BITS_PER_LONG) {
211 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
212 (rcnt == (pide & (BITS_PER_LONG - 1)))
218 printk(KERN_DEBUG "%s", msg);
223 * sba_check_pdir - debugging only - consistency checker
224 * @ioc: IO MMU structure which owns the pdir we are interested in.
225 * @msg: text to print ont the output line.
227 * Verify the resource map and pdir state is consistent
230 sba_check_pdir(struct ioc *ioc, char *msg)
232 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
233 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
234 u64 *pptr = ioc->pdir_base; /* pdir ptr */
237 while (rptr < rptr_end) {
239 int rcnt = 32; /* number of bits we might check */
242 /* Get last byte and highest bit from that */
243 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
244 if ((rval ^ pde) & 0x80000000)
247 ** BUMMER! -- res_map != pdir --
248 ** Dump rval and matching pdir entries
250 sba_dump_pdir_entry(ioc, msg, pide);
254 rval <<= 1; /* try the next bit */
258 rptr++; /* look at next word of res_map */
260 /* It'd be nice if we always got here :^) */
266 * sba_dump_sg - debugging only - print Scatter-Gather list
267 * @ioc: IO MMU structure which owns the pdir we are interested in.
268 * @startsg: head of the SG list
269 * @nents: number of entries in SG list
271 * print the SG list so we can verify it's correct by hand.
274 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
276 while (nents-- > 0) {
277 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
279 (unsigned long) sg_dma_address(startsg),
281 sg_virt(startsg), startsg->length);
286 #endif /* ASSERT_PDIR_SANITY */
291 /**************************************************************
293 * I/O Pdir Resource Management
295 * Bits set in the resource map are in use.
296 * Each bit can represent a number of pages.
297 * LSbs represent lower addresses (IOVA's).
299 ***************************************************************/
300 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
302 /* Convert from IOVP to IOVA and vice versa. */
305 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
306 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
307 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
309 /* only support Astro and ancestors. Saves a few cycles in key places */
310 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
311 #define SBA_IOVP(ioc,iova) (iova)
314 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
316 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
317 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
319 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
320 unsigned int bitshiftcnt)
322 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
327 * sba_search_bitmap - find free space in IO PDIR resource bitmap
328 * @ioc: IO MMU structure which owns the pdir we are interested in.
329 * @bits_wanted: number of entries we need.
331 * Find consecutive free bits in resource bitmap.
332 * Each bit represents one entry in the IO Pdir.
333 * Cool perf optimization: search for log2(size) bits at a time.
335 static SBA_INLINE unsigned long
336 sba_search_bitmap(struct ioc *ioc, struct device *dev,
337 unsigned long bits_wanted)
339 unsigned long *res_ptr = ioc->res_hint;
340 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
341 unsigned long pide = ~0UL, tpide;
342 unsigned long boundary_size;
346 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
347 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
349 #if defined(ZX1_SUPPORT)
350 BUG_ON(ioc->ibase & ~IOVP_MASK);
351 shift = ioc->ibase >> IOVP_SHIFT;
356 if (bits_wanted > (BITS_PER_LONG/2)) {
357 /* Search word at a time - no mask needed */
358 for(; res_ptr < res_end; ++res_ptr) {
359 tpide = ptr_to_pide(ioc, res_ptr, 0);
360 ret = iommu_is_span_boundary(tpide, bits_wanted,
363 if ((*res_ptr == 0) && !ret) {
364 *res_ptr = RESMAP_MASK(bits_wanted);
369 /* point to the next word on next pass */
371 ioc->res_bitshift = 0;
374 ** Search the resource bit map on well-aligned values.
375 ** "o" is the alignment.
376 ** We need the alignment to invalidate I/O TLB using
377 ** SBA HW features in the unmap path.
379 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
380 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
383 if (bitshiftcnt >= BITS_PER_LONG) {
387 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
389 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
390 while(res_ptr < res_end)
392 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
394 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
395 ret = iommu_is_span_boundary(tpide, bits_wanted,
398 if ((((*res_ptr) & mask) == 0) && !ret) {
399 *res_ptr |= mask; /* mark resources busy! */
406 mask = RESMAP_MASK(bits_wanted);
411 /* look in the same word on the next pass */
412 ioc->res_bitshift = bitshiftcnt + bits_wanted;
416 if (res_end <= res_ptr) {
417 ioc->res_hint = (unsigned long *) ioc->res_map;
418 ioc->res_bitshift = 0;
420 ioc->res_hint = res_ptr;
427 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
428 * @ioc: IO MMU structure which owns the pdir we are interested in.
429 * @size: number of bytes to create a mapping for
431 * Given a size, find consecutive unmarked and then mark those bits in the
435 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
437 unsigned int pages_needed = size >> IOVP_SHIFT;
438 #ifdef SBA_COLLECT_STATS
439 unsigned long cr_start = mfctl(16);
443 pide = sba_search_bitmap(ioc, dev, pages_needed);
444 if (pide >= (ioc->res_size << 3)) {
445 pide = sba_search_bitmap(ioc, dev, pages_needed);
446 if (pide >= (ioc->res_size << 3))
447 panic("%s: I/O MMU @ %p is out of mapping resources\n",
448 __FILE__, ioc->ioc_hpa);
451 #ifdef ASSERT_PDIR_SANITY
452 /* verify the first enable bit is clear */
453 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
454 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
458 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
459 __func__, size, pages_needed, pide,
460 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
463 #ifdef SBA_COLLECT_STATS
465 unsigned long cr_end = mfctl(16);
466 unsigned long tmp = cr_end - cr_start;
467 /* check for roll over */
468 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
470 ioc->avg_search[ioc->avg_idx++] = cr_start;
471 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
473 ioc->used_pages += pages_needed;
481 * sba_free_range - unmark bits in IO PDIR resource bitmap
482 * @ioc: IO MMU structure which owns the pdir we are interested in.
483 * @iova: IO virtual address which was previously allocated.
484 * @size: number of bytes to create a mapping for
486 * clear bits in the ioc's resource map
488 static SBA_INLINE void
489 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
491 unsigned long iovp = SBA_IOVP(ioc, iova);
492 unsigned int pide = PDIR_INDEX(iovp);
493 unsigned int ridx = pide >> 3; /* convert bit to byte address */
494 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
496 int bits_not_wanted = size >> IOVP_SHIFT;
498 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
499 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
501 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
502 __func__, (uint) iova, size,
503 bits_not_wanted, m, pide, res_ptr, *res_ptr);
505 #ifdef SBA_COLLECT_STATS
506 ioc->used_pages -= bits_not_wanted;
513 /**************************************************************
515 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
517 ***************************************************************/
519 #ifdef SBA_HINT_SUPPORT
520 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
523 typedef unsigned long space_t;
524 #define KERNEL_SPACE 0
527 * sba_io_pdir_entry - fill in one IO PDIR entry
528 * @pdir_ptr: pointer to IO PDIR entry
529 * @sid: process Space ID - currently only support KERNEL_SPACE
530 * @vba: Virtual CPU address of buffer to map
531 * @hint: DMA hint set to use for this mapping
533 * SBA Mapping Routine
535 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
536 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
538 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
539 * for Astro/Ike looks like:
543 * +-+---------------------+----------------------------------+----+--------+
544 * |V| U | PPN[43:12] | U | VI |
545 * +-+---------------------+----------------------------------+----+--------+
547 * Pluto is basically identical, supports fewer physical address bits:
550 * +-+------------------------+-------------------------------+----+--------+
551 * |V| U | PPN[39:12] | U | VI |
552 * +-+------------------------+-------------------------------+----+--------+
554 * V == Valid Bit (Most Significant Bit is bit 0)
556 * PPN == Physical Page Number
557 * VI == Virtual Index (aka Coherent Index)
559 * LPA instruction output is put into PPN field.
560 * LCI (Load Coherence Index) instruction provides the "VI" bits.
562 * We pre-swap the bytes since PCX-W is Big Endian and the
563 * IOMMU uses little endian for the pdir.
566 static void SBA_INLINE
567 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
570 u64 pa; /* physical address */
571 register unsigned ci; /* coherent index */
573 pa = virt_to_phys(vba);
576 asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba));
577 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
579 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
580 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
583 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
584 * (bit #61, big endian), we have to flush and sync every time
585 * IO-PDIR is changed in Ike/Astro.
588 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
593 * sba_mark_invalid - invalidate one or more IO PDIR entries
594 * @ioc: IO MMU structure which owns the pdir we are interested in.
595 * @iova: IO Virtual Address mapped earlier
596 * @byte_cnt: number of bytes this mapping covers.
598 * Marking the IO PDIR entry(ies) as Invalid and invalidate
599 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
600 * is to purge stale entries in the IO TLB when unmapping entries.
602 * The PCOM register supports purging of multiple pages, with a minium
603 * of 1 page and a maximum of 2GB. Hardware requires the address be
604 * aligned to the size of the range being purged. The size of the range
605 * must be a power of 2. The "Cool perf optimization" in the
606 * allocation routine helps keep that true.
608 static SBA_INLINE void
609 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
611 u32 iovp = (u32) SBA_IOVP(ioc,iova);
612 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
614 #ifdef ASSERT_PDIR_SANITY
615 /* Assert first pdir entry is set.
617 ** Even though this is a big-endian machine, the entries
618 ** in the iopdir are little endian. That's why we look at
619 ** the byte at +7 instead of at +0.
621 if (0x80 != (((u8 *) pdir_ptr)[7])) {
622 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
626 if (byte_cnt > IOVP_SIZE)
629 unsigned long entries_per_cacheline = ioc_needs_fdc ?
630 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
631 - (unsigned long) pdir_ptr;
635 /* set "size" field for PCOM */
636 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
639 /* clear I/O Pdir entry "valid" bit first */
640 ((u8 *) pdir_ptr)[7] = 0;
642 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
644 entries_per_cacheline = L1_CACHE_SHIFT - 3;
648 byte_cnt -= IOVP_SIZE;
649 } while (byte_cnt > IOVP_SIZE);
651 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
654 ** clear I/O PDIR entry "valid" bit.
655 ** We have to R/M/W the cacheline regardless how much of the
656 ** pdir entry that we clobber.
657 ** The rest of the entry would be useful for debugging if we
658 ** could dump core on HPMC.
660 ((u8 *) pdir_ptr)[7] = 0;
662 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
664 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
668 * sba_dma_supported - PCI driver can query DMA support
669 * @dev: instance of PCI owned by the driver that's asking
670 * @mask: number of address bits this PCI device can handle
672 * See Documentation/DMA-API-HOWTO.txt
674 static int sba_dma_supported( struct device *dev, u64 mask)
679 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
684 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit
685 * first, then fall back to 32-bit if that fails.
686 * We are just "encouraging" 32-bit DMA masks here since we can
687 * never allow IOMMU bypass unless we add special support for ZX1.
697 * check if mask is >= than the current max IO Virt Address
698 * The max IO Virt address will *always* < 30 bits.
700 return((int)(mask >= (ioc->ibase - 1 +
701 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
706 * sba_map_single - map one buffer and return IOVA for DMA
707 * @dev: instance of PCI owned by the driver that's asking.
708 * @addr: driver buffer to map.
709 * @size: number of bytes to map in driver buffer.
710 * @direction: R/W or both.
712 * See Documentation/DMA-API-HOWTO.txt
715 sba_map_single(struct device *dev, void *addr, size_t size,
716 enum dma_data_direction direction)
727 return DMA_ERROR_CODE;
729 /* save offset bits */
730 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
732 /* round up to nearest IOVP_SIZE */
733 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
735 spin_lock_irqsave(&ioc->res_lock, flags);
736 #ifdef ASSERT_PDIR_SANITY
737 sba_check_pdir(ioc,"Check before sba_map_single()");
740 #ifdef SBA_COLLECT_STATS
741 ioc->msingle_calls++;
742 ioc->msingle_pages += size >> IOVP_SHIFT;
744 pide = sba_alloc_range(ioc, dev, size);
745 iovp = (dma_addr_t) pide << IOVP_SHIFT;
747 DBG_RUN("%s() 0x%p -> 0x%lx\n",
748 __func__, addr, (long) iovp | offset);
750 pdir_start = &(ioc->pdir_base[pide]);
753 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
755 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
757 (u8) (((u8 *) pdir_start)[7]),
758 (u8) (((u8 *) pdir_start)[6]),
759 (u8) (((u8 *) pdir_start)[5]),
760 (u8) (((u8 *) pdir_start)[4]),
761 (u8) (((u8 *) pdir_start)[3]),
762 (u8) (((u8 *) pdir_start)[2]),
763 (u8) (((u8 *) pdir_start)[1]),
764 (u8) (((u8 *) pdir_start)[0])
772 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
774 asm volatile("sync" : : );
776 #ifdef ASSERT_PDIR_SANITY
777 sba_check_pdir(ioc,"Check after sba_map_single()");
779 spin_unlock_irqrestore(&ioc->res_lock, flags);
781 /* form complete address */
782 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
787 sba_map_page(struct device *dev, struct page *page, unsigned long offset,
788 size_t size, enum dma_data_direction direction,
791 return sba_map_single(dev, page_address(page) + offset, size,
797 * sba_unmap_page - unmap one IOVA and free resources
798 * @dev: instance of PCI owned by the driver that's asking.
799 * @iova: IOVA of driver buffer previously mapped.
800 * @size: number of bytes mapped in driver buffer.
801 * @direction: R/W or both.
803 * See Documentation/DMA-API-HOWTO.txt
806 sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
807 enum dma_data_direction direction, unsigned long attrs)
810 #if DELAYED_RESOURCE_CNT > 0
811 struct sba_dma_pair *d;
816 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
823 offset = iova & ~IOVP_MASK;
824 iova ^= offset; /* clear offset bits */
826 size = ALIGN(size, IOVP_SIZE);
828 spin_lock_irqsave(&ioc->res_lock, flags);
830 #ifdef SBA_COLLECT_STATS
831 ioc->usingle_calls++;
832 ioc->usingle_pages += size >> IOVP_SHIFT;
835 sba_mark_invalid(ioc, iova, size);
837 #if DELAYED_RESOURCE_CNT > 0
838 /* Delaying when we re-use a IO Pdir entry reduces the number
839 * of MMIO reads needed to flush writes to the PCOM register.
841 d = &(ioc->saved[ioc->saved_cnt]);
844 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
845 int cnt = ioc->saved_cnt;
847 sba_free_range(ioc, d->iova, d->size);
852 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
854 #else /* DELAYED_RESOURCE_CNT == 0 */
855 sba_free_range(ioc, iova, size);
857 /* If fdc's were issued, force fdc's to be visible now */
859 asm volatile("sync" : : );
861 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
862 #endif /* DELAYED_RESOURCE_CNT == 0 */
864 spin_unlock_irqrestore(&ioc->res_lock, flags);
866 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
867 ** For Astro based systems this isn't a big deal WRT performance.
868 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
869 ** we don't need the syncdma. The issue here is I/O MMU cachelines
870 ** are *not* coherent in all cases. May be hwrev dependent.
871 ** Need to investigate more.
872 asm volatile("syncdma");
878 * sba_alloc - allocate/map shared mem for DMA
879 * @hwdev: instance of PCI owned by the driver that's asking.
880 * @size: number of bytes mapped in driver buffer.
881 * @dma_handle: IOVA of new buffer.
883 * See Documentation/DMA-API-HOWTO.txt
885 static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
886 gfp_t gfp, unsigned long attrs)
891 /* only support PCI */
896 ret = (void *) __get_free_pages(gfp, get_order(size));
899 memset(ret, 0, size);
900 *dma_handle = sba_map_single(hwdev, ret, size, 0);
908 * sba_free - free/unmap shared mem for DMA
909 * @hwdev: instance of PCI owned by the driver that's asking.
910 * @size: number of bytes mapped in driver buffer.
911 * @vaddr: virtual address IOVA of "consistent" buffer.
912 * @dma_handler: IO virtual address of "consistent" buffer.
914 * See Documentation/DMA-API-HOWTO.txt
917 sba_free(struct device *hwdev, size_t size, void *vaddr,
918 dma_addr_t dma_handle, unsigned long attrs)
920 sba_unmap_page(hwdev, dma_handle, size, 0, 0);
921 free_pages((unsigned long) vaddr, get_order(size));
926 ** Since 0 is a valid pdir_base index value, can't use that
927 ** to determine if a value is valid or not. Use a flag to indicate
928 ** the SG list entry contains a valid pdir index.
930 #define PIDE_FLAG 0x80000000UL
932 #ifdef SBA_COLLECT_STATS
933 #define IOMMU_MAP_STATS
935 #include "iommu-helpers.h"
937 #ifdef DEBUG_LARGE_SG_ENTRIES
943 * sba_map_sg - map Scatter/Gather list
944 * @dev: instance of PCI owned by the driver that's asking.
945 * @sglist: array of buffer/length pairs
946 * @nents: number of entries in list
947 * @direction: R/W or both.
949 * See Documentation/DMA-API-HOWTO.txt
952 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
953 enum dma_data_direction direction, unsigned long attrs)
956 int coalesced, filled = 0;
959 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
965 /* Fast path single entry scatterlists. */
967 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
968 sglist->length, direction);
969 sg_dma_len(sglist) = sglist->length;
973 spin_lock_irqsave(&ioc->res_lock, flags);
975 #ifdef ASSERT_PDIR_SANITY
976 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
978 sba_dump_sg(ioc, sglist, nents);
979 panic("Check before sba_map_sg()");
983 #ifdef SBA_COLLECT_STATS
988 ** First coalesce the chunks and allocate I/O pdir space
990 ** If this is one DMA stream, we can properly map using the
991 ** correct virtual address associated with each DMA page.
992 ** w/o this association, we wouldn't have coherent DMA!
993 ** Access to the virtual address is what forces a two pass algorithm.
995 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
998 ** Program the I/O Pdir
1000 ** map the virtual addresses to the I/O Pdir
1001 ** o dma_address will contain the pdir index
1002 ** o dma_len will contain the number of bytes to map
1003 ** o address contains the virtual address.
1005 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1007 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1009 asm volatile("sync" : : );
1011 #ifdef ASSERT_PDIR_SANITY
1012 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1014 sba_dump_sg(ioc, sglist, nents);
1015 panic("Check after sba_map_sg()\n");
1019 spin_unlock_irqrestore(&ioc->res_lock, flags);
1021 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
1028 * sba_unmap_sg - unmap Scatter/Gather list
1029 * @dev: instance of PCI owned by the driver that's asking.
1030 * @sglist: array of buffer/length pairs
1031 * @nents: number of entries in list
1032 * @direction: R/W or both.
1034 * See Documentation/DMA-API-HOWTO.txt
1037 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1038 enum dma_data_direction direction, unsigned long attrs)
1041 #ifdef ASSERT_PDIR_SANITY
1042 unsigned long flags;
1045 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1046 __func__, nents, sg_virt(sglist), sglist->length);
1054 #ifdef SBA_COLLECT_STATS
1058 #ifdef ASSERT_PDIR_SANITY
1059 spin_lock_irqsave(&ioc->res_lock, flags);
1060 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1061 spin_unlock_irqrestore(&ioc->res_lock, flags);
1064 while (nents && sg_dma_len(sglist)) {
1066 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
1068 #ifdef SBA_COLLECT_STATS
1069 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1070 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1076 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1078 #ifdef ASSERT_PDIR_SANITY
1079 spin_lock_irqsave(&ioc->res_lock, flags);
1080 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1081 spin_unlock_irqrestore(&ioc->res_lock, flags);
1086 static struct dma_map_ops sba_ops = {
1087 .dma_supported = sba_dma_supported,
1090 .map_page = sba_map_page,
1091 .unmap_page = sba_unmap_page,
1092 .map_sg = sba_map_sg,
1093 .unmap_sg = sba_unmap_sg,
1097 /**************************************************************************
1099 ** SBA PAT PDC support
1101 ** o call pdc_pat_cell_module()
1102 ** o store ranges in PCI "resource" structures
1104 **************************************************************************/
1107 sba_get_pat_resources(struct sba_device *sba_dev)
1111 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1112 ** PAT PDC to program the SBA/LBA directed range registers...this
1113 ** burden may fall on the LBA code since it directly supports the
1114 ** PCI subsystem. It's not clear yet. - ggg
1116 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1118 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1119 Tells where the dvi bits are located in the address.
1120 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1126 /**************************************************************
1128 * Initialization and claim
1130 ***************************************************************/
1131 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1132 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1134 sba_alloc_pdir(unsigned int pdir_size)
1136 unsigned long pdir_base;
1137 unsigned long pdir_order = get_order(pdir_size);
1139 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1140 if (NULL == (void *) pdir_base) {
1141 panic("%s() could not allocate I/O Page Table\n",
1145 /* If this is not PA8700 (PCX-W2)
1146 ** OR newer than ver 2.2
1147 ** OR in a system that doesn't need VINDEX bits from SBA,
1149 ** then we aren't exposed to the HW bug.
1151 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1152 || (boot_cpu_data.pdc.versions > 0x202)
1153 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1154 return (void *) pdir_base;
1157 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1159 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1160 * Ike/Astro can cause silent data corruption. This is only
1161 * a problem if the I/O PDIR is located in memory such that
1162 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1164 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1165 * right physical address, we can either avoid (IOPDIR <= 1MB)
1166 * or minimize (2MB IO Pdir) the problem if we restrict the
1167 * IO Pdir to a maximum size of 2MB-128K (1902K).
1169 * Because we always allocate 2^N sized IO pdirs, either of the
1170 * "bad" regions will be the last 128K if at all. That's easy
1174 if (pdir_order <= (19-12)) {
1175 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1176 /* allocate a new one on 512k alignment */
1177 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1178 /* release original */
1179 free_pages(pdir_base, pdir_order);
1181 pdir_base = new_pdir;
1183 /* release excess */
1184 while (pdir_order < (19-12)) {
1185 new_pdir += pdir_size;
1186 free_pages(new_pdir, pdir_order);
1194 ** Needs to be aligned on an "odd" 1MB boundary.
1196 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1198 /* release original */
1199 free_pages( pdir_base, pdir_order);
1201 /* release first 1MB */
1202 free_pages(new_pdir, 20-12);
1204 pdir_base = new_pdir + 1024*1024;
1206 if (pdir_order > (20-12)) {
1210 ** Flag tells init_bitmap() to mark bad 128k as used
1211 ** and to reduce the size by 128k.
1213 piranha_bad_128k = 1;
1215 new_pdir += 3*1024*1024;
1216 /* release last 1MB */
1217 free_pages(new_pdir, 20-12);
1219 /* release unusable 128KB */
1220 free_pages(new_pdir - 128*1024 , 17-12);
1222 pdir_size -= 128*1024;
1226 memset((void *) pdir_base, 0, pdir_size);
1227 return (void *) pdir_base;
1230 struct ibase_data_struct {
1235 static int setup_ibase_imask_callback(struct device *dev, void *data)
1237 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
1238 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1239 struct parisc_device *lba = to_parisc_device(dev);
1240 struct ibase_data_struct *ibd = data;
1241 int rope_num = (lba->hpa.start >> 13) & 0xf;
1242 if (rope_num >> 3 == ibd->ioc_num)
1243 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1247 /* setup Mercury or Elroy IBASE/IMASK registers. */
1249 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1251 struct ibase_data_struct ibase_data = {
1256 device_for_each_child(&sba->dev, &ibase_data,
1257 setup_ibase_imask_callback);
1260 #ifdef SBA_AGP_SUPPORT
1262 sba_ioc_find_quicksilver(struct device *dev, void *data)
1264 int *agp_found = data;
1265 struct parisc_device *lba = to_parisc_device(dev);
1267 if (IS_QUICKSILVER(lba))
1274 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1276 u32 iova_space_mask;
1277 u32 iova_space_size;
1278 int iov_order, tcnfg;
1279 #ifdef SBA_AGP_SUPPORT
1283 ** Firmware programs the base and size of a "safe IOVA space"
1284 ** (one that doesn't overlap memory or LMMIO space) in the
1285 ** IBASE and IMASK registers.
1287 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL;
1288 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1290 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1291 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1292 iova_space_size /= 2;
1296 ** iov_order is always based on a 1GB IOVA space since we want to
1297 ** turn on the other half for AGP GART.
1299 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1300 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1302 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1303 __func__, ioc->ioc_hpa, iova_space_size >> 20,
1304 iov_order + PAGE_SHIFT);
1306 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1307 get_order(ioc->pdir_size));
1308 if (!ioc->pdir_base)
1309 panic("Couldn't allocate I/O Page Table\n");
1311 memset(ioc->pdir_base, 0, ioc->pdir_size);
1313 DBG_INIT("%s() pdir %p size %x\n",
1314 __func__, ioc->pdir_base, ioc->pdir_size);
1316 #ifdef SBA_HINT_SUPPORT
1317 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1318 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1320 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1321 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1324 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1325 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1327 /* build IMASK for IOC and Elroy */
1328 iova_space_mask = 0xffffffff;
1329 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1330 ioc->imask = iova_space_mask;
1332 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1334 sba_dump_tlb(ioc->ioc_hpa);
1336 setup_ibase_imask(sba, ioc, ioc_num);
1338 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1342 ** Setting the upper bits makes checking for bypass addresses
1343 ** a little faster later on.
1345 ioc->imask |= 0xFFFFFFFF00000000UL;
1348 /* Set I/O PDIR Page size to system page size */
1349 switch (PAGE_SHIFT) {
1350 case 12: tcnfg = 0; break; /* 4K */
1351 case 13: tcnfg = 1; break; /* 8K */
1352 case 14: tcnfg = 2; break; /* 16K */
1353 case 16: tcnfg = 3; break; /* 64K */
1355 panic(__FILE__ "Unsupported system page size %d",
1359 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1362 ** Program the IOC's ibase and enable IOVA translation
1363 ** Bit zero == enable bit.
1365 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1368 ** Clear I/O TLB of any possible entries.
1369 ** (Yes. This is a bit paranoid...but so what)
1371 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1373 #ifdef SBA_AGP_SUPPORT
1376 ** If an AGP device is present, only use half of the IOV space
1377 ** for PCI DMA. Unfortunately we can't know ahead of time
1378 ** whether GART support will actually be used, for now we
1379 ** can just key on any AGP device found in the system.
1380 ** We program the next pdir index after we stop w/ a key for
1381 ** the GART code to handshake on.
1383 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
1385 if (agp_found && sba_reserve_agpgart) {
1386 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1387 __func__, (iova_space_size/2) >> 20);
1388 ioc->pdir_size /= 2;
1389 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
1391 #endif /*SBA_AGP_SUPPORT*/
1395 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1397 u32 iova_space_size, iova_space_mask;
1398 unsigned int pdir_size, iov_order, tcnfg;
1401 ** Determine IOVA Space size from memory size.
1403 ** Ideally, PCI drivers would register the maximum number
1404 ** of DMA they can have outstanding for each device they
1405 ** own. Next best thing would be to guess how much DMA
1406 ** can be outstanding based on PCI Class/sub-class. Both
1407 ** methods still require some "extra" to support PCI
1408 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1410 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1411 ** for DMA hints - ergo only 30 bits max.
1414 iova_space_size = (u32) (totalram_pages/global_ioc_cnt);
1416 /* limit IOVA space size to 1MB-1GB */
1417 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1418 iova_space_size = 1 << (20 - PAGE_SHIFT);
1420 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1421 iova_space_size = 1 << (30 - PAGE_SHIFT);
1425 ** iova space must be log2() in size.
1426 ** thus, pdir/res_map will also be log2().
1427 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1429 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1431 /* iova_space_size is now bytes, not pages */
1432 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1434 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1436 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1439 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT),
1440 iova_space_size>>20,
1441 iov_order + PAGE_SHIFT);
1443 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1445 DBG_INIT("%s() pdir %p size %x\n",
1446 __func__, ioc->pdir_base, pdir_size);
1448 #ifdef SBA_HINT_SUPPORT
1449 /* FIXME : DMA HINTs not used */
1450 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1451 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1453 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1454 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1457 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1459 /* build IMASK for IOC and Elroy */
1460 iova_space_mask = 0xffffffff;
1461 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1464 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1465 ** ibase=0, imask=0xFE000000, size=0x2000000.
1468 ioc->imask = iova_space_mask; /* save it */
1470 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1473 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1474 __func__, ioc->ibase, ioc->imask);
1477 ** FIXME: Hint registers are programmed with default hint
1478 ** values during boot, so hints should be sane even if we
1479 ** can't reprogram them the way drivers want.
1482 setup_ibase_imask(sba, ioc, ioc_num);
1485 ** Program the IOC's ibase and enable IOVA translation
1487 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1488 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1490 /* Set I/O PDIR Page size to system page size */
1491 switch (PAGE_SHIFT) {
1492 case 12: tcnfg = 0; break; /* 4K */
1493 case 13: tcnfg = 1; break; /* 8K */
1494 case 14: tcnfg = 2; break; /* 16K */
1495 case 16: tcnfg = 3; break; /* 64K */
1497 panic(__FILE__ "Unsupported system page size %d",
1501 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
1502 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
1505 ** Clear I/O TLB of any possible entries.
1506 ** (Yes. This is a bit paranoid...but so what)
1508 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1510 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1512 DBG_INIT("%s() DONE\n", __func__);
1517 /**************************************************************************
1519 ** SBA initialization code (HW and SW)
1521 ** o identify SBA chip itself
1522 ** o initialize SBA chip modes (HardFail)
1523 ** o initialize SBA chip modes (HardFail)
1524 ** o FIXME: initialize DMA hints for reasonable defaults
1526 **************************************************************************/
1528 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1530 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1533 static void sba_hw_init(struct sba_device *sba_dev)
1539 if (!is_pdc_pat()) {
1540 /* Shutdown the USB controller on Astro-based workstations.
1541 ** Once we reprogram the IOMMU, the next DMA performed by
1542 ** USB will HPMC the box. USB is only enabled if a
1543 ** keyboard is present and found.
1545 ** With serial console, j6k v5.0 firmware says:
1546 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1548 ** FIXME: Using GFX+USB console at power up but direct
1549 ** linux to serial console is still broken.
1550 ** USB could generate DMA so we must reset USB.
1551 ** The proper sequence would be:
1552 ** o block console output
1553 ** o reset USB device
1554 ** o reprogram serial port
1555 ** o unblock console output
1557 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1558 pdc_io_reset_devices();
1565 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1566 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1569 ** Need to deal with DMA from LAN.
1570 ** Maybe use page zero boot device as a handle to talk
1571 ** to PDC about which device to shutdown.
1573 ** Netbooting, j6k v5.0 firmware says:
1574 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1575 ** ARGH! invalid class.
1577 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1578 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1583 if (!IS_PLUTO(sba_dev->dev)) {
1584 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1585 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1586 __func__, sba_dev->sba_hpa, ioc_ctl);
1587 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1588 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1589 /* j6700 v1.6 firmware sets 0x294f */
1590 /* A500 firmware sets 0x4d */
1592 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1594 #ifdef DEBUG_SBA_INIT
1595 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1596 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1600 if (IS_ASTRO(sba_dev->dev)) {
1602 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1605 sba_dev->chip_resv.name = "Astro Intr Ack";
1606 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1607 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1608 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1611 } else if (IS_PLUTO(sba_dev->dev)) {
1614 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1617 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1618 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1619 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1620 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1623 sba_dev->iommu_resv.name = "IOVA Space";
1624 sba_dev->iommu_resv.start = 0x40000000UL;
1625 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1626 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1630 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1631 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1634 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1636 /* XXX: What about Reo Grande? */
1638 sba_dev->num_ioc = num_ioc;
1639 for (i = 0; i < num_ioc; i++) {
1640 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1643 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1646 * Clear ROPE(N)_CONFIG AO bit.
1647 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1648 * Overrides bit 1 in DMA Hint Sets.
1649 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1651 if (IS_PLUTO(sba_dev->dev)) {
1652 void __iomem *rope_cfg;
1653 unsigned long cfg_val;
1655 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1656 cfg_val = READ_REG(rope_cfg);
1657 cfg_val &= ~IOC_ROPE_AO;
1658 WRITE_REG(cfg_val, rope_cfg);
1662 ** Make sure the box crashes on rope errors.
1664 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1667 /* flush out the last writes */
1668 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1670 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1672 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1673 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1675 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1676 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1677 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1680 if (IS_PLUTO(sba_dev->dev)) {
1681 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1683 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1689 sba_common_init(struct sba_device *sba_dev)
1693 /* add this one to the head of the list (order doesn't matter)
1694 ** This will be useful for debugging - especially if we get coredumps
1696 sba_dev->next = sba_list;
1699 for(i=0; i< sba_dev->num_ioc; i++) {
1701 #ifdef DEBUG_DMB_TRAP
1702 extern void iterate_pages(unsigned long , unsigned long ,
1703 void (*)(pte_t * , unsigned long),
1705 void set_data_memory_break(pte_t * , unsigned long);
1707 /* resource map size dictated by pdir_size */
1708 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1710 /* Second part of PIRANHA BUG */
1711 if (piranha_bad_128k) {
1712 res_size -= (128*1024)/sizeof(u64);
1715 res_size >>= 3; /* convert bit count to byte count */
1716 DBG_INIT("%s() res_size 0x%x\n",
1717 __func__, res_size);
1719 sba_dev->ioc[i].res_size = res_size;
1720 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1722 #ifdef DEBUG_DMB_TRAP
1723 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1724 set_data_memory_break, 0);
1727 if (NULL == sba_dev->ioc[i].res_map)
1729 panic("%s:%s() could not allocate resource map\n",
1730 __FILE__, __func__ );
1733 memset(sba_dev->ioc[i].res_map, 0, res_size);
1734 /* next available IOVP - circular search */
1735 sba_dev->ioc[i].res_hint = (unsigned long *)
1736 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1738 #ifdef ASSERT_PDIR_SANITY
1739 /* Mark first bit busy - ie no IOVA 0 */
1740 sba_dev->ioc[i].res_map[0] = 0x80;
1741 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1744 /* Third (and last) part of PIRANHA BUG */
1745 if (piranha_bad_128k) {
1746 /* region from +1408K to +1536 is un-usable. */
1748 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1749 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1750 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1751 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1753 /* mark that part of the io pdir busy */
1754 while (p_start < p_end)
1759 #ifdef DEBUG_DMB_TRAP
1760 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1761 set_data_memory_break, 0);
1762 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1763 set_data_memory_break, 0);
1766 DBG_INIT("%s() %d res_map %x %p\n",
1767 __func__, i, res_size, sba_dev->ioc[i].res_map);
1770 spin_lock_init(&sba_dev->sba_lock);
1771 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1773 #ifdef DEBUG_SBA_INIT
1775 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1776 * (bit #61, big endian), we have to flush and sync every time
1777 * IO-PDIR is changed in Ike/Astro.
1779 if (ioc_needs_fdc) {
1780 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1782 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1787 #ifdef CONFIG_PROC_FS
1788 static int sba_proc_info(struct seq_file *m, void *p)
1790 struct sba_device *sba_dev = sba_list;
1791 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1792 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1793 #ifdef SBA_COLLECT_STATS
1794 unsigned long avg = 0, min, max;
1798 seq_printf(m, "%s rev %d.%d\n",
1800 (sba_dev->hw_rev & 0x7) + 1,
1801 (sba_dev->hw_rev & 0x18) >> 3);
1802 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1803 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1806 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1807 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1809 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1810 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1811 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1812 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
1815 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
1817 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1818 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1819 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
1821 #ifdef SBA_COLLECT_STATS
1822 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1823 total_pages - ioc->used_pages, ioc->used_pages,
1824 (int)(ioc->used_pages * 100 / total_pages));
1826 min = max = ioc->avg_search[0];
1827 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1828 avg += ioc->avg_search[i];
1829 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1830 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1832 avg /= SBA_SEARCH_SAMPLE;
1833 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1836 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1837 ioc->msingle_calls, ioc->msingle_pages,
1838 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1840 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1841 min = ioc->usingle_calls;
1842 max = ioc->usingle_pages - ioc->usg_pages;
1843 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1844 min, max, (int)((max * 1000)/min));
1846 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1847 ioc->msg_calls, ioc->msg_pages,
1848 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1850 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1851 ioc->usg_calls, ioc->usg_pages,
1852 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1859 sba_proc_open(struct inode *i, struct file *f)
1861 return single_open(f, &sba_proc_info, NULL);
1864 static const struct file_operations sba_proc_fops = {
1865 .owner = THIS_MODULE,
1866 .open = sba_proc_open,
1868 .llseek = seq_lseek,
1869 .release = single_release,
1873 sba_proc_bitmap_info(struct seq_file *m, void *p)
1875 struct sba_device *sba_dev = sba_list;
1876 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1878 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
1879 ioc->res_size, false);
1886 sba_proc_bitmap_open(struct inode *i, struct file *f)
1888 return single_open(f, &sba_proc_bitmap_info, NULL);
1891 static const struct file_operations sba_proc_bitmap_fops = {
1892 .owner = THIS_MODULE,
1893 .open = sba_proc_bitmap_open,
1895 .llseek = seq_lseek,
1896 .release = single_release,
1898 #endif /* CONFIG_PROC_FS */
1900 static struct parisc_device_id sba_tbl[] = {
1901 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1902 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1903 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1904 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1905 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1909 static int sba_driver_callback(struct parisc_device *);
1911 static struct parisc_driver sba_driver = {
1912 .name = MODULE_NAME,
1913 .id_table = sba_tbl,
1914 .probe = sba_driver_callback,
1918 ** Determine if sba should claim this chip (return 0) or not (return 1).
1919 ** If so, initialize the chip and tell other partners in crime they
1922 static int sba_driver_callback(struct parisc_device *dev)
1924 struct sba_device *sba_dev;
1928 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
1929 #ifdef CONFIG_PROC_FS
1930 struct proc_dir_entry *root;
1933 sba_dump_ranges(sba_addr);
1935 /* Read HW Rev First */
1936 func_class = READ_REG(sba_addr + SBA_FCLASS);
1938 if (IS_ASTRO(dev)) {
1939 unsigned long fclass;
1940 static char astro_rev[]="Astro ?.?";
1942 /* Astro is broken...Read HW Rev First */
1943 fclass = READ_REG(sba_addr);
1945 astro_rev[6] = '1' + (char) (fclass & 0x7);
1946 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1947 version = astro_rev;
1949 } else if (IS_IKE(dev)) {
1950 static char ike_rev[] = "Ike rev ?";
1951 ike_rev[8] = '0' + (char) (func_class & 0xff);
1953 } else if (IS_PLUTO(dev)) {
1954 static char pluto_rev[]="Pluto ?.?";
1955 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1956 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1957 version = pluto_rev;
1959 static char reo_rev[] = "REO rev ?";
1960 reo_rev[8] = '0' + (char) (func_class & 0xff);
1964 if (!global_ioc_cnt) {
1965 global_ioc_cnt = count_parisc_driver(&sba_driver);
1967 /* Astro and Pluto have one IOC per SBA */
1968 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
1969 global_ioc_cnt *= 2;
1972 printk(KERN_INFO "%s found %s at 0x%llx\n",
1973 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
1975 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
1977 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1981 parisc_set_drvdata(dev, sba_dev);
1983 for(i=0; i<MAX_IOC; i++)
1984 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1987 sba_dev->hw_rev = func_class;
1988 sba_dev->name = dev->name;
1989 sba_dev->sba_hpa = sba_addr;
1991 sba_get_pat_resources(sba_dev);
1992 sba_hw_init(sba_dev);
1993 sba_common_init(sba_dev);
1995 hppa_dma_ops = &sba_ops;
1997 #ifdef CONFIG_PROC_FS
1998 switch (dev->id.hversion) {
1999 case PLUTO_MCKINLEY_PORT:
2000 root = proc_mckinley_root;
2002 case ASTRO_RUNWAY_PORT:
2003 case IKE_MERCED_PORT:
2005 root = proc_runway_root;
2009 proc_create("sba_iommu", 0, root, &sba_proc_fops);
2010 proc_create("sba_iommu-bitmap", 0, root, &sba_proc_bitmap_fops);
2018 ** One time initialization to let the world know the SBA was found.
2019 ** This is the only routine which is NOT static.
2020 ** Must be called exactly once before pci_init().
2022 void __init sba_init(void)
2024 register_parisc_driver(&sba_driver);
2029 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2030 * @dev: The parisc device.
2032 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2033 * This is cached and used later for PCI DMA Mapping.
2035 void * sba_get_iommu(struct parisc_device *pci_hba)
2037 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2038 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2039 char t = sba_dev->id.hw_type;
2040 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2042 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2044 return &(sba->ioc[iocnum]);
2049 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2050 * @pa_dev: The parisc device.
2051 * @r: resource PCI host controller wants start/end fields assigned.
2053 * For the given parisc PCI controller, determine if any direct ranges
2054 * are routed down the corresponding rope.
2056 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2058 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2059 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2060 char t = sba_dev->id.hw_type;
2062 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2064 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2066 r->start = r->end = 0;
2068 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2069 for (i=0; i<4; i++) {
2071 void __iomem *reg = sba->sba_hpa + i*0x18;
2073 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2074 if ((base & 1) == 0)
2075 continue; /* not enabled */
2077 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2079 if ((size & (ROPES_PER_IOC-1)) != rope)
2080 continue; /* directed down different rope */
2082 r->start = (base & ~1UL) | PCI_F_EXTEND;
2083 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2084 r->end = r->start + size;
2085 r->flags = IORESOURCE_MEM;
2091 * sba_distributed_lmmio - return portion of distributed LMMIO range
2092 * @pa_dev: The parisc device.
2093 * @r: resource PCI host controller wants start/end fields assigned.
2095 * For the given parisc PCI controller, return portion of distributed LMMIO
2096 * range. The distributed LMMIO is always present and it's just a question
2097 * of the base address and size of the range.
2099 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2101 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2102 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2103 char t = sba_dev->id.hw_type;
2105 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2107 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2109 r->start = r->end = 0;
2111 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2112 if ((base & 1) == 0) {
2113 BUG(); /* Gah! Distr Range wasn't enabled! */
2117 r->start = (base & ~1UL) | PCI_F_EXTEND;
2119 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2120 r->start += rope * (size + 1); /* adjust base for this rope */
2121 r->end = r->start + size;
2122 r->flags = IORESOURCE_MEM;