4 ** (c) Copyright 1999 Red Hat Software
5 ** (c) Copyright 1999 SuSE GmbH
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** (c) Copyright 2000 Grant Grundler
8 ** (c) Copyright 2006 Helge Deller
10 ** This program is free software; you can redistribute it and/or modify
11 ** it under the terms of the GNU General Public License as published by
12 ** the Free Software Foundation; either version 2 of the License, or
13 ** (at your option) any later version.
15 ** This module provides access to Dino PCI bus (config/IOport spaces)
16 ** and helps manage Dino IRQ lines.
18 ** Dino interrupt handling is a bit complicated.
19 ** Dino always writes to the broadcast EIR via irr0 for now.
20 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
21 ** Only one processor interrupt is used for the 11 IRQ line
24 ** The different between Built-in Dino and Card-Mode
25 ** dino is in chip initialization and pci device initialization.
27 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port
28 ** BARs are configured and used by the driver. Programming MMIO address
29 ** requires substantial knowledge of available Host I/O address ranges
30 ** is currently not supported. Port/Config accessor functions are the
31 ** same. "BIOS" differences are handled within the existing routines.
35 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
36 ** - added support for the integrated RS232.
40 ** TODO: create a virtual address for each Dino HPA.
41 ** GSC code might be able to do this since IODC data tells us
42 ** how many pages are used. PCI subsystem could (must?) do this
43 ** for PCI drivers devices which implement/use MMIO registers.
46 #include <linux/delay.h>
47 #include <linux/types.h>
48 #include <linux/kernel.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/ioport.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h> /* for struct irqaction */
54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */
59 #include <asm/hardware.h>
66 #define DBG(x...) printk(x)
72 ** Config accessor functions only pass in the 8-bit bus number
73 ** and not the 8-bit "PCI Segment" number. Each Dino will be
74 ** assigned a PCI bus number based on "when" it's discovered.
76 ** The "secondary" bus number is set to this before calling
77 ** pci_scan_bus(). If any PPB's are present, the scan will
78 ** discover them and update the "secondary" and "subordinate"
79 ** fields in Dino's pci_bus structure.
81 ** Changes in the configuration *will* result in a different
82 ** bus number for each dino.
85 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
86 #define is_cujo(id) ((id)->hversion == 0x682)
88 #define DINO_IAR0 0x004
89 #define DINO_IODC_ADDR 0x008
90 #define DINO_IODC_DATA_0 0x008
91 #define DINO_IODC_DATA_1 0x008
92 #define DINO_IRR0 0x00C
93 #define DINO_IAR1 0x010
94 #define DINO_IRR1 0x014
95 #define DINO_IMR 0x018
96 #define DINO_IPR 0x01C
97 #define DINO_TOC_ADDR 0x020
98 #define DINO_ICR 0x024
99 #define DINO_ILR 0x028
100 #define DINO_IO_COMMAND 0x030
101 #define DINO_IO_STATUS 0x034
102 #define DINO_IO_CONTROL 0x038
103 #define DINO_IO_GSC_ERR_RESP 0x040
104 #define DINO_IO_ERR_INFO 0x044
105 #define DINO_IO_PCI_ERR_RESP 0x048
106 #define DINO_IO_FBB_EN 0x05c
107 #define DINO_IO_ADDR_EN 0x060
108 #define DINO_PCI_ADDR 0x064
109 #define DINO_CONFIG_DATA 0x068
110 #define DINO_IO_DATA 0x06c
111 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */
112 #define DINO_GSC2X_CONFIG 0x7b4
113 #define DINO_GMASK 0x800
114 #define DINO_PAMR 0x804
115 #define DINO_PAPR 0x808
116 #define DINO_DAMODE 0x80c
117 #define DINO_PCICMD 0x810
118 #define DINO_PCISTS 0x814
119 #define DINO_MLTIM 0x81c
120 #define DINO_BRDG_FEAT 0x820
121 #define DINO_PCIROR 0x824
122 #define DINO_PCIWOR 0x828
123 #define DINO_TLTIM 0x830
125 #define DINO_IRQS 11 /* bits 0-10 are architected */
126 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
127 #define DINO_LOCAL_IRQS (DINO_IRQS+1)
129 #define DINO_MASK_IRQ(x) (1<<(x))
131 #define PCIINTA 0x001
132 #define PCIINTB 0x002
133 #define PCIINTC 0x004
134 #define PCIINTD 0x008
135 #define PCIINTE 0x010
136 #define PCIINTF 0x020
137 #define GSCEXTINT 0x040
138 /* #define xxx 0x080 - bit 7 is "default" */
139 /* #define xxx 0x100 - bit 8 not used */
140 /* #define xxx 0x200 - bit 9 not used */
141 #define RS232INT 0x400
145 struct pci_hba_data hba; /* 'C' inheritance - must be first */
146 spinlock_t dinosaur_pen;
147 u32 imr; /* IRQ's which are enabled */
148 struct gsc_irq gsc_irq;
149 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
151 unsigned int dino_irr0; /* save most recent IRQ line stat */
155 /* Looks nice and keeps the compiler happy */
156 #define DINO_DEV(d) ({ \
159 (struct dino_device *)__pdata; })
163 * Dino Configuration Space Accessor Functions
166 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
169 * keep the current highest bus count to assist in allocating busses. This
170 * tries to keep a global bus count total so that when we discover an
171 * entirely new bus, it can be given a unique bus number.
173 static int dino_current_bus = 0;
175 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
178 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
179 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
180 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
181 void __iomem *base_addr = d->hba.base_addr;
184 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
186 spin_lock_irqsave(&d->dinosaur_pen, flags);
188 /* tell HW which CFG address */
189 __raw_writel(v, base_addr + DINO_PCI_ADDR);
191 /* generate cfg read cycle */
193 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
194 } else if (size == 2) {
195 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
196 } else if (size == 4) {
197 *val = readl(base_addr + DINO_CONFIG_DATA);
200 spin_unlock_irqrestore(&d->dinosaur_pen, flags);
205 * Dino address stepping "feature":
206 * When address stepping, Dino attempts to drive the bus one cycle too soon
207 * even though the type of cycle (config vs. MMIO) might be different.
208 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
210 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
213 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
214 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
215 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
216 void __iomem *base_addr = d->hba.base_addr;
219 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
221 spin_lock_irqsave(&d->dinosaur_pen, flags);
223 /* avoid address stepping feature */
224 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
225 __raw_readl(base_addr + DINO_CONFIG_DATA);
227 /* tell HW which CFG address */
228 __raw_writel(v, base_addr + DINO_PCI_ADDR);
229 /* generate cfg read cycle */
231 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
232 } else if (size == 2) {
233 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
234 } else if (size == 4) {
235 writel(val, base_addr + DINO_CONFIG_DATA);
238 spin_unlock_irqrestore(&d->dinosaur_pen, flags);
242 static struct pci_ops dino_cfg_ops = {
243 .read = dino_cfg_read,
244 .write = dino_cfg_write,
249 * Dino "I/O Port" Space Accessor Functions
251 * Many PCI devices don't require use of I/O port space (eg Tulip,
252 * NCR720) since they export the same registers to both MMIO and
253 * I/O port space. Performance is going to stink if drivers use
254 * I/O port instead of MMIO.
257 #define DINO_PORT_IN(type, size, mask) \
258 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
261 unsigned long flags; \
262 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
263 /* tell HW which IO Port address */ \
264 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
265 /* generate I/O PORT read cycle */ \
266 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
267 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
271 DINO_PORT_IN(b, 8, 3)
272 DINO_PORT_IN(w, 16, 2)
273 DINO_PORT_IN(l, 32, 0)
275 #define DINO_PORT_OUT(type, size, mask) \
276 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
278 unsigned long flags; \
279 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
280 /* tell HW which IO port address */ \
281 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
282 /* generate cfg write cycle */ \
283 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
284 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
287 DINO_PORT_OUT(b, 8, 3)
288 DINO_PORT_OUT(w, 16, 2)
289 DINO_PORT_OUT(l, 32, 0)
291 static struct pci_port_ops dino_port_ops = {
300 static void dino_mask_irq(struct irq_data *d)
302 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
303 int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
305 DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
307 /* Clear the matching bit in the IMR register */
308 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
309 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
312 static void dino_unmask_irq(struct irq_data *d)
314 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
315 int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
318 DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
321 ** clear pending IRQ bits
323 ** This does NOT change ILR state!
324 ** See comment below for ILR usage.
326 __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
328 /* set the matching bit in the IMR register */
329 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */
330 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
332 /* Emulate "Level Triggered" Interrupt
333 ** Basically, a driver is blowing it if the IRQ line is asserted
334 ** while the IRQ is disabled. But tulip.c seems to do that....
335 ** Give 'em a kluge award and a nice round of applause!
337 ** The gsc_write will generate an interrupt which invokes dino_isr().
338 ** dino_isr() will read IPR and find nothing. But then catch this
339 ** when it also checks ILR.
341 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
342 if (tmp & DINO_MASK_IRQ(local_irq)) {
343 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
345 gsc_writel(dino_dev->gsc_irq.txn_data, dino_dev->gsc_irq.txn_addr);
350 static int dino_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
353 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
354 struct cpumask tmask;
358 if (!cpumask_and(&tmask, dest, cpu_online_mask))
361 cpu_irq = cpu_check_affinity(d, &tmask);
365 dino_dev->gsc_irq.txn_addr = txn_affinity_addr(d->irq, cpu_irq);
366 eim = ((u32) dino_dev->gsc_irq.txn_addr) | dino_dev->gsc_irq.txn_data;
367 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
369 irq_data_update_effective_affinity(d, &tmask);
371 return IRQ_SET_MASK_OK;
375 static struct irq_chip dino_interrupt_type = {
377 .irq_unmask = dino_unmask_irq,
378 .irq_mask = dino_mask_irq,
380 .irq_set_affinity = dino_set_affinity_irq,
386 * Handle a Processor interrupt generated by Dino.
388 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
389 * wedging the CPU. Could be removed or made optional at some point.
391 static irqreturn_t dino_isr(int irq, void *intr_dev)
393 struct dino_device *dino_dev = intr_dev;
397 /* read and acknowledge pending interrupts */
399 dino_dev->dino_irr0 =
401 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
408 int local_irq = __ffs(mask);
409 int irq = dino_dev->global_irq[local_irq];
410 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
411 __func__, irq, intr_dev, mask);
412 generic_handle_irq(irq);
413 mask &= ~(1 << local_irq);
416 /* Support for level triggered IRQ lines.
418 ** Dropping this support would make this routine *much* faster.
419 ** But since PCI requires level triggered IRQ line to share lines...
420 ** device drivers may assume lines are level triggered (and not
421 ** edge triggered like EISA/ISA can be).
423 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
427 printk(KERN_ERR "Dino 0x%px: stuck interrupt %d\n",
428 dino_dev->hba.base_addr, mask);
434 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
436 int irq = gsc_assign_irq(&dino_interrupt_type, dino);
441 dino->global_irq[local_irq] = irq;
444 static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
447 struct dino_device *dino = ctrl;
449 switch (dev->id.sversion) {
450 case 0x00084: irq = 8; break; /* PS/2 */
451 case 0x0008c: irq = 10; break; /* RS232 */
452 case 0x00096: irq = 8; break; /* PS/2 */
453 default: return; /* Unknown */
456 dino_assign_irq(dino, irq, &dev->irq);
461 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
462 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
464 static void quirk_cirrus_cardbus(struct pci_dev *dev)
466 u8 new_irq = dev->irq - 1;
467 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
468 pci_name(dev), dev->irq, new_irq);
471 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
474 /* Check if PCI device is behind a Card-mode Dino. */
475 static int pci_dev_is_behind_card_dino(struct pci_dev *dev)
477 struct dino_device *dino_dev;
479 dino_dev = DINO_DEV(parisc_walk_tree(dev->bus->bridge));
480 return is_card_dino(&dino_dev->hba.dev->id);
483 static void pci_fixup_tulip(struct pci_dev *dev)
485 if (!pci_dev_is_behind_card_dino(dev))
487 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM))
489 pr_warn("%s: HP HSC-PCI Cards with card-mode Dino not yet supported.\n",
491 /* Disable this card by zeroing the PCI resources */
492 memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
493 memset(&dev->resource[1], 0, sizeof(dev->resource[1]));
495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_DEC, PCI_ANY_ID, pci_fixup_tulip);
496 #endif /* CONFIG_TULIP */
501 DBG("dino_bios_init\n");
505 * dino_card_setup - Set up the memory space for a Dino in card mode.
506 * @bus: the bus under this dino
508 * Claim an 8MB chunk of unused IO space and call the generic PCI routines
509 * to set up the addresses of the devices on this bus.
511 #define _8MB 0x00800000UL
513 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
516 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
517 struct resource *res;
521 res = &dino_dev->hba.lmmio_space;
522 res->flags = IORESOURCE_MEM;
523 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
524 dev_name(bus->bridge));
525 res->name = kmalloc(size+1, GFP_KERNEL);
527 strcpy((char *)res->name, name);
529 res->name = dino_dev->hba.lmmio_space.name;
532 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
533 F_EXTEND(0xf0000000UL) | _8MB,
534 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
535 struct pci_dev *dev, *tmp;
537 printk(KERN_ERR "Dino: cannot attach bus %s\n",
538 dev_name(bus->bridge));
539 /* kill the bus, we can't do anything with it */
540 list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
541 list_del(&dev->bus_list);
546 bus->resource[1] = res;
547 bus->resource[0] = &(dino_dev->hba.io_space);
549 /* Now tell dino what range it has */
550 for (i = 1; i < 31; i++) {
551 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
554 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
555 i, res->start, base_addr + DINO_IO_ADDR_EN);
556 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
560 dino_card_fixup(struct pci_dev *dev)
565 ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
566 ** Not sure they were ever productized.
567 ** Die here since we'll die later in dino_inb() anyway.
569 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
570 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
574 ** Set Latency Timer to 0xff (not a shared bus)
575 ** Set CACHELINE_SIZE.
577 dino_cfg_write(dev->bus, dev->devfn,
578 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
581 ** Program INT_LINE for card-mode devices.
582 ** The cards are hardwired according to this algorithm.
583 ** And it doesn't matter if PPB's are present or not since
584 ** the IRQ lines bypass the PPB.
586 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
587 ** The additional "-1" adjusts for skewing the IRQ<->slot.
589 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
590 dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
592 /* Shouldn't really need to do this but it's in case someone tries
593 ** to bypass PCI services and look at the card themselves.
595 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
598 /* The alignment contraints for PCI bridges under dino */
599 #define DINO_BRIDGE_ALIGN 0x100000
603 dino_fixup_bus(struct pci_bus *bus)
606 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
608 DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n",
609 __func__, bus, bus->busn_res.start,
610 bus->bridge->platform_data);
612 /* Firmware doesn't set up card-mode dino, so we have to */
613 if (is_card_dino(&dino_dev->hba.dev->id)) {
614 dino_card_setup(bus, dino_dev->hba.base_addr);
615 } else if (bus->parent) {
618 pci_read_bridge_bases(bus);
621 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
622 if((bus->self->resource[i].flags &
623 (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
626 if(bus->self->resource[i].flags & IORESOURCE_MEM) {
627 /* There's a quirk to alignment of
628 * bridge memory resources: the start
629 * is the alignment and start-end is
630 * the size. However, firmware will
631 * have assigned start and end, so we
632 * need to take this into account */
633 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
634 bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
638 DBG("DEBUG %s assigning %d [%pR]\n",
639 dev_name(&bus->self->dev), i,
640 &bus->self->resource[i]);
641 WARN_ON(pci_assign_resource(bus->self, i));
642 DBG("DEBUG %s after assign %d [%pR]\n",
643 dev_name(&bus->self->dev), i,
644 &bus->self->resource[i]);
649 list_for_each_entry(dev, &bus->devices, bus_list) {
650 if (is_card_dino(&dino_dev->hba.dev->id))
651 dino_card_fixup(dev);
654 ** P2PB's only have 2 BARs, no IRQs.
655 ** I'd like to just ignore them for now.
657 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
658 pcibios_init_bridge(dev);
662 /* null out the ROM resource if there is one (we don't
663 * care about an expansion rom on parisc, since it
664 * usually contains (x86) bios code) */
665 dev->resource[PCI_ROM_RESOURCE].flags = 0;
667 if(dev->irq == 255) {
669 #define DINO_FIX_UNASSIGNED_INTERRUPTS
670 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
672 /* This code tries to assign an unassigned
673 * interrupt. Leave it disabled unless you
674 * *really* know what you're doing since the
675 * pin<->interrupt line mapping varies by bus
680 dino_cfg_read(dev->bus, dev->devfn,
681 PCI_INTERRUPT_PIN, 1, &irq_pin);
682 irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
683 printk(KERN_WARNING "Device %s has undefined IRQ, "
684 "setting to %d\n", pci_name(dev), irq_pin);
685 dino_cfg_write(dev->bus, dev->devfn,
686 PCI_INTERRUPT_LINE, 1, irq_pin);
687 dino_assign_irq(dino_dev, irq_pin, &dev->irq);
690 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
693 /* Adjust INT_LINE for that busses region */
694 dino_assign_irq(dino_dev, dev->irq, &dev->irq);
700 static struct pci_bios_ops dino_bios_ops = {
701 .init = dino_bios_init,
702 .fixup_bus = dino_fixup_bus
707 * Initialise a DINO controller chip
710 dino_card_init(struct dino_device *dino_dev)
712 u32 brdg_feat = 0x00784e05;
713 unsigned long status;
715 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
716 if (status & 0x0000ff80) {
717 __raw_writel(0x00000005,
718 dino_dev->hba.base_addr+DINO_IO_COMMAND);
722 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
723 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
724 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
727 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
729 ** PCX-L processors don't support XQL like Dino wants it.
730 ** PCX-L2 ignore XQL signal and it doesn't matter.
732 brdg_feat &= ~0x4; /* UXQL */
734 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
737 ** Don't enable address decoding until we know which I/O range
738 ** currently is available from the host. Only affects MMIO
739 ** and not I/O port space.
741 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
743 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
744 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
745 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
747 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
748 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
749 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
751 /* Disable PAMR before writing PAPR */
752 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
753 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
754 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
757 ** Dino ERS encourages enabling FBB (0x6f).
758 ** We can't until we know *all* devices below us can support it.
759 ** (Something in device configuration header tells us).
761 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
763 /* Somewhere, the PCI spec says give devices 1 second
764 ** to recover from the #RESET being de-asserted.
765 ** Experience shows most devices only need 10ms.
766 ** This short-cut speeds up booting significantly.
768 mdelay(pci_post_reset_delay);
772 dino_bridge_init(struct dino_device *dino_dev, const char *name)
774 unsigned long io_addr;
775 int result, i, count=0;
776 struct resource *res, *prevres = NULL;
778 * Decoding IO_ADDR_EN only works for Built-in Dino
779 * since PDC has already initialized this.
782 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
784 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
788 res = &dino_dev->hba.lmmio_space;
789 for (i = 0; i < 32; i++) {
790 unsigned long start, end;
792 if((io_addr & (1 << i)) == 0)
795 start = F_EXTEND(0xf0000000UL) | (i << 23);
796 end = start + 8 * 1024 * 1024 - 1;
798 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
801 if(prevres && prevres->end + 1 == start) {
804 if(count >= DINO_MAX_LMMIO_RESOURCES) {
805 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
811 res->flags = IORESOURCE_MEM;
812 res->name = kmalloc(64, GFP_KERNEL);
814 snprintf((char *)res->name, 64, "%s LMMIO %d",
821 res = &dino_dev->hba.lmmio_space;
823 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
824 if(res[i].flags == 0)
827 result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
829 printk(KERN_ERR "%s: failed to claim PCI Bus address "
830 "space %d (%pR)!\n", name, i, &res[i]);
837 static int __init dino_common_init(struct parisc_device *dev,
838 struct dino_device *dino_dev, const char *name)
842 struct resource *res;
844 pcibios_register_hba(&dino_dev->hba);
846 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */
847 pci_port = &dino_port_ops;
850 ** Note: SMP systems can make use of IRR1/IAR1 registers
851 ** But it won't buy much performance except in very
852 ** specific applications/configurations. Note Dino
853 ** still only has 11 IRQ input lines - just map some of them
854 ** to a different processor.
856 dev->irq = gsc_alloc_irq(&dino_dev->gsc_irq);
857 eim = ((u32) dino_dev->gsc_irq.txn_addr) | dino_dev->gsc_irq.txn_data;
860 ** Dino needs a PA "IRQ" to get a processor's attention.
861 ** arch/parisc/kernel/irq.c returns an EIRR bit.
864 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
868 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
870 printk(KERN_WARNING "%s: request_irq() failed with %d\n",
875 /* Support the serial port which is sometimes attached on built-in
879 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
882 ** This enables DINO to generate interrupts when it sees
883 ** any of its inputs *change*. Just asserting an IRQ
884 ** before it's enabled (ie unmasked) isn't good enough.
886 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
889 ** Some platforms don't clear Dino's IRR0 register at boot time.
890 ** Reading will clear it now.
892 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
894 /* allocate I/O Port resource region */
895 res = &dino_dev->hba.io_space;
896 if (!is_cujo(&dev->id)) {
897 res->name = "Dino I/O Port";
899 res->name = "Cujo I/O Port";
901 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
902 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
903 res->flags = IORESOURCE_IO; /* do not mark it busy ! */
904 if (request_resource(&ioport_resource, res) < 0) {
905 printk(KERN_ERR "%s: request I/O Port region failed "
906 "0x%lx/%lx (hpa 0x%px)\n",
907 name, (unsigned long)res->start, (unsigned long)res->end,
908 dino_dev->hba.base_addr);
915 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
916 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
917 #define CUJO_RAVEN_BADPAGE 0x01003000UL
918 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL
920 static const char *dino_vers[] = {
927 static const char *cujo_vers[] = {
932 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
935 ** Determine if dino should claim this chip (return 0) or not (return 1).
936 ** If so, initialize the chip appropriately (card-mode vs bridge mode).
937 ** Much of the initialization is common though.
939 static int __init dino_probe(struct parisc_device *dev)
941 struct dino_device *dino_dev; // Dino specific control struct
942 const char *version = "unknown";
945 LIST_HEAD(resources);
947 unsigned long hpa = dev->hpa.start;
951 if (is_card_dino(&dev->id)) {
952 version = "3.x (card mode)";
954 if (!is_cujo(&dev->id)) {
955 if (dev->id.hversion_rev < 4) {
956 version = dino_vers[dev->id.hversion_rev];
961 if (dev->id.hversion_rev < 2) {
962 version = cujo_vers[dev->id.hversion_rev];
967 printk("%s version %s found at 0x%lx\n", name, version, hpa);
969 if (!request_mem_region(hpa, PAGE_SIZE, name)) {
970 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
976 if (is_cujo && dev->id.hversion_rev == 1) {
977 #ifdef CONFIG_IOMMU_CCIO
978 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
979 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
980 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
981 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
982 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
984 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
987 } else if (!is_cujo && !is_card_dino(&dev->id) &&
988 dev->id.hversion_rev < 3) {
990 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
991 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
992 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
993 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
994 dev->id.hversion_rev);
995 /* REVISIT: why are C200/C240 listed in the README table but not
996 ** "Models affected"? Could be an omission in the original literature.
1000 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
1002 printk("dino_init_chip - couldn't alloc dino_device\n");
1006 dino_dev->hba.dev = dev;
1007 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
1008 dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1009 spin_lock_init(&dino_dev->dinosaur_pen);
1010 dino_dev->hba.iommu = ccio_get_iommu(dev);
1012 if (is_card_dino(&dev->id)) {
1013 dino_card_init(dino_dev);
1015 dino_bridge_init(dino_dev, name);
1018 if (dino_common_init(dev, dino_dev, name))
1021 dev->dev.platform_data = dino_dev;
1023 pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
1024 HBA_PORT_BASE(dino_dev->hba.hba_num));
1025 if (dino_dev->hba.lmmio_space.flags)
1026 pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
1027 dino_dev->hba.lmmio_space_offset);
1028 if (dino_dev->hba.elmmio_space.flags)
1029 pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
1030 dino_dev->hba.lmmio_space_offset);
1031 if (dino_dev->hba.gmmio_space.flags)
1032 pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
1034 dino_dev->hba.bus_num.start = dino_current_bus;
1035 dino_dev->hba.bus_num.end = 255;
1036 dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
1037 pci_add_resource(&resources, &dino_dev->hba.bus_num);
1039 ** It's not used to avoid chicken/egg problems
1040 ** with configuration accessor functions.
1042 dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
1043 dino_current_bus, &dino_cfg_ops, NULL, &resources);
1045 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
1046 dev_name(&dev->dev), dino_current_bus);
1047 pci_free_resource_list(&resources);
1048 /* increment the bus number in case of duplicates */
1053 max = pci_scan_child_bus(bus);
1054 pci_bus_update_busn_res_end(bus, max);
1056 /* This code *depends* on scanning being single threaded
1057 * if it isn't, this global bus number count will fail
1059 dino_current_bus = max + 1;
1060 pci_bus_assign_resources(bus);
1061 pci_bus_add_devices(bus);
1066 * Normally, we would just test sversion. But the Elroy PCI adapter has
1067 * the same sversion as Dino, so we have to check hversion as well.
1068 * Unfortunately, the J2240 PDC reports the wrong hversion for the first
1069 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1070 * For card-mode Dino, most machines report an sversion of 9D. But 715
1071 * and 725 firmware misreport it as 0x08080 for no adequately explained
1074 static const struct parisc_device_id dino_tbl[] __initconst = {
1075 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1076 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1077 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1078 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1079 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1083 static struct parisc_driver dino_driver __refdata = {
1085 .id_table = dino_tbl,
1086 .probe = dino_probe,
1090 * One time initialization to let the world know Dino is here.
1091 * This is the only routine which is NOT static.
1092 * Must be called exactly once before pci_init().
1094 int __init dino_init(void)
1096 register_parisc_driver(&dino_driver);