drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/idr.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kdev_t.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/timer.h>
  43 #include <linux/types.h>
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45 #include <asm/unaligned.h>
  46
  47 #include "nvme.h"
  48
  49 #define NVME_Q_DEPTH            1024
  50 #define NVME_AQ_DEPTH           256
  51 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  52 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  53
  54 /*
  55  * We handle AEN commands ourselves and don't even let the
  56  * block layer know about them.
  57  */
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         void __iomem *bar;
  93         struct work_struct reset_work;
  94         struct work_struct remove_work;
  95         struct timer_list watchdog_timer;
  96         struct mutex shutdown_lock;
  97         bool subsystem;
  98         void __iomem *cmb;
  99         pci_bus_addr_t cmb_bus_addr;
 100         u64 cmb_size;
 101         u32 cmbsz;
 102         u32 cmbloc;
 103         struct nvme_ctrl ctrl;
 104         struct completion ioq_wait;
 105 };
 106
 107 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 108 {
 109         return container_of(ctrl, struct nvme_dev, ctrl);
 110 }
 111
 112 /*
 113  * An NVM Express queue.  Each device has at least two (one for admin
 114  * commands and one for I/O commands).
 115  */
 116 struct nvme_queue {
 117         struct device *q_dmadev;
 118         struct nvme_dev *dev;
 119         char irqname[24];       /* nvme4294967295-65535\0 */
 120         spinlock_t q_lock;
 121         struct nvme_command *sq_cmds;
 122         struct nvme_command __iomem *sq_cmds_io;
 123         volatile struct nvme_completion *cqes;
 124         struct blk_mq_tags **tags;
 125         dma_addr_t sq_dma_addr;
 126         dma_addr_t cq_dma_addr;
 127         u32 __iomem *q_db;
 128         u16 q_depth;
 129         s16 cq_vector;
 130         u16 sq_tail;
 131         u16 cq_head;
 132         u16 qid;
 133         u8 cq_phase;
 134         u8 cqe_seen;
 135 };
 136
 137 /*
 138  * The nvme_iod describes the data in an I/O, including the list of PRP
 139  * entries.  You can't see it in this data structure because C doesn't let
 140  * me express that.  Use nvme_init_iod to ensure there's enough space
 141  * allocated to store the PRP list.
 142  */
 143 struct nvme_iod {
 144         struct nvme_queue *nvmeq;
 145         int aborted;
 146         int npages;             /* In the PRP list. 0 means small pool in use */
 147         int nents;              /* Used in scatterlist */
 148         int length;             /* Of data, in bytes */
 149         dma_addr_t first_dma;
 150         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 151         struct scatterlist *sg;
 152         struct scatterlist inline_sg[0];
 153 };
 154
 155 /*
 156  * Check we didin't inadvertently grow the command struct
 157  */
 158 static inline void _nvme_check_size(void)
 159 {
 160         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 161         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 162         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 169         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 170         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 171         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 172 }
 173
 174 /*
 175  * Max size of iod being embedded in the request payload
 176  */
 177 #define NVME_INT_PAGES          2
 178 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 179
 180 /*
 181  * Will slightly overestimate the number of pages needed.  This is OK
 182  * as it only leads to a small amount of wasted memory for the lifetime of
 183  * the I/O.
 184  */
 185 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 186 {
 187         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 188                                       dev->ctrl.page_size);
 189         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 190 }
 191
 192 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 193                 unsigned int size, unsigned int nseg)
 194 {
 195         return sizeof(__le64 *) * nvme_npages(size, dev) +
 196                         sizeof(struct scatterlist) * nseg;
 197 }
 198
 199 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 200 {
 201         return sizeof(struct nvme_iod) +
 202                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 203 }
 204
 205 static int nvmeq_irq(struct nvme_queue *nvmeq)
 206 {
 207         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 208 }
 209
 210 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 211                                 unsigned int hctx_idx)
 212 {
 213         struct nvme_dev *dev = data;
 214         struct nvme_queue *nvmeq = dev->queues[0];
 215
 216         WARN_ON(hctx_idx != 0);
 217         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 218         WARN_ON(nvmeq->tags);
 219
 220         hctx->driver_data = nvmeq;
 221         nvmeq->tags = &dev->admin_tagset.tags[0];
 222         return 0;
 223 }
 224
 225 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 226 {
 227         struct nvme_queue *nvmeq = hctx->driver_data;
 228
 229         nvmeq->tags = NULL;
 230 }
 231
 232 static int nvme_admin_init_request(void *data, struct request *req,
 233                                 unsigned int hctx_idx, unsigned int rq_idx,
 234                                 unsigned int numa_node)
 235 {
 236         struct nvme_dev *dev = data;
 237         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 238         struct nvme_queue *nvmeq = dev->queues[0];
 239
 240         BUG_ON(!nvmeq);
 241         iod->nvmeq = nvmeq;
 242         return 0;
 243 }
 244
 245 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 246                           unsigned int hctx_idx)
 247 {
 248         struct nvme_dev *dev = data;
 249         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 250
 251         if (!nvmeq->tags)
 252                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 253
 254         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 255         hctx->driver_data = nvmeq;
 256         return 0;
 257 }
 258
 259 static int nvme_init_request(void *data, struct request *req,
 260                                 unsigned int hctx_idx, unsigned int rq_idx,
 261                                 unsigned int numa_node)
 262 {
 263         struct nvme_dev *dev = data;
 264         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 265         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 266
 267         BUG_ON(!nvmeq);
 268         iod->nvmeq = nvmeq;
 269         return 0;
 270 }
 271
 272 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 273 {
 274         struct nvme_dev *dev = set->driver_data;
 275
 276         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 277 }
 278
 279 /**
 280  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 281  * @nvmeq: The queue to use
 282  * @cmd: The command to send
 283  *
 284  * Safe to use from interrupt context
 285  */
 286 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 287                                                 struct nvme_command *cmd)
 288 {
 289         u16 tail = nvmeq->sq_tail;
 290
 291         if (nvmeq->sq_cmds_io)
 292                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 293         else
 294                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 295
 296         if (++tail == nvmeq->q_depth)
 297                 tail = 0;
 298         writel(tail, nvmeq->q_db);
 299         nvmeq->sq_tail = tail;
 300 }
 301
 302 static __le64 **iod_list(struct request *req)
 303 {
 304         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 305         return (__le64 **)(iod->sg + req->nr_phys_segments);
 306 }
 307
 308 static int nvme_init_iod(struct request *rq, unsigned size,
 309                 struct nvme_dev *dev)
 310 {
 311         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 312         int nseg = rq->nr_phys_segments;
 313
 314         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 315                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 316                 if (!iod->sg)
 317                         return BLK_MQ_RQ_QUEUE_BUSY;
 318         } else {
 319                 iod->sg = iod->inline_sg;
 320         }
 321
 322         iod->aborted = 0;
 323         iod->npages = -1;
 324         iod->nents = 0;
 325         iod->length = size;
 326
 327         if (!(rq->cmd_flags & REQ_DONTPREP)) {
 328                 rq->retries = 0;
 329                 rq->cmd_flags |= REQ_DONTPREP;
 330         }
 331         return 0;
 332 }
 333
 334 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 335 {
 336         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 337         const int last_prp = dev->ctrl.page_size / 8 - 1;
 338         int i;
 339         __le64 **list = iod_list(req);
 340         dma_addr_t prp_dma = iod->first_dma;
 341
 342         nvme_cleanup_cmd(req);
 343
 344         if (iod->npages == 0)
 345                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 346         for (i = 0; i < iod->npages; i++) {
 347                 __le64 *prp_list = list[i];
 348                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 349                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 350                 prp_dma = next_prp_dma;
 351         }
 352
 353         if (iod->sg != iod->inline_sg)
 354                 kfree(iod->sg);
 355 }
 356
 357 #ifdef CONFIG_BLK_DEV_INTEGRITY
 358 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 359 {
 360         if (be32_to_cpu(pi->ref_tag) == v)
 361                 pi->ref_tag = cpu_to_be32(p);
 362 }
 363
 364 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 365 {
 366         if (be32_to_cpu(pi->ref_tag) == p)
 367                 pi->ref_tag = cpu_to_be32(v);
 368 }
 369
 370 /**
 371  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 372  *
 373  * The virtual start sector is the one that was originally submitted by the
 374  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 375  * start sector may be different. Remap protection information to match the
 376  * physical LBA on writes, and back to the original seed on reads.
 377  *
 378  * Type 0 and 3 do not have a ref tag, so no remapping required.
 379  */
 380 static void nvme_dif_remap(struct request *req,
 381                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 382 {
 383         struct nvme_ns *ns = req->rq_disk->private_data;
 384         struct bio_integrity_payload *bip;
 385         struct t10_pi_tuple *pi;
 386         void *p, *pmap;
 387         u32 i, nlb, ts, phys, virt;
 388
 389         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 390                 return;
 391
 392         bip = bio_integrity(req->bio);
 393         if (!bip)
 394                 return;
 395
 396         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 397
 398         p = pmap;
 399         virt = bip_get_seed(bip);
 400         phys = nvme_block_nr(ns, blk_rq_pos(req));
 401         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 402         ts = ns->disk->queue->integrity.tuple_size;
 403
 404         for (i = 0; i < nlb; i++, virt++, phys++) {
 405                 pi = (struct t10_pi_tuple *)p;
 406                 dif_swap(phys, virt, pi);
 407                 p += ts;
 408         }
 409         kunmap_atomic(pmap);
 410 }
 411 #else /* CONFIG_BLK_DEV_INTEGRITY */
 412 static void nvme_dif_remap(struct request *req,
 413                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 414 {
 415 }
 416 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 417 {
 418 }
 419 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 420 {
 421 }
 422 #endif
 423
 424 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 425                 int total_len)
 426 {
 427         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 428         struct dma_pool *pool;
 429         int length = total_len;
 430         struct scatterlist *sg = iod->sg;
 431         int dma_len = sg_dma_len(sg);
 432         u64 dma_addr = sg_dma_address(sg);
 433         u32 page_size = dev->ctrl.page_size;
 434         int offset = dma_addr & (page_size - 1);
 435         __le64 *prp_list;
 436         __le64 **list = iod_list(req);
 437         dma_addr_t prp_dma;
 438         int nprps, i;
 439
 440         length -= (page_size - offset);
 441         if (length <= 0)
 442                 return true;
 443
 444         dma_len -= (page_size - offset);
 445         if (dma_len) {
 446                 dma_addr += (page_size - offset);
 447         } else {
 448                 sg = sg_next(sg);
 449                 dma_addr = sg_dma_address(sg);
 450                 dma_len = sg_dma_len(sg);
 451         }
 452
 453         if (length <= page_size) {
 454                 iod->first_dma = dma_addr;
 455                 return true;
 456         }
 457
 458         nprps = DIV_ROUND_UP(length, page_size);
 459         if (nprps <= (256 / 8)) {
 460                 pool = dev->prp_small_pool;
 461                 iod->npages = 0;
 462         } else {
 463                 pool = dev->prp_page_pool;
 464                 iod->npages = 1;
 465         }
 466
 467         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 468         if (!prp_list) {
 469                 iod->first_dma = dma_addr;
 470                 iod->npages = -1;
 471                 return false;
 472         }
 473         list[0] = prp_list;
 474         iod->first_dma = prp_dma;
 475         i = 0;
 476         for (;;) {
 477                 if (i == page_size >> 3) {
 478                         __le64 *old_prp_list = prp_list;
 479                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 480                         if (!prp_list)
 481                                 return false;
 482                         list[iod->npages++] = prp_list;
 483                         prp_list[0] = old_prp_list[i - 1];
 484                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 485                         i = 1;
 486                 }
 487                 prp_list[i++] = cpu_to_le64(dma_addr);
 488                 dma_len -= page_size;
 489                 dma_addr += page_size;
 490                 length -= page_size;
 491                 if (length <= 0)
 492                         break;
 493                 if (dma_len > 0)
 494                         continue;
 495                 BUG_ON(dma_len < 0);
 496                 sg = sg_next(sg);
 497                 dma_addr = sg_dma_address(sg);
 498                 dma_len = sg_dma_len(sg);
 499         }
 500
 501         return true;
 502 }
 503
 504 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 505                 unsigned size, struct nvme_command *cmnd)
 506 {
 507         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 508         struct request_queue *q = req->q;
 509         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 510                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 511         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 512
 513         sg_init_table(iod->sg, req->nr_phys_segments);
 514         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 515         if (!iod->nents)
 516                 goto out;
 517
 518         ret = BLK_MQ_RQ_QUEUE_BUSY;
 519         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 520                                 DMA_ATTR_NO_WARN))
 521                 goto out;
 522
 523         if (!nvme_setup_prps(dev, req, size))
 524                 goto out_unmap;
 525
 526         ret = BLK_MQ_RQ_QUEUE_ERROR;
 527         if (blk_integrity_rq(req)) {
 528                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 529                         goto out_unmap;
 530
 531                 sg_init_table(&iod->meta_sg, 1);
 532                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 533                         goto out_unmap;
 534
 535                 if (rq_data_dir(req))
 536                         nvme_dif_remap(req, nvme_dif_prep);
 537
 538                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 539                         goto out_unmap;
 540         }
 541
 542         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 543         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 544         if (blk_integrity_rq(req))
 545                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 546         return BLK_MQ_RQ_QUEUE_OK;
 547
 548 out_unmap:
 549         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 550 out:
 551         return ret;
 552 }
 553
 554 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 555 {
 556         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 557         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 558                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 559
 560         if (iod->nents) {
 561                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 562                 if (blk_integrity_rq(req)) {
 563                         if (!rq_data_dir(req))
 564                                 nvme_dif_remap(req, nvme_dif_complete);
 565                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 566                 }
 567         }
 568
 569         nvme_free_iod(dev, req);
 570 }
 571
 572 /*
 573  * NOTE: ns is NULL when called on the admin queue.
 574  */
 575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 576                          const struct blk_mq_queue_data *bd)
 577 {
 578         struct nvme_ns *ns = hctx->queue->queuedata;
 579         struct nvme_queue *nvmeq = hctx->driver_data;
 580         struct nvme_dev *dev = nvmeq->dev;
 581         struct request *req = bd->rq;
 582         struct nvme_command cmnd;
 583         unsigned map_len;
 584         int ret = BLK_MQ_RQ_QUEUE_OK;
 585
 586         /*
 587          * If formated with metadata, require the block layer provide a buffer
 588          * unless this namespace is formated such that the metadata can be
 589          * stripped/generated by the controller with PRACT=1.
 590          */
 591         if (ns && ns->ms && !blk_integrity_rq(req)) {
 592                 if (!(ns->pi_type && ns->ms == 8) &&
 593                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 594                         blk_mq_end_request(req, -EFAULT);
 595                         return BLK_MQ_RQ_QUEUE_OK;
 596                 }
 597         }
 598
 599         map_len = nvme_map_len(req);
 600         ret = nvme_init_iod(req, map_len, dev);
 601         if (ret)
 602                 return ret;
 603
 604         ret = nvme_setup_cmd(ns, req, &cmnd);
 605         if (ret)
 606                 goto out;
 607
 608         if (req->nr_phys_segments)
 609                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 610
 611         if (ret)
 612                 goto out;
 613
 614         cmnd.common.command_id = req->tag;
 615         blk_mq_start_request(req);
 616
 617         spin_lock_irq(&nvmeq->q_lock);
 618         if (unlikely(nvmeq->cq_vector < 0)) {
 619                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 620                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 621                 else
 622                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 623                 spin_unlock_irq(&nvmeq->q_lock);
 624                 goto out;
 625         }
 626         __nvme_submit_cmd(nvmeq, &cmnd);
 627         nvme_process_cq(nvmeq);
 628         spin_unlock_irq(&nvmeq->q_lock);
 629         return BLK_MQ_RQ_QUEUE_OK;
 630 out:
 631         nvme_free_iod(dev, req);
 632         return ret;
 633 }
 634
 635 static void nvme_complete_rq(struct request *req)
 636 {
 637         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 638         struct nvme_dev *dev = iod->nvmeq->dev;
 639         int error = 0;
 640
 641         nvme_unmap_data(dev, req);
 642
 643         if (unlikely(req->errors)) {
 644                 if (nvme_req_needs_retry(req, req->errors)) {
 645                         req->retries++;
 646                         nvme_requeue_req(req);
 647                         return;
 648                 }
 649
 650                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 651                         error = req->errors;
 652                 else
 653                         error = nvme_error_status(req->errors);
 654         }
 655
 656         if (unlikely(iod->aborted)) {
 657                 dev_warn(dev->ctrl.device,
 658                         "completing aborted command with status: %04x\n",
 659                         req->errors);
 660         }
 661
 662         blk_mq_end_request(req, error);
 663 }
 664
 665 /* We read the CQE phase first to check if the rest of the entry is valid */
 666 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 667                 u16 phase)
 668 {
 669         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 670 }
 671
 672 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 673 {
 674         u16 head, phase;
 675
 676         head = nvmeq->cq_head;
 677         phase = nvmeq->cq_phase;
 678
 679         while (nvme_cqe_valid(nvmeq, head, phase)) {
 680                 struct nvme_completion cqe = nvmeq->cqes[head];
 681                 struct request *req;
 682
 683                 if (++head == nvmeq->q_depth) {
 684                         head = 0;
 685                         phase = !phase;
 686                 }
 687
 688                 if (tag && *tag == cqe.command_id)
 689                         *tag = -1;
 690
 691                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 692                         dev_warn(nvmeq->dev->ctrl.device,
 693                                 "invalid id %d completed on queue %d\n",
 694                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 695                         continue;
 696                 }
 697
 698                 /*
 699                  * AEN requests are special as they don't time out and can
 700                  * survive any kind of queue freeze and often don't respond to
 701                  * aborts.  We don't even bother to allocate a struct request
 702                  * for them but rather special case them here.
 703                  */
 704                 if (unlikely(nvmeq->qid == 0 &&
 705                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 706                         nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe);
 707                         continue;
 708                 }
 709
 710                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 711                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 712                         memcpy(req->special, &cqe, sizeof(cqe));
 713                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 714
 715         }
 716
 717         /* If the controller ignores the cq head doorbell and continuously
 718          * writes to the queue, it is theoretically possible to wrap around
 719          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 720          * requires that 0.1% of your interrupts are handled, so this isn't
 721          * a big problem.
 722          */
 723         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 724                 return;
 725
 726         if (likely(nvmeq->cq_vector >= 0))
 727                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 728         nvmeq->cq_head = head;
 729         nvmeq->cq_phase = phase;
 730
 731         nvmeq->cqe_seen = 1;
 732 }
 733
 734 static void nvme_process_cq(struct nvme_queue *nvmeq)
 735 {
 736         __nvme_process_cq(nvmeq, NULL);
 737 }
 738
 739 static irqreturn_t nvme_irq(int irq, void *data)
 740 {
 741         irqreturn_t result;
 742         struct nvme_queue *nvmeq = data;
 743         spin_lock(&nvmeq->q_lock);
 744         nvme_process_cq(nvmeq);
 745         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 746         nvmeq->cqe_seen = 0;
 747         spin_unlock(&nvmeq->q_lock);
 748         return result;
 749 }
 750
 751 static irqreturn_t nvme_irq_check(int irq, void *data)
 752 {
 753         struct nvme_queue *nvmeq = data;
 754         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 755                 return IRQ_WAKE_THREAD;
 756         return IRQ_NONE;
 757 }
 758
 759 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 760 {
 761         struct nvme_queue *nvmeq = hctx->driver_data;
 762
 763         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 764                 spin_lock_irq(&nvmeq->q_lock);
 765                 __nvme_process_cq(nvmeq, &tag);
 766                 spin_unlock_irq(&nvmeq->q_lock);
 767
 768                 if (tag == -1)
 769                         return 1;
 770         }
 771
 772         return 0;
 773 }
 774
 775 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 776 {
 777         struct nvme_dev *dev = to_nvme_dev(ctrl);
 778         struct nvme_queue *nvmeq = dev->queues[0];
 779         struct nvme_command c;
 780
 781         memset(&c, 0, sizeof(c));
 782         c.common.opcode = nvme_admin_async_event;
 783         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 784
 785         spin_lock_irq(&nvmeq->q_lock);
 786         __nvme_submit_cmd(nvmeq, &c);
 787         spin_unlock_irq(&nvmeq->q_lock);
 788 }
 789
 790 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 791 {
 792         struct nvme_command c;
 793
 794         memset(&c, 0, sizeof(c));
 795         c.delete_queue.opcode = opcode;
 796         c.delete_queue.qid = cpu_to_le16(id);
 797
 798         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 799 }
 800
 801 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 802                                                 struct nvme_queue *nvmeq)
 803 {
 804         struct nvme_command c;
 805         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 806
 807         /*
 808          * Note: we (ab)use the fact the the prp fields survive if no data
 809          * is attached to the request.
 810          */
 811         memset(&c, 0, sizeof(c));
 812         c.create_cq.opcode = nvme_admin_create_cq;
 813         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 814         c.create_cq.cqid = cpu_to_le16(qid);
 815         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 816         c.create_cq.cq_flags = cpu_to_le16(flags);
 817         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 818
 819         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 820 }
 821
 822 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 823                                                 struct nvme_queue *nvmeq)
 824 {
 825         struct nvme_command c;
 826         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 827
 828         /*
 829          * Note: we (ab)use the fact the the prp fields survive if no data
 830          * is attached to the request.
 831          */
 832         memset(&c, 0, sizeof(c));
 833         c.create_sq.opcode = nvme_admin_create_sq;
 834         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 835         c.create_sq.sqid = cpu_to_le16(qid);
 836         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 837         c.create_sq.sq_flags = cpu_to_le16(flags);
 838         c.create_sq.cqid = cpu_to_le16(qid);
 839
 840         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 841 }
 842
 843 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 844 {
 845         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 846 }
 847
 848 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 849 {
 850         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 851 }
 852
 853 static void abort_endio(struct request *req, int error)
 854 {
 855         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 856         struct nvme_queue *nvmeq = iod->nvmeq;
 857         u16 status = req->errors;
 858
 859         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 860         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 861         blk_mq_free_request(req);
 862 }
 863
 864 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 865 {
 866         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 867         struct nvme_queue *nvmeq = iod->nvmeq;
 868         struct nvme_dev *dev = nvmeq->dev;
 869         struct request *abort_req;
 870         struct nvme_command cmd;
 871
 872         /*
 873          * Shutdown immediately if controller times out while starting. The
 874          * reset work will see the pci device disabled when it gets the forced
 875          * cancellation error. All outstanding requests are completed on
 876          * shutdown, so we return BLK_EH_HANDLED.
 877          */
 878         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 879                 dev_warn(dev->ctrl.device,
 880                          "I/O %d QID %d timeout, disable controller\n",
 881                          req->tag, nvmeq->qid);
 882                 nvme_dev_disable(dev, false);
 883                 req->errors = NVME_SC_CANCELLED;
 884                 return BLK_EH_HANDLED;
 885         }
 886
 887         /*
 888          * Shutdown the controller immediately and schedule a reset if the
 889          * command was already aborted once before and still hasn't been
 890          * returned to the driver, or if this is the admin queue.
 891          */
 892         if (!nvmeq->qid || iod->aborted) {
 893                 dev_warn(dev->ctrl.device,
 894                          "I/O %d QID %d timeout, reset controller\n",
 895                          req->tag, nvmeq->qid);
 896                 nvme_dev_disable(dev, false);
 897                 nvme_reset(dev);
 898
 899                 /*
 900                  * Mark the request as handled, since the inline shutdown
 901                  * forces all outstanding requests to complete.
 902                  */
 903                 req->errors = NVME_SC_CANCELLED;
 904                 return BLK_EH_HANDLED;
 905         }
 906
 907         iod->aborted = 1;
 908
 909         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 910                 atomic_inc(&dev->ctrl.abort_limit);
 911                 return BLK_EH_RESET_TIMER;
 912         }
 913
 914         memset(&cmd, 0, sizeof(cmd));
 915         cmd.abort.opcode = nvme_admin_abort_cmd;
 916         cmd.abort.cid = req->tag;
 917         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 918
 919         dev_warn(nvmeq->dev->ctrl.device,
 920                 "I/O %d QID %d timeout, aborting\n",
 921                  req->tag, nvmeq->qid);
 922
 923         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 924                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 925         if (IS_ERR(abort_req)) {
 926                 atomic_inc(&dev->ctrl.abort_limit);
 927                 return BLK_EH_RESET_TIMER;
 928         }
 929
 930         abort_req->timeout = ADMIN_TIMEOUT;
 931         abort_req->end_io_data = NULL;
 932         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 933
 934         /*
 935          * The aborted req will be completed on receiving the abort req.
 936          * We enable the timer again. If hit twice, it'll cause a device reset,
 937          * as the device then is in a faulty state.
 938          */
 939         return BLK_EH_RESET_TIMER;
 940 }
 941
 942 static void nvme_free_queue(struct nvme_queue *nvmeq)
 943 {
 944         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 945                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 946         if (nvmeq->sq_cmds)
 947                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 948                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 949         kfree(nvmeq);
 950 }
 951
 952 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 953 {
 954         int i;
 955
 956         for (i = dev->queue_count - 1; i >= lowest; i--) {
 957                 struct nvme_queue *nvmeq = dev->queues[i];
 958                 dev->queue_count--;
 959                 dev->queues[i] = NULL;
 960                 nvme_free_queue(nvmeq);
 961         }
 962 }
 963
 964 /**
 965  * nvme_suspend_queue - put queue into suspended state
 966  * @nvmeq - queue to suspend
 967  */
 968 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 969 {
 970         int vector;
 971
 972         spin_lock_irq(&nvmeq->q_lock);
 973         if (nvmeq->cq_vector == -1) {
 974                 spin_unlock_irq(&nvmeq->q_lock);
 975                 return 1;
 976         }
 977         vector = nvmeq_irq(nvmeq);
 978         nvmeq->dev->online_queues--;
 979         nvmeq->cq_vector = -1;
 980         spin_unlock_irq(&nvmeq->q_lock);
 981
 982         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 983                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 984
 985         free_irq(vector, nvmeq);
 986
 987         return 0;
 988 }
 989
 990 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 991 {
 992         struct nvme_queue *nvmeq = dev->queues[0];
 993
 994         if (!nvmeq)
 995                 return;
 996         if (nvme_suspend_queue(nvmeq))
 997                 return;
 998
 999         if (shutdown)
1000                 nvme_shutdown_ctrl(&dev->ctrl);
1001         else
1002                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1003                                                 dev->bar + NVME_REG_CAP));
1004
1005         spin_lock_irq(&nvmeq->q_lock);
1006         nvme_process_cq(nvmeq);
1007         spin_unlock_irq(&nvmeq->q_lock);
1008 }
1009
1010 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1011                                 int entry_size)
1012 {
1013         int q_depth = dev->q_depth;
1014         unsigned q_size_aligned = roundup(q_depth * entry_size,
1015                                           dev->ctrl.page_size);
1016
1017         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1018                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1019                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1020                 q_depth = div_u64(mem_per_q, entry_size);
1021
1022                 /*
1023                  * Ensure the reduced q_depth is above some threshold where it
1024                  * would be better to map queues in system memory with the
1025                  * original depth
1026                  */
1027                 if (q_depth < 64)
1028                         return -ENOMEM;
1029         }
1030
1031         return q_depth;
1032 }
1033
1034 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1035                                 int qid, int depth)
1036 {
1037
1038         /* CMB SQEs will be mapped before creation */
1039         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz))
1040                 return 0;
1041
1042         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1043                                             &nvmeq->sq_dma_addr, GFP_KERNEL);
1044         if (!nvmeq->sq_cmds)
1045                 return -ENOMEM;
1046
1047         return 0;
1048 }
1049
1050 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1051                                                         int depth)
1052 {
1053         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1054         if (!nvmeq)
1055                 return NULL;
1056
1057         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1058                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1059         if (!nvmeq->cqes)
1060                 goto free_nvmeq;
1061
1062         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1063                 goto free_cqdma;
1064
1065         nvmeq->q_dmadev = dev->dev;
1066         nvmeq->dev = dev;
1067         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1068                         dev->ctrl.instance, qid);
1069         spin_lock_init(&nvmeq->q_lock);
1070         nvmeq->cq_head = 0;
1071         nvmeq->cq_phase = 1;
1072         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1073         nvmeq->q_depth = depth;
1074         nvmeq->qid = qid;
1075         nvmeq->cq_vector = -1;
1076         dev->queues[qid] = nvmeq;
1077         dev->queue_count++;
1078
1079         return nvmeq;
1080
1081  free_cqdma:
1082         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1083                                                         nvmeq->cq_dma_addr);
1084  free_nvmeq:
1085         kfree(nvmeq);
1086         return NULL;
1087 }
1088
1089 static int queue_request_irq(struct nvme_queue *nvmeq)
1090 {
1091         if (use_threaded_interrupts)
1092                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1093                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1094         else
1095                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1096                                 nvmeq->irqname, nvmeq);
1097 }
1098
1099 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1100 {
1101         struct nvme_dev *dev = nvmeq->dev;
1102
1103         spin_lock_irq(&nvmeq->q_lock);
1104         nvmeq->sq_tail = 0;
1105         nvmeq->cq_head = 0;
1106         nvmeq->cq_phase = 1;
1107         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1108         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1109         dev->online_queues++;
1110         spin_unlock_irq(&nvmeq->q_lock);
1111 }
1112
1113 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1114 {
1115         struct nvme_dev *dev = nvmeq->dev;
1116         int result;
1117
1118         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1119                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1120                                                       dev->ctrl.page_size);
1121                 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1122                 nvmeq->sq_cmds_io = dev->cmb + offset;
1123         }
1124
1125         nvmeq->cq_vector = qid - 1;
1126         result = adapter_alloc_cq(dev, qid, nvmeq);
1127         if (result < 0)
1128                 goto release_vector;
1129
1130         result = adapter_alloc_sq(dev, qid, nvmeq);
1131         if (result < 0)
1132                 goto release_cq;
1133
1134         nvme_init_queue(nvmeq, qid);
1135         result = queue_request_irq(nvmeq);
1136         if (result < 0)
1137                 goto release_sq;
1138
1139         return result;
1140
1141  release_sq:
1142         dev->online_queues--;
1143         adapter_delete_sq(dev, qid);
1144  release_cq:
1145         adapter_delete_cq(dev, qid);
1146  release_vector:
1147         nvmeq->cq_vector = -1;
1148         return result;
1149 }
1150
1151 static struct blk_mq_ops nvme_mq_admin_ops = {
1152         .queue_rq       = nvme_queue_rq,
1153         .complete       = nvme_complete_rq,
1154         .init_hctx      = nvme_admin_init_hctx,
1155         .exit_hctx      = nvme_admin_exit_hctx,
1156         .init_request   = nvme_admin_init_request,
1157         .timeout        = nvme_timeout,
1158 };
1159
1160 static struct blk_mq_ops nvme_mq_ops = {
1161         .queue_rq       = nvme_queue_rq,
1162         .complete       = nvme_complete_rq,
1163         .init_hctx      = nvme_init_hctx,
1164         .init_request   = nvme_init_request,
1165         .map_queues     = nvme_pci_map_queues,
1166         .timeout        = nvme_timeout,
1167         .poll           = nvme_poll,
1168 };
1169
1170 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1171 {
1172         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1173                 /*
1174                  * If the controller was reset during removal, it's possible
1175                  * user requests may be waiting on a stopped queue. Start the
1176                  * queue to flush these to completion.
1177                  */
1178                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1179                 blk_cleanup_queue(dev->ctrl.admin_q);
1180                 blk_mq_free_tag_set(&dev->admin_tagset);
1181         }
1182 }
1183
1184 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1185 {
1186         if (!dev->ctrl.admin_q) {
1187                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1188                 dev->admin_tagset.nr_hw_queues = 1;
1189
1190                 /*
1191                  * Subtract one to leave an empty queue entry for 'Full Queue'
1192                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1193                  */
1194                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1195                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1196                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1197                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1198                 dev->admin_tagset.driver_data = dev;
1199
1200                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1201                         return -ENOMEM;
1202
1203                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1204                 if (IS_ERR(dev->ctrl.admin_q)) {
1205                         blk_mq_free_tag_set(&dev->admin_tagset);
1206                         return -ENOMEM;
1207                 }
1208                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1209                         nvme_dev_remove_admin(dev);
1210                         dev->ctrl.admin_q = NULL;
1211                         return -ENODEV;
1212                 }
1213         } else
1214                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1215
1216         return 0;
1217 }
1218
1219 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1220 {
1221         int result;
1222         u32 aqa;
1223         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1224         struct nvme_queue *nvmeq;
1225
1226         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1227                                                 NVME_CAP_NSSRC(cap) : 0;
1228
1229         if (dev->subsystem &&
1230             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1231                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1232
1233         result = nvme_disable_ctrl(&dev->ctrl, cap);
1234         if (result < 0)
1235                 return result;
1236
1237         nvmeq = dev->queues[0];
1238         if (!nvmeq) {
1239                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1240                 if (!nvmeq)
1241                         return -ENOMEM;
1242         }
1243
1244         aqa = nvmeq->q_depth - 1;
1245         aqa |= aqa << 16;
1246
1247         writel(aqa, dev->bar + NVME_REG_AQA);
1248         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1249         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1250
1251         result = nvme_enable_ctrl(&dev->ctrl, cap);
1252         if (result)
1253                 return result;
1254
1255         nvmeq->cq_vector = 0;
1256         nvme_init_queue(nvmeq, 0);
1257         result = queue_request_irq(nvmeq);
1258         if (result) {
1259                 nvmeq->cq_vector = -1;
1260                 return result;
1261         }
1262
1263         return result;
1264 }
1265
1266 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1267 {
1268
1269         /* If true, indicates loss of adapter communication, possibly by a
1270          * NVMe Subsystem reset.
1271          */
1272         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1273
1274         /* If there is a reset ongoing, we shouldn't reset again. */
1275         if (dev->ctrl.state == NVME_CTRL_RESETTING)
1276                 return false;
1277
1278         /* We shouldn't reset unless the controller is on fatal error state
1279          * _or_ if we lost the communication with it.
1280          */
1281         if (!(csts & NVME_CSTS_CFS) && !nssro)
1282                 return false;
1283
1284         /* If PCI error recovery process is happening, we cannot reset or
1285          * the recovery mechanism will surely fail.
1286          */
1287         if (pci_channel_offline(to_pci_dev(dev->dev)))
1288                 return false;
1289
1290         return true;
1291 }
1292
1293 static void nvme_watchdog_timer(unsigned long data)
1294 {
1295         struct nvme_dev *dev = (struct nvme_dev *)data;
1296         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1297
1298         /* Skip controllers under certain specific conditions. */
1299         if (nvme_should_reset(dev, csts)) {
1300                 if (!nvme_reset(dev))
1301                         dev_warn(dev->dev,
1302                                 "Failed status: 0x%x, reset controller.\n",
1303                                 csts);
1304                 return;
1305         }
1306
1307         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1308 }
1309
1310 static int nvme_create_io_queues(struct nvme_dev *dev)
1311 {
1312         unsigned i, max;
1313         int ret = 0;
1314
1315         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1316                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1317                         ret = -ENOMEM;
1318                         break;
1319                 }
1320         }
1321
1322         max = min(dev->max_qid, dev->queue_count - 1);
1323         for (i = dev->online_queues; i <= max; i++) {
1324                 ret = nvme_create_queue(dev->queues[i], i);
1325                 if (ret)
1326                         break;
1327         }
1328
1329         /*
1330          * Ignore failing Create SQ/CQ commands, we can continue with less
1331          * than the desired aount of queues, and even a controller without
1332          * I/O queues an still be used to issue admin commands.  This might
1333          * be useful to upgrade a buggy firmware for example.
1334          */
1335         return ret >= 0 ? 0 : ret;
1336 }
1337
1338 static ssize_t nvme_cmb_show(struct device *dev,
1339                              struct device_attribute *attr,
1340                              char *buf)
1341 {
1342         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1343
1344         return snprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1345                        ndev->cmbloc, ndev->cmbsz);
1346 }
1347 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1348
1349 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1350 {
1351         u64 szu, size, offset;
1352         resource_size_t bar_size;
1353         struct pci_dev *pdev = to_pci_dev(dev->dev);
1354         void __iomem *cmb;
1355         int bar;
1356
1357         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1358         if (!(NVME_CMB_SZ(dev->cmbsz)))
1359                 return NULL;
1360         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1361
1362         if (!use_cmb_sqes)
1363                 return NULL;
1364
1365         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1366         size = szu * NVME_CMB_SZ(dev->cmbsz);
1367         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1368         bar = NVME_CMB_BIR(dev->cmbloc);
1369         bar_size = pci_resource_len(pdev, bar);
1370
1371         if (offset > bar_size)
1372                 return NULL;
1373
1374         /*
1375          * Controllers may support a CMB size larger than their BAR,
1376          * for example, due to being behind a bridge. Reduce the CMB to
1377          * the reported size of the BAR
1378          */
1379         if (size > bar_size - offset)
1380                 size = bar_size - offset;
1381
1382         cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1383         if (!cmb)
1384                 return NULL;
1385
1386         dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1387         dev->cmb_size = size;
1388         return cmb;
1389 }
1390
1391 static inline void nvme_release_cmb(struct nvme_dev *dev)
1392 {
1393         if (dev->cmb) {
1394                 iounmap(dev->cmb);
1395                 dev->cmb = NULL;
1396                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1397                                              &dev_attr_cmb.attr, NULL);
1398                 dev->cmbsz = 0;
1399         }
1400 }
1401
1402 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1403 {
1404         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1405 }
1406
1407 static int nvme_setup_io_queues(struct nvme_dev *dev)
1408 {
1409         struct nvme_queue *adminq = dev->queues[0];
1410         struct pci_dev *pdev = to_pci_dev(dev->dev);
1411         int result, nr_io_queues, size;
1412
1413         nr_io_queues = num_online_cpus();
1414         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1415         if (result < 0)
1416                 return result;
1417
1418         if (nr_io_queues == 0)
1419                 return 0;
1420
1421         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1422                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1423                                 sizeof(struct nvme_command));
1424                 if (result > 0)
1425                         dev->q_depth = result;
1426                 else
1427                         nvme_release_cmb(dev);
1428         }
1429
1430         size = db_bar_size(dev, nr_io_queues);
1431         if (size > 8192) {
1432                 iounmap(dev->bar);
1433                 do {
1434                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1435                         if (dev->bar)
1436                                 break;
1437                         if (!--nr_io_queues)
1438                                 return -ENOMEM;
1439                         size = db_bar_size(dev, nr_io_queues);
1440                 } while (1);
1441                 dev->dbs = dev->bar + 4096;
1442                 adminq->q_db = dev->dbs;
1443         }
1444
1445         /* Deregister the admin queue's interrupt */
1446         free_irq(pci_irq_vector(pdev, 0), adminq);
1447
1448         /*
1449          * If we enable msix early due to not intx, disable it again before
1450          * setting up the full range we need.
1451          */
1452         pci_free_irq_vectors(pdev);
1453         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1454                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1455         if (nr_io_queues <= 0)
1456                 return -EIO;
1457         dev->max_qid = nr_io_queues;
1458
1459         /*
1460          * Should investigate if there's a performance win from allocating
1461          * more queues than interrupt vectors; it might allow the submission
1462          * path to scale better, even if the receive path is limited by the
1463          * number of interrupts.
1464          */
1465
1466         result = queue_request_irq(adminq);
1467         if (result) {
1468                 adminq->cq_vector = -1;
1469                 return result;
1470         }
1471         return nvme_create_io_queues(dev);
1472 }
1473
1474 static void nvme_del_queue_end(struct request *req, int error)
1475 {
1476         struct nvme_queue *nvmeq = req->end_io_data;
1477
1478         blk_mq_free_request(req);
1479         complete(&nvmeq->dev->ioq_wait);
1480 }
1481
1482 static void nvme_del_cq_end(struct request *req, int error)
1483 {
1484         struct nvme_queue *nvmeq = req->end_io_data;
1485
1486         if (!error) {
1487                 unsigned long flags;
1488
1489                 /*
1490                  * We might be called with the AQ q_lock held
1491                  * and the I/O queue q_lock should always
1492                  * nest inside the AQ one.
1493                  */
1494                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1495                                         SINGLE_DEPTH_NESTING);
1496                 nvme_process_cq(nvmeq);
1497                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1498         }
1499
1500         nvme_del_queue_end(req, error);
1501 }
1502
1503 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1504 {
1505         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1506         struct request *req;
1507         struct nvme_command cmd;
1508
1509         memset(&cmd, 0, sizeof(cmd));
1510         cmd.delete_queue.opcode = opcode;
1511         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1512
1513         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1514         if (IS_ERR(req))
1515                 return PTR_ERR(req);
1516
1517         req->timeout = ADMIN_TIMEOUT;
1518         req->end_io_data = nvmeq;
1519
1520         blk_execute_rq_nowait(q, NULL, req, false,
1521                         opcode == nvme_admin_delete_cq ?
1522                                 nvme_del_cq_end : nvme_del_queue_end);
1523         return 0;
1524 }
1525
1526 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1527 {
1528         int pass;
1529         unsigned long timeout;
1530         u8 opcode = nvme_admin_delete_sq;
1531
1532         for (pass = 0; pass < 2; pass++) {
1533                 int sent = 0, i = queues;
1534
1535                 reinit_completion(&dev->ioq_wait);
1536  retry:
1537                 timeout = ADMIN_TIMEOUT;
1538                 for (; i > 0; i--, sent++)
1539                         if (nvme_delete_queue(dev->queues[i], opcode))
1540                                 break;
1541
1542                 while (sent--) {
1543                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1544                         if (timeout == 0)
1545                                 return;
1546                         if (i)
1547                                 goto retry;
1548                 }
1549                 opcode = nvme_admin_delete_cq;
1550         }
1551 }
1552
1553 /*
1554  * Return: error value if an error occurred setting up the queues or calling
1555  * Identify Device.  0 if these succeeded, even if adding some of the
1556  * namespaces failed.  At the moment, these failures are silent.  TBD which
1557  * failures should be reported.
1558  */
1559 static int nvme_dev_add(struct nvme_dev *dev)
1560 {
1561         if (!dev->ctrl.tagset) {
1562                 dev->tagset.ops = &nvme_mq_ops;
1563                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1564                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1565                 dev->tagset.numa_node = dev_to_node(dev->dev);
1566                 dev->tagset.queue_depth =
1567                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1568                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1569                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1570                 dev->tagset.driver_data = dev;
1571
1572                 if (blk_mq_alloc_tag_set(&dev->tagset))
1573                         return 0;
1574                 dev->ctrl.tagset = &dev->tagset;
1575         } else {
1576                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1577
1578                 /* Free previously allocated queues that are no longer usable */
1579                 nvme_free_queues(dev, dev->online_queues);
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int nvme_pci_enable(struct nvme_dev *dev)
1586 {
1587         u64 cap;
1588         int result = -ENOMEM;
1589         struct pci_dev *pdev = to_pci_dev(dev->dev);
1590
1591         if (pci_enable_device_mem(pdev))
1592                 return result;
1593
1594         pci_set_master(pdev);
1595
1596         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1597             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1598                 goto disable;
1599
1600         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1601                 result = -ENODEV;
1602                 goto disable;
1603         }
1604
1605         /*
1606          * Some devices and/or platforms don't advertise or work with INTx
1607          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1608          * adjust this later.
1609          */
1610         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1611         if (result < 0)
1612                 return result;
1613
1614         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1615
1616         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1617         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1618         dev->dbs = dev->bar + 4096;
1619
1620         /*
1621          * Temporary fix for the Apple controller found in the MacBook8,1 and
1622          * some MacBook7,1 to avoid controller resets and data loss.
1623          */
1624         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1625                 dev->q_depth = 2;
1626                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1627                         "queue depth=%u to work around controller resets\n",
1628                         dev->q_depth);
1629         }
1630
1631         /*
1632          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1633          * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
1634          * has no name we can pass NULL as final argument to
1635          * sysfs_add_file_to_group.
1636          */
1637
1638         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1639                 dev->cmb = nvme_map_cmb(dev);
1640                 if (dev->cmb) {
1641                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1642                                                     &dev_attr_cmb.attr, NULL))
1643                                 dev_warn(dev->dev,
1644                                          "failed to add sysfs attribute for CMB\n");
1645                 }
1646         }
1647
1648         pci_enable_pcie_error_reporting(pdev);
1649         pci_save_state(pdev);
1650         return 0;
1651
1652  disable:
1653         pci_disable_device(pdev);
1654         return result;
1655 }
1656
1657 static void nvme_dev_unmap(struct nvme_dev *dev)
1658 {
1659         if (dev->bar)
1660                 iounmap(dev->bar);
1661         pci_release_mem_regions(to_pci_dev(dev->dev));
1662 }
1663
1664 static void nvme_pci_disable(struct nvme_dev *dev)
1665 {
1666         struct pci_dev *pdev = to_pci_dev(dev->dev);
1667
1668         nvme_release_cmb(dev);
1669         pci_free_irq_vectors(pdev);
1670
1671         if (pci_is_enabled(pdev)) {
1672                 pci_disable_pcie_error_reporting(pdev);
1673                 pci_disable_device(pdev);
1674         }
1675 }
1676
1677 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1678 {
1679         int i, queues;
1680         u32 csts = -1;
1681
1682         del_timer_sync(&dev->watchdog_timer);
1683
1684         mutex_lock(&dev->shutdown_lock);
1685         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1686                 nvme_stop_queues(&dev->ctrl);
1687                 csts = readl(dev->bar + NVME_REG_CSTS);
1688         }
1689
1690         queues = dev->online_queues - 1;
1691         for (i = dev->queue_count - 1; i > 0; i--)
1692                 nvme_suspend_queue(dev->queues[i]);
1693
1694         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1695                 /* A device might become IO incapable very soon during
1696                  * probe, before the admin queue is configured. Thus,
1697                  * queue_count can be 0 here.
1698                  */
1699                 if (dev->queue_count)
1700                         nvme_suspend_queue(dev->queues[0]);
1701         } else {
1702                 nvme_disable_io_queues(dev, queues);
1703                 nvme_disable_admin_queue(dev, shutdown);
1704         }
1705         nvme_pci_disable(dev);
1706
1707         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1708         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1709         mutex_unlock(&dev->shutdown_lock);
1710 }
1711
1712 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1713 {
1714         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1715                                                 PAGE_SIZE, PAGE_SIZE, 0);
1716         if (!dev->prp_page_pool)
1717                 return -ENOMEM;
1718
1719         /* Optimisation for I/Os between 4k and 128k */
1720         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1721                                                 256, 256, 0);
1722         if (!dev->prp_small_pool) {
1723                 dma_pool_destroy(dev->prp_page_pool);
1724                 return -ENOMEM;
1725         }
1726         return 0;
1727 }
1728
1729 static void nvme_release_prp_pools(struct nvme_dev *dev)
1730 {
1731         dma_pool_destroy(dev->prp_page_pool);
1732         dma_pool_destroy(dev->prp_small_pool);
1733 }
1734
1735 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1736 {
1737         struct nvme_dev *dev = to_nvme_dev(ctrl);
1738
1739         put_device(dev->dev);
1740         if (dev->tagset.tags)
1741                 blk_mq_free_tag_set(&dev->tagset);
1742         if (dev->ctrl.admin_q)
1743                 blk_put_queue(dev->ctrl.admin_q);
1744         kfree(dev->queues);
1745         kfree(dev);
1746 }
1747
1748 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1749 {
1750         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1751
1752         kref_get(&dev->ctrl.kref);
1753         nvme_dev_disable(dev, false);
1754         if (!schedule_work(&dev->remove_work))
1755                 nvme_put_ctrl(&dev->ctrl);
1756 }
1757
1758 static void nvme_reset_work(struct work_struct *work)
1759 {
1760         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1761         int result = -ENODEV;
1762
1763         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
1764                 goto out;
1765
1766         /*
1767          * If we're called to reset a live controller first shut it down before
1768          * moving on.
1769          */
1770         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1771                 nvme_dev_disable(dev, false);
1772
1773         result = nvme_pci_enable(dev);
1774         if (result)
1775                 goto out;
1776
1777         result = nvme_configure_admin_queue(dev);
1778         if (result)
1779                 goto out;
1780
1781         result = nvme_alloc_admin_tags(dev);
1782         if (result)
1783                 goto out;
1784
1785         result = nvme_init_identify(&dev->ctrl);
1786         if (result)
1787                 goto out;
1788
1789         result = nvme_setup_io_queues(dev);
1790         if (result)
1791                 goto out;
1792
1793         /*
1794          * A controller that can not execute IO typically requires user
1795          * intervention to correct. For such degraded controllers, the driver
1796          * should not submit commands the user did not request, so skip
1797          * registering for asynchronous event notification on this condition.
1798          */
1799         if (dev->online_queues > 1)
1800                 nvme_queue_async_events(&dev->ctrl);
1801
1802         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1803
1804         /*
1805          * Keep the controller around but remove all namespaces if we don't have
1806          * any working I/O queue.
1807          */
1808         if (dev->online_queues < 2) {
1809                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1810                 nvme_kill_queues(&dev->ctrl);
1811                 nvme_remove_namespaces(&dev->ctrl);
1812         } else {
1813                 nvme_start_queues(&dev->ctrl);
1814                 nvme_dev_add(dev);
1815         }
1816
1817         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1818                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1819                 goto out;
1820         }
1821
1822         if (dev->online_queues > 1)
1823                 nvme_queue_scan(&dev->ctrl);
1824         return;
1825
1826  out:
1827         nvme_remove_dead_ctrl(dev, result);
1828 }
1829
1830 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1831 {
1832         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1833         struct pci_dev *pdev = to_pci_dev(dev->dev);
1834
1835         nvme_kill_queues(&dev->ctrl);
1836         if (pci_get_drvdata(pdev))
1837                 device_release_driver(&pdev->dev);
1838         nvme_put_ctrl(&dev->ctrl);
1839 }
1840
1841 static int nvme_reset(struct nvme_dev *dev)
1842 {
1843         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1844                 return -ENODEV;
1845         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1846                 return -EBUSY;
1847         if (!queue_work(nvme_workq, &dev->reset_work))
1848                 return -EBUSY;
1849         return 0;
1850 }
1851
1852 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1853 {
1854         *val = readl(to_nvme_dev(ctrl)->bar + off);
1855         return 0;
1856 }
1857
1858 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1859 {
1860         writel(val, to_nvme_dev(ctrl)->bar + off);
1861         return 0;
1862 }
1863
1864 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1865 {
1866         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
1867         return 0;
1868 }
1869
1870 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1871 {
1872         struct nvme_dev *dev = to_nvme_dev(ctrl);
1873         int ret = nvme_reset(dev);
1874
1875         if (!ret)
1876                 flush_work(&dev->reset_work);
1877         return ret;
1878 }
1879
1880 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1881         .name                   = "pcie",
1882         .module                 = THIS_MODULE,
1883         .reg_read32             = nvme_pci_reg_read32,
1884         .reg_write32            = nvme_pci_reg_write32,
1885         .reg_read64             = nvme_pci_reg_read64,
1886         .reset_ctrl             = nvme_pci_reset_ctrl,
1887         .free_ctrl              = nvme_pci_free_ctrl,
1888         .submit_async_event     = nvme_pci_submit_async_event,
1889 };
1890
1891 static int nvme_dev_map(struct nvme_dev *dev)
1892 {
1893         struct pci_dev *pdev = to_pci_dev(dev->dev);
1894
1895         if (pci_request_mem_regions(pdev, "nvme"))
1896                 return -ENODEV;
1897
1898         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1899         if (!dev->bar)
1900                 goto release;
1901
1902        return 0;
1903   release:
1904        pci_release_mem_regions(pdev);
1905        return -ENODEV;
1906 }
1907
1908 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1909 {
1910         int node, result = -ENOMEM;
1911         struct nvme_dev *dev;
1912
1913         node = dev_to_node(&pdev->dev);
1914         if (node == NUMA_NO_NODE)
1915                 set_dev_node(&pdev->dev, first_memory_node);
1916
1917         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1918         if (!dev)
1919                 return -ENOMEM;
1920         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1921                                                         GFP_KERNEL, node);
1922         if (!dev->queues)
1923                 goto free;
1924
1925         dev->dev = get_device(&pdev->dev);
1926         pci_set_drvdata(pdev, dev);
1927
1928         result = nvme_dev_map(dev);
1929         if (result)
1930                 goto put_pci;
1931
1932         INIT_WORK(&dev->reset_work, nvme_reset_work);
1933         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1934         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1935                 (unsigned long)dev);
1936         mutex_init(&dev->shutdown_lock);
1937         init_completion(&dev->ioq_wait);
1938
1939         result = nvme_setup_prp_pools(dev);
1940         if (result)
1941                 goto unmap;
1942
1943         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1944                         id->driver_data);
1945         if (result)
1946                 goto release_pools;
1947
1948         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
1949         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1950
1951         queue_work(nvme_workq, &dev->reset_work);
1952         return 0;
1953
1954  release_pools:
1955         nvme_release_prp_pools(dev);
1956  unmap:
1957         nvme_dev_unmap(dev);
1958  put_pci:
1959         put_device(dev->dev);
1960  free:
1961         kfree(dev->queues);
1962         kfree(dev);
1963         return result;
1964 }
1965
1966 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1967 {
1968         struct nvme_dev *dev = pci_get_drvdata(pdev);
1969
1970         if (prepare)
1971                 nvme_dev_disable(dev, false);
1972         else
1973                 nvme_reset(dev);
1974 }
1975
1976 static void nvme_shutdown(struct pci_dev *pdev)
1977 {
1978         struct nvme_dev *dev = pci_get_drvdata(pdev);
1979         nvme_dev_disable(dev, true);
1980 }
1981
1982 /*
1983  * The driver's remove may be called on a device in a partially initialized
1984  * state. This function must not have any dependencies on the device state in
1985  * order to proceed.
1986  */
1987 static void nvme_remove(struct pci_dev *pdev)
1988 {
1989         struct nvme_dev *dev = pci_get_drvdata(pdev);
1990
1991         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1992
1993         cancel_work_sync(&dev->reset_work);
1994         pci_set_drvdata(pdev, NULL);
1995
1996         if (!pci_device_is_present(pdev)) {
1997                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1998                 nvme_dev_disable(dev, false);
1999         }
2000
2001         flush_work(&dev->reset_work);
2002         nvme_uninit_ctrl(&dev->ctrl);
2003         nvme_dev_disable(dev, true);
2004         nvme_dev_remove_admin(dev);
2005         nvme_free_queues(dev, 0);
2006         nvme_release_prp_pools(dev);
2007         nvme_dev_unmap(dev);
2008         nvme_put_ctrl(&dev->ctrl);
2009 }
2010
2011 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2012 {
2013         int ret = 0;
2014
2015         if (numvfs == 0) {
2016                 if (pci_vfs_assigned(pdev)) {
2017                         dev_warn(&pdev->dev,
2018                                 "Cannot disable SR-IOV VFs while assigned\n");
2019                         return -EPERM;
2020                 }
2021                 pci_disable_sriov(pdev);
2022                 return 0;
2023         }
2024
2025         ret = pci_enable_sriov(pdev, numvfs);
2026         return ret ? ret : numvfs;
2027 }
2028
2029 #ifdef CONFIG_PM_SLEEP
2030 static int nvme_suspend(struct device *dev)
2031 {
2032         struct pci_dev *pdev = to_pci_dev(dev);
2033         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2034
2035         nvme_dev_disable(ndev, true);
2036         return 0;
2037 }
2038
2039 static int nvme_resume(struct device *dev)
2040 {
2041         struct pci_dev *pdev = to_pci_dev(dev);
2042         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2043
2044         nvme_reset(ndev);
2045         return 0;
2046 }
2047 #endif
2048
2049 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2050
2051 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2052                                                 pci_channel_state_t state)
2053 {
2054         struct nvme_dev *dev = pci_get_drvdata(pdev);
2055
2056         /*
2057          * A frozen channel requires a reset. When detected, this method will
2058          * shutdown the controller to quiesce. The controller will be restarted
2059          * after the slot reset through driver's slot_reset callback.
2060          */
2061         switch (state) {
2062         case pci_channel_io_normal:
2063                 return PCI_ERS_RESULT_CAN_RECOVER;
2064         case pci_channel_io_frozen:
2065                 dev_warn(dev->ctrl.device,
2066                         "frozen state error detected, reset controller\n");
2067                 nvme_dev_disable(dev, false);
2068                 return PCI_ERS_RESULT_NEED_RESET;
2069         case pci_channel_io_perm_failure:
2070                 dev_warn(dev->ctrl.device,
2071                         "failure state error detected, request disconnect\n");
2072                 return PCI_ERS_RESULT_DISCONNECT;
2073         }
2074         return PCI_ERS_RESULT_NEED_RESET;
2075 }
2076
2077 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2078 {
2079         struct nvme_dev *dev = pci_get_drvdata(pdev);
2080
2081         dev_info(dev->ctrl.device, "restart after slot reset\n");
2082         pci_restore_state(pdev);
2083         nvme_reset(dev);
2084         return PCI_ERS_RESULT_RECOVERED;
2085 }
2086
2087 static void nvme_error_resume(struct pci_dev *pdev)
2088 {
2089         pci_cleanup_aer_uncorrect_error_status(pdev);
2090 }
2091
2092 static const struct pci_error_handlers nvme_err_handler = {
2093         .error_detected = nvme_error_detected,
2094         .slot_reset     = nvme_slot_reset,
2095         .resume         = nvme_error_resume,
2096         .reset_notify   = nvme_reset_notify,
2097 };
2098
2099 /* Move to pci_ids.h later */
2100 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2101
2102 static const struct pci_device_id nvme_id_table[] = {
2103         { PCI_VDEVICE(INTEL, 0x0953),
2104                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2105                                 NVME_QUIRK_DISCARD_ZEROES, },
2106         { PCI_VDEVICE(INTEL, 0x0a53),
2107                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2108                                 NVME_QUIRK_DISCARD_ZEROES, },
2109         { PCI_VDEVICE(INTEL, 0x0a54),
2110                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2111                                 NVME_QUIRK_DISCARD_ZEROES, },
2112         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2113                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2114         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2115                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2116         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
2117                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2118         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2119                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2120         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2121         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2122         { 0, }
2123 };
2124 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2125
2126 static struct pci_driver nvme_driver = {
2127         .name           = "nvme",
2128         .id_table       = nvme_id_table,
2129         .probe          = nvme_probe,
2130         .remove         = nvme_remove,
2131         .shutdown       = nvme_shutdown,
2132         .driver         = {
2133                 .pm     = &nvme_dev_pm_ops,
2134         },
2135         .sriov_configure = nvme_pci_sriov_configure,
2136         .err_handler    = &nvme_err_handler,
2137 };
2138
2139 static int __init nvme_init(void)
2140 {
2141         int result;
2142
2143         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2144         if (!nvme_workq)
2145                 return -ENOMEM;
2146
2147         result = pci_register_driver(&nvme_driver);
2148         if (result)
2149                 destroy_workqueue(nvme_workq);
2150         return result;
2151 }
2152
2153 static void __exit nvme_exit(void)
2154 {
2155         pci_unregister_driver(&nvme_driver);
2156         destroy_workqueue(nvme_workq);
2157         _nvme_check_size();
2158 }
2159
2160 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2161 MODULE_LICENSE("GPL");
2162 MODULE_VERSION("1.0");
2163 module_init(nvme_init);
2164 module_exit(nvme_exit);