2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/poison.h>
30 #include <linux/t10-pi.h>
31 #include <linux/timer.h>
32 #include <linux/types.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include <asm/unaligned.h>
35 #include <linux/sed-opal.h>
39 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
40 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 * We handle AEN commands ourselves and don't even let the
44 * block layer know about them.
46 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0);
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0644);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
60 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
61 static const struct kernel_param_ops io_queue_depth_ops = {
62 .set = io_queue_depth_set,
66 static int io_queue_depth = 1024;
67 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
68 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
73 static void nvme_process_cq(struct nvme_queue *nvmeq);
74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
77 * Represents an NVM Express device. Each nvme_dev is a PCI function.
80 struct nvme_queue *queues;
81 struct blk_mq_tag_set tagset;
82 struct blk_mq_tag_set admin_tagset;
85 struct dma_pool *prp_page_pool;
86 struct dma_pool *prp_small_pool;
87 unsigned online_queues;
92 unsigned long bar_mapped_size;
93 struct work_struct remove_work;
94 struct mutex shutdown_lock;
97 pci_bus_addr_t cmb_bus_addr;
101 struct nvme_ctrl ctrl;
102 struct completion ioq_wait;
104 /* shadow doorbell buffer support: */
106 dma_addr_t dbbuf_dbs_dma_addr;
108 dma_addr_t dbbuf_eis_dma_addr;
110 /* host memory buffer support: */
112 u32 nr_host_mem_descs;
113 dma_addr_t host_mem_descs_dma;
114 struct nvme_host_mem_buf_desc *host_mem_descs;
115 void **host_mem_desc_bufs;
118 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
122 ret = kstrtoint(val, 10, &n);
123 if (ret != 0 || n < 2)
126 return param_set_int(val, kp);
129 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
131 return qid * 2 * stride;
134 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
136 return (qid * 2 + 1) * stride;
139 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
141 return container_of(ctrl, struct nvme_dev, ctrl);
145 * An NVM Express queue. Each device has at least two (one for admin
146 * commands and one for I/O commands).
149 struct device *q_dmadev;
150 struct nvme_dev *dev;
152 struct nvme_command *sq_cmds;
153 struct nvme_command __iomem *sq_cmds_io;
154 volatile struct nvme_completion *cqes;
155 struct blk_mq_tags **tags;
156 dma_addr_t sq_dma_addr;
157 dma_addr_t cq_dma_addr;
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
175 * me express that. Use nvme_init_iod to ensure there's enough space
176 * allocated to store the PRP list.
179 struct nvme_request req;
180 struct nvme_queue *nvmeq;
182 int npages; /* In the PRP list. 0 means small pool in use */
183 int nents; /* Used in scatterlist */
184 int length; /* Of data, in bytes */
185 dma_addr_t first_dma;
186 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
187 struct scatterlist *sg;
188 struct scatterlist inline_sg[0];
192 * Check we didin't inadvertently grow the command struct
194 static inline void _nvme_check_size(void)
196 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
206 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
208 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
211 static inline unsigned int nvme_dbbuf_size(u32 stride)
213 return ((num_possible_cpus() + 1) * 8 * stride);
216 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
218 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
223 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
224 &dev->dbbuf_dbs_dma_addr,
228 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
229 &dev->dbbuf_eis_dma_addr,
231 if (!dev->dbbuf_eis) {
232 dma_free_coherent(dev->dev, mem_size,
233 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
234 dev->dbbuf_dbs = NULL;
241 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
243 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
245 if (dev->dbbuf_dbs) {
246 dma_free_coherent(dev->dev, mem_size,
247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
248 dev->dbbuf_dbs = NULL;
250 if (dev->dbbuf_eis) {
251 dma_free_coherent(dev->dev, mem_size,
252 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
253 dev->dbbuf_eis = NULL;
257 static void nvme_dbbuf_init(struct nvme_dev *dev,
258 struct nvme_queue *nvmeq, int qid)
260 if (!dev->dbbuf_dbs || !qid)
263 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
264 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
265 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
266 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
269 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
274 nvmeq->dbbuf_sq_db = NULL;
275 nvmeq->dbbuf_cq_db = NULL;
276 nvmeq->dbbuf_sq_ei = NULL;
277 nvmeq->dbbuf_cq_ei = NULL;
280 static void nvme_dbbuf_set(struct nvme_dev *dev)
282 struct nvme_command c;
288 memset(&c, 0, sizeof(c));
289 c.dbbuf.opcode = nvme_admin_dbbuf;
290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
295 /* Free memory and continue on */
296 nvme_dbbuf_dma_free(dev);
298 for (i = 1; i <= dev->online_queues; i++)
299 nvme_dbbuf_free(&dev->queues[i]);
303 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
305 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
308 /* Update dbbuf and return true if an MMIO is required */
309 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
310 volatile u32 *dbbuf_ei)
316 * Ensure that the queue is written before updating
317 * the doorbell in memory
321 old_value = *dbbuf_db;
325 * Ensure that the doorbell is updated before reading the event
326 * index from memory. The controller needs to provide similar
327 * ordering to ensure the envent index is updated before reading
332 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
340 * Max size of iod being embedded in the request payload
342 #define NVME_INT_PAGES 2
343 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
346 * Will slightly overestimate the number of pages needed. This is OK
347 * as it only leads to a small amount of wasted memory for the lifetime of
350 static int nvme_npages(unsigned size, struct nvme_dev *dev)
352 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
353 dev->ctrl.page_size);
354 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
357 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
358 unsigned int size, unsigned int nseg)
360 return sizeof(__le64 *) * nvme_npages(size, dev) +
361 sizeof(struct scatterlist) * nseg;
364 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
366 return sizeof(struct nvme_iod) +
367 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
371 unsigned int hctx_idx)
373 struct nvme_dev *dev = data;
374 struct nvme_queue *nvmeq = &dev->queues[0];
376 WARN_ON(hctx_idx != 0);
377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
378 WARN_ON(nvmeq->tags);
380 hctx->driver_data = nvmeq;
381 nvmeq->tags = &dev->admin_tagset.tags[0];
385 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
387 struct nvme_queue *nvmeq = hctx->driver_data;
392 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
393 unsigned int hctx_idx)
395 struct nvme_dev *dev = data;
396 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
399 nvmeq->tags = &dev->tagset.tags[hctx_idx];
401 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
402 hctx->driver_data = nvmeq;
406 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
407 unsigned int hctx_idx, unsigned int numa_node)
409 struct nvme_dev *dev = set->driver_data;
410 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
411 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
412 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
419 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
421 struct nvme_dev *dev = set->driver_data;
423 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
427 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
428 * @nvmeq: The queue to use
429 * @cmd: The command to send
431 * Safe to use from interrupt context
433 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
434 struct nvme_command *cmd)
436 u16 tail = nvmeq->sq_tail;
438 if (nvmeq->sq_cmds_io)
439 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
441 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
443 if (++tail == nvmeq->q_depth)
445 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
447 writel(tail, nvmeq->q_db);
448 nvmeq->sq_tail = tail;
451 static __le64 **iod_list(struct request *req)
453 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
454 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
457 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
459 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
460 int nseg = blk_rq_nr_phys_segments(rq);
461 unsigned int size = blk_rq_payload_bytes(rq);
463 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
464 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
466 return BLK_STS_RESOURCE;
468 iod->sg = iod->inline_sg;
479 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
481 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
482 const int last_prp = dev->ctrl.page_size / 8 - 1;
484 __le64 **list = iod_list(req);
485 dma_addr_t prp_dma = iod->first_dma;
487 if (iod->npages == 0)
488 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
489 for (i = 0; i < iod->npages; i++) {
490 __le64 *prp_list = list[i];
491 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
492 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
493 prp_dma = next_prp_dma;
496 if (iod->sg != iod->inline_sg)
500 #ifdef CONFIG_BLK_DEV_INTEGRITY
501 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
503 if (be32_to_cpu(pi->ref_tag) == v)
504 pi->ref_tag = cpu_to_be32(p);
507 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
509 if (be32_to_cpu(pi->ref_tag) == p)
510 pi->ref_tag = cpu_to_be32(v);
514 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
516 * The virtual start sector is the one that was originally submitted by the
517 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
518 * start sector may be different. Remap protection information to match the
519 * physical LBA on writes, and back to the original seed on reads.
521 * Type 0 and 3 do not have a ref tag, so no remapping required.
523 static void nvme_dif_remap(struct request *req,
524 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
526 struct nvme_ns *ns = req->rq_disk->private_data;
527 struct bio_integrity_payload *bip;
528 struct t10_pi_tuple *pi;
530 u32 i, nlb, ts, phys, virt;
532 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
535 bip = bio_integrity(req->bio);
539 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
542 virt = bip_get_seed(bip);
543 phys = nvme_block_nr(ns, blk_rq_pos(req));
544 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
545 ts = ns->disk->queue->integrity.tuple_size;
547 for (i = 0; i < nlb; i++, virt++, phys++) {
548 pi = (struct t10_pi_tuple *)p;
549 dif_swap(phys, virt, pi);
554 #else /* CONFIG_BLK_DEV_INTEGRITY */
555 static void nvme_dif_remap(struct request *req,
556 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
559 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
562 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
567 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
570 struct scatterlist *sg;
572 for_each_sg(sgl, sg, nents, i) {
573 dma_addr_t phys = sg_phys(sg);
574 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
575 "dma_address:%pad dma_length:%d\n",
576 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
581 static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req)
583 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
584 struct dma_pool *pool;
585 int length = blk_rq_payload_bytes(req);
586 struct scatterlist *sg = iod->sg;
587 int dma_len = sg_dma_len(sg);
588 u64 dma_addr = sg_dma_address(sg);
589 u32 page_size = dev->ctrl.page_size;
590 int offset = dma_addr & (page_size - 1);
592 __le64 **list = iod_list(req);
596 length -= (page_size - offset);
602 dma_len -= (page_size - offset);
604 dma_addr += (page_size - offset);
607 dma_addr = sg_dma_address(sg);
608 dma_len = sg_dma_len(sg);
611 if (length <= page_size) {
612 iod->first_dma = dma_addr;
616 nprps = DIV_ROUND_UP(length, page_size);
617 if (nprps <= (256 / 8)) {
618 pool = dev->prp_small_pool;
621 pool = dev->prp_page_pool;
625 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
627 iod->first_dma = dma_addr;
629 return BLK_STS_RESOURCE;
632 iod->first_dma = prp_dma;
635 if (i == page_size >> 3) {
636 __le64 *old_prp_list = prp_list;
637 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
639 return BLK_STS_RESOURCE;
640 list[iod->npages++] = prp_list;
641 prp_list[0] = old_prp_list[i - 1];
642 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
645 prp_list[i++] = cpu_to_le64(dma_addr);
646 dma_len -= page_size;
647 dma_addr += page_size;
653 if (unlikely(dma_len < 0))
656 dma_addr = sg_dma_address(sg);
657 dma_len = sg_dma_len(sg);
663 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->nents);
666 return BLK_STS_IOERR;
669 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
670 struct nvme_command *cmnd)
672 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
673 struct request_queue *q = req->q;
674 enum dma_data_direction dma_dir = rq_data_dir(req) ?
675 DMA_TO_DEVICE : DMA_FROM_DEVICE;
676 blk_status_t ret = BLK_STS_IOERR;
678 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
679 iod->nents = blk_rq_map_sg(q, req, iod->sg);
683 ret = BLK_STS_RESOURCE;
684 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
688 ret = nvme_setup_prps(dev, req);
689 if (ret != BLK_STS_OK)
693 if (blk_integrity_rq(req)) {
694 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
697 sg_init_table(&iod->meta_sg, 1);
698 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
701 if (req_op(req) == REQ_OP_WRITE)
702 nvme_dif_remap(req, nvme_dif_prep);
704 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
708 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
709 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
710 if (blk_integrity_rq(req))
711 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
715 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
720 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
722 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
723 enum dma_data_direction dma_dir = rq_data_dir(req) ?
724 DMA_TO_DEVICE : DMA_FROM_DEVICE;
727 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
728 if (blk_integrity_rq(req)) {
729 if (req_op(req) == REQ_OP_READ)
730 nvme_dif_remap(req, nvme_dif_complete);
731 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
735 nvme_cleanup_cmd(req);
736 nvme_free_iod(dev, req);
740 * NOTE: ns is NULL when called on the admin queue.
742 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
743 const struct blk_mq_queue_data *bd)
745 struct nvme_ns *ns = hctx->queue->queuedata;
746 struct nvme_queue *nvmeq = hctx->driver_data;
747 struct nvme_dev *dev = nvmeq->dev;
748 struct request *req = bd->rq;
749 struct nvme_command cmnd;
752 ret = nvme_setup_cmd(ns, req, &cmnd);
756 ret = nvme_init_iod(req, dev);
760 if (blk_rq_nr_phys_segments(req)) {
761 ret = nvme_map_data(dev, req, &cmnd);
763 goto out_cleanup_iod;
766 blk_mq_start_request(req);
768 spin_lock_irq(&nvmeq->q_lock);
769 if (unlikely(nvmeq->cq_vector < 0)) {
771 spin_unlock_irq(&nvmeq->q_lock);
772 goto out_cleanup_iod;
774 __nvme_submit_cmd(nvmeq, &cmnd);
775 nvme_process_cq(nvmeq);
776 spin_unlock_irq(&nvmeq->q_lock);
779 nvme_free_iod(dev, req);
781 nvme_cleanup_cmd(req);
785 static void nvme_pci_complete_rq(struct request *req)
787 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
789 nvme_unmap_data(iod->nvmeq->dev, req);
790 nvme_complete_rq(req);
793 /* We read the CQE phase first to check if the rest of the entry is valid */
794 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
797 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
800 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
802 u16 head = nvmeq->cq_head;
804 if (likely(nvmeq->cq_vector >= 0)) {
805 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
807 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
811 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
812 struct nvme_completion *cqe)
816 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
817 dev_warn(nvmeq->dev->ctrl.device,
818 "invalid id %d completed on queue %d\n",
819 cqe->command_id, le16_to_cpu(cqe->sq_id));
824 * AEN requests are special as they don't time out and can
825 * survive any kind of queue freeze and often don't respond to
826 * aborts. We don't even bother to allocate a struct request
827 * for them but rather special case them here.
829 if (unlikely(nvmeq->qid == 0 &&
830 cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
831 nvme_complete_async_event(&nvmeq->dev->ctrl,
832 cqe->status, &cqe->result);
837 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
838 nvme_end_request(req, cqe->status, cqe->result);
841 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
842 struct nvme_completion *cqe)
844 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
845 *cqe = nvmeq->cqes[nvmeq->cq_head];
847 if (++nvmeq->cq_head == nvmeq->q_depth) {
849 nvmeq->cq_phase = !nvmeq->cq_phase;
856 static void nvme_process_cq(struct nvme_queue *nvmeq)
858 struct nvme_completion cqe;
861 while (nvme_read_cqe(nvmeq, &cqe)) {
862 nvme_handle_cqe(nvmeq, &cqe);
867 nvme_ring_cq_doorbell(nvmeq);
870 static irqreturn_t nvme_irq(int irq, void *data)
873 struct nvme_queue *nvmeq = data;
874 spin_lock(&nvmeq->q_lock);
875 nvme_process_cq(nvmeq);
876 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
878 spin_unlock(&nvmeq->q_lock);
882 static irqreturn_t nvme_irq_check(int irq, void *data)
884 struct nvme_queue *nvmeq = data;
885 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
886 return IRQ_WAKE_THREAD;
890 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
892 struct nvme_completion cqe;
893 int found = 0, consumed = 0;
895 if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
898 spin_lock_irq(&nvmeq->q_lock);
899 while (nvme_read_cqe(nvmeq, &cqe)) {
900 nvme_handle_cqe(nvmeq, &cqe);
903 if (tag == cqe.command_id) {
910 nvme_ring_cq_doorbell(nvmeq);
911 spin_unlock_irq(&nvmeq->q_lock);
916 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
918 struct nvme_queue *nvmeq = hctx->driver_data;
920 return __nvme_poll(nvmeq, tag);
923 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
925 struct nvme_dev *dev = to_nvme_dev(ctrl);
926 struct nvme_queue *nvmeq = &dev->queues[0];
927 struct nvme_command c;
929 memset(&c, 0, sizeof(c));
930 c.common.opcode = nvme_admin_async_event;
931 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
933 spin_lock_irq(&nvmeq->q_lock);
934 __nvme_submit_cmd(nvmeq, &c);
935 spin_unlock_irq(&nvmeq->q_lock);
938 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
940 struct nvme_command c;
942 memset(&c, 0, sizeof(c));
943 c.delete_queue.opcode = opcode;
944 c.delete_queue.qid = cpu_to_le16(id);
946 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
949 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
950 struct nvme_queue *nvmeq)
952 struct nvme_command c;
953 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
956 * Note: we (ab)use the fact the the prp fields survive if no data
957 * is attached to the request.
959 memset(&c, 0, sizeof(c));
960 c.create_cq.opcode = nvme_admin_create_cq;
961 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
962 c.create_cq.cqid = cpu_to_le16(qid);
963 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
964 c.create_cq.cq_flags = cpu_to_le16(flags);
965 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
967 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
970 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
971 struct nvme_queue *nvmeq)
973 struct nvme_ctrl *ctrl = &dev->ctrl;
974 struct nvme_command c;
975 int flags = NVME_QUEUE_PHYS_CONTIG;
978 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
979 * set. Since URGENT priority is zeroes, it makes all queues
982 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
983 flags |= NVME_SQ_PRIO_MEDIUM;
986 * Note: we (ab)use the fact the the prp fields survive if no data
987 * is attached to the request.
989 memset(&c, 0, sizeof(c));
990 c.create_sq.opcode = nvme_admin_create_sq;
991 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
992 c.create_sq.sqid = cpu_to_le16(qid);
993 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
994 c.create_sq.sq_flags = cpu_to_le16(flags);
995 c.create_sq.cqid = cpu_to_le16(qid);
997 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1000 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1002 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1005 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1007 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1010 static void abort_endio(struct request *req, blk_status_t error)
1012 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1013 struct nvme_queue *nvmeq = iod->nvmeq;
1015 dev_warn(nvmeq->dev->ctrl.device,
1016 "Abort status: 0x%x", nvme_req(req)->status);
1017 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1018 blk_mq_free_request(req);
1021 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1024 /* If true, indicates loss of adapter communication, possibly by a
1025 * NVMe Subsystem reset.
1027 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1029 /* If there is a reset ongoing, we shouldn't reset again. */
1030 if (dev->ctrl.state == NVME_CTRL_RESETTING)
1033 /* We shouldn't reset unless the controller is on fatal error state
1034 * _or_ if we lost the communication with it.
1036 if (!(csts & NVME_CSTS_CFS) && !nssro)
1042 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1044 /* Read a config register to help see what died. */
1048 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1050 if (result == PCIBIOS_SUCCESSFUL)
1051 dev_warn(dev->ctrl.device,
1052 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1055 dev_warn(dev->ctrl.device,
1056 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1060 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1062 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1063 struct nvme_queue *nvmeq = iod->nvmeq;
1064 struct nvme_dev *dev = nvmeq->dev;
1065 struct request *abort_req;
1066 struct nvme_command cmd;
1067 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1069 /* If PCI error recovery process is happening, we cannot reset or
1070 * the recovery mechanism will surely fail.
1073 if (pci_channel_offline(to_pci_dev(dev->dev)))
1074 return BLK_EH_RESET_TIMER;
1077 * Reset immediately if the controller is failed
1079 if (nvme_should_reset(dev, csts)) {
1080 nvme_warn_reset(dev, csts);
1081 nvme_dev_disable(dev, false);
1082 nvme_reset_ctrl(&dev->ctrl);
1083 return BLK_EH_HANDLED;
1087 * Did we miss an interrupt?
1089 if (__nvme_poll(nvmeq, req->tag)) {
1090 dev_warn(dev->ctrl.device,
1091 "I/O %d QID %d timeout, completion polled\n",
1092 req->tag, nvmeq->qid);
1093 return BLK_EH_HANDLED;
1097 * Shutdown immediately if controller times out while starting. The
1098 * reset work will see the pci device disabled when it gets the forced
1099 * cancellation error. All outstanding requests are completed on
1100 * shutdown, so we return BLK_EH_HANDLED.
1102 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1103 dev_warn(dev->ctrl.device,
1104 "I/O %d QID %d timeout, disable controller\n",
1105 req->tag, nvmeq->qid);
1106 nvme_dev_disable(dev, false);
1107 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1108 return BLK_EH_HANDLED;
1112 * Shutdown the controller immediately and schedule a reset if the
1113 * command was already aborted once before and still hasn't been
1114 * returned to the driver, or if this is the admin queue.
1116 if (!nvmeq->qid || iod->aborted) {
1117 dev_warn(dev->ctrl.device,
1118 "I/O %d QID %d timeout, reset controller\n",
1119 req->tag, nvmeq->qid);
1120 nvme_dev_disable(dev, false);
1121 nvme_reset_ctrl(&dev->ctrl);
1124 * Mark the request as handled, since the inline shutdown
1125 * forces all outstanding requests to complete.
1127 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1128 return BLK_EH_HANDLED;
1131 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1132 atomic_inc(&dev->ctrl.abort_limit);
1133 return BLK_EH_RESET_TIMER;
1137 memset(&cmd, 0, sizeof(cmd));
1138 cmd.abort.opcode = nvme_admin_abort_cmd;
1139 cmd.abort.cid = req->tag;
1140 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1142 dev_warn(nvmeq->dev->ctrl.device,
1143 "I/O %d QID %d timeout, aborting\n",
1144 req->tag, nvmeq->qid);
1146 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1147 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1148 if (IS_ERR(abort_req)) {
1149 atomic_inc(&dev->ctrl.abort_limit);
1150 return BLK_EH_RESET_TIMER;
1153 abort_req->timeout = ADMIN_TIMEOUT;
1154 abort_req->end_io_data = NULL;
1155 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1158 * The aborted req will be completed on receiving the abort req.
1159 * We enable the timer again. If hit twice, it'll cause a device reset,
1160 * as the device then is in a faulty state.
1162 return BLK_EH_RESET_TIMER;
1165 static void nvme_free_queue(struct nvme_queue *nvmeq)
1167 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1168 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1170 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1171 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1174 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1178 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1179 dev->ctrl.queue_count--;
1180 nvme_free_queue(&dev->queues[i]);
1185 * nvme_suspend_queue - put queue into suspended state
1186 * @nvmeq - queue to suspend
1188 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1192 spin_lock_irq(&nvmeq->q_lock);
1193 if (nvmeq->cq_vector == -1) {
1194 spin_unlock_irq(&nvmeq->q_lock);
1197 vector = nvmeq->cq_vector;
1198 nvmeq->dev->online_queues--;
1199 nvmeq->cq_vector = -1;
1200 spin_unlock_irq(&nvmeq->q_lock);
1202 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1203 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1205 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1210 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1212 struct nvme_queue *nvmeq = &dev->queues[0];
1214 if (nvme_suspend_queue(nvmeq))
1218 nvme_shutdown_ctrl(&dev->ctrl);
1220 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1222 spin_lock_irq(&nvmeq->q_lock);
1223 nvme_process_cq(nvmeq);
1224 spin_unlock_irq(&nvmeq->q_lock);
1227 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1230 int q_depth = dev->q_depth;
1231 unsigned q_size_aligned = roundup(q_depth * entry_size,
1232 dev->ctrl.page_size);
1234 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1235 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1236 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1237 q_depth = div_u64(mem_per_q, entry_size);
1240 * Ensure the reduced q_depth is above some threshold where it
1241 * would be better to map queues in system memory with the
1251 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1255 /* CMB SQEs will be mapped before creation */
1256 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz))
1259 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1260 &nvmeq->sq_dma_addr, GFP_KERNEL);
1261 if (!nvmeq->sq_cmds)
1267 static int nvme_alloc_queue(struct nvme_dev *dev, int qid,
1268 int depth, int node)
1270 struct nvme_queue *nvmeq = &dev->queues[qid];
1272 if (dev->ctrl.queue_count > qid)
1275 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1276 &nvmeq->cq_dma_addr, GFP_KERNEL);
1280 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1283 nvmeq->q_dmadev = dev->dev;
1285 spin_lock_init(&nvmeq->q_lock);
1287 nvmeq->cq_phase = 1;
1288 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1289 nvmeq->q_depth = depth;
1291 nvmeq->cq_vector = -1;
1292 dev->ctrl.queue_count++;
1297 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1298 nvmeq->cq_dma_addr);
1303 static int queue_request_irq(struct nvme_queue *nvmeq)
1305 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1306 int nr = nvmeq->dev->ctrl.instance;
1308 if (use_threaded_interrupts) {
1309 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1310 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1312 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1313 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1317 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1319 struct nvme_dev *dev = nvmeq->dev;
1321 spin_lock_irq(&nvmeq->q_lock);
1324 nvmeq->cq_phase = 1;
1325 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1326 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1327 nvme_dbbuf_init(dev, nvmeq, qid);
1328 dev->online_queues++;
1329 spin_unlock_irq(&nvmeq->q_lock);
1332 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1334 struct nvme_dev *dev = nvmeq->dev;
1337 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1338 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1339 dev->ctrl.page_size);
1340 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1341 nvmeq->sq_cmds_io = dev->cmb + offset;
1344 nvmeq->cq_vector = qid - 1;
1345 result = adapter_alloc_cq(dev, qid, nvmeq);
1347 goto release_vector;
1349 result = adapter_alloc_sq(dev, qid, nvmeq);
1353 nvme_init_queue(nvmeq, qid);
1354 result = queue_request_irq(nvmeq);
1361 dev->online_queues--;
1362 adapter_delete_sq(dev, qid);
1364 adapter_delete_cq(dev, qid);
1366 nvmeq->cq_vector = -1;
1370 static const struct blk_mq_ops nvme_mq_admin_ops = {
1371 .queue_rq = nvme_queue_rq,
1372 .complete = nvme_pci_complete_rq,
1373 .init_hctx = nvme_admin_init_hctx,
1374 .exit_hctx = nvme_admin_exit_hctx,
1375 .init_request = nvme_init_request,
1376 .timeout = nvme_timeout,
1379 static const struct blk_mq_ops nvme_mq_ops = {
1380 .queue_rq = nvme_queue_rq,
1381 .complete = nvme_pci_complete_rq,
1382 .init_hctx = nvme_init_hctx,
1383 .init_request = nvme_init_request,
1384 .map_queues = nvme_pci_map_queues,
1385 .timeout = nvme_timeout,
1389 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1391 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1393 * If the controller was reset during removal, it's possible
1394 * user requests may be waiting on a stopped queue. Start the
1395 * queue to flush these to completion.
1397 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1398 blk_cleanup_queue(dev->ctrl.admin_q);
1399 blk_mq_free_tag_set(&dev->admin_tagset);
1403 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1405 if (!dev->ctrl.admin_q) {
1406 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1407 dev->admin_tagset.nr_hw_queues = 1;
1410 * Subtract one to leave an empty queue entry for 'Full Queue'
1411 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1413 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1414 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1415 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1416 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1417 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1418 dev->admin_tagset.driver_data = dev;
1420 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1422 dev->ctrl.admin_tagset = &dev->admin_tagset;
1424 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1425 if (IS_ERR(dev->ctrl.admin_q)) {
1426 blk_mq_free_tag_set(&dev->admin_tagset);
1429 if (!blk_get_queue(dev->ctrl.admin_q)) {
1430 nvme_dev_remove_admin(dev);
1431 dev->ctrl.admin_q = NULL;
1435 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1440 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1442 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1445 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1447 struct pci_dev *pdev = to_pci_dev(dev->dev);
1449 if (size <= dev->bar_mapped_size)
1451 if (size > pci_resource_len(pdev, 0))
1455 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1457 dev->bar_mapped_size = 0;
1460 dev->bar_mapped_size = size;
1461 dev->dbs = dev->bar + NVME_REG_DBS;
1466 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1470 struct nvme_queue *nvmeq;
1472 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1476 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1477 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1479 if (dev->subsystem &&
1480 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1481 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1483 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1487 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1488 dev_to_node(dev->dev));
1492 nvmeq = &dev->queues[0];
1493 aqa = nvmeq->q_depth - 1;
1496 writel(aqa, dev->bar + NVME_REG_AQA);
1497 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1498 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1500 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1504 nvmeq->cq_vector = 0;
1505 nvme_init_queue(nvmeq, 0);
1506 result = queue_request_irq(nvmeq);
1508 nvmeq->cq_vector = -1;
1515 static int nvme_create_io_queues(struct nvme_dev *dev)
1520 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1521 /* vector == qid - 1, match nvme_create_queue */
1522 if (nvme_alloc_queue(dev, i, dev->q_depth,
1523 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1529 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1530 for (i = dev->online_queues; i <= max; i++) {
1531 ret = nvme_create_queue(&dev->queues[i], i);
1537 * Ignore failing Create SQ/CQ commands, we can continue with less
1538 * than the desired aount of queues, and even a controller without
1539 * I/O queues an still be used to issue admin commands. This might
1540 * be useful to upgrade a buggy firmware for example.
1542 return ret >= 0 ? 0 : ret;
1545 static ssize_t nvme_cmb_show(struct device *dev,
1546 struct device_attribute *attr,
1549 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1551 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1552 ndev->cmbloc, ndev->cmbsz);
1554 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1556 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1558 u64 szu, size, offset;
1559 resource_size_t bar_size;
1560 struct pci_dev *pdev = to_pci_dev(dev->dev);
1564 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1565 if (!(NVME_CMB_SZ(dev->cmbsz)))
1567 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1572 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1573 size = szu * NVME_CMB_SZ(dev->cmbsz);
1574 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1575 bar = NVME_CMB_BIR(dev->cmbloc);
1576 bar_size = pci_resource_len(pdev, bar);
1578 if (offset > bar_size)
1582 * Controllers may support a CMB size larger than their BAR,
1583 * for example, due to being behind a bridge. Reduce the CMB to
1584 * the reported size of the BAR
1586 if (size > bar_size - offset)
1587 size = bar_size - offset;
1589 cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1593 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1594 dev->cmb_size = size;
1598 static inline void nvme_release_cmb(struct nvme_dev *dev)
1603 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1604 &dev_attr_cmb.attr, NULL);
1609 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1611 u64 dma_addr = dev->host_mem_descs_dma;
1612 struct nvme_command c;
1615 memset(&c, 0, sizeof(c));
1616 c.features.opcode = nvme_admin_set_features;
1617 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1618 c.features.dword11 = cpu_to_le32(bits);
1619 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1620 ilog2(dev->ctrl.page_size));
1621 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1622 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1623 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1625 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1627 dev_warn(dev->ctrl.device,
1628 "failed to set host mem (err %d, flags %#x).\n",
1634 static void nvme_free_host_mem(struct nvme_dev *dev)
1638 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1639 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1640 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1642 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1643 le64_to_cpu(desc->addr),
1644 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1647 kfree(dev->host_mem_desc_bufs);
1648 dev->host_mem_desc_bufs = NULL;
1649 dma_free_coherent(dev->dev,
1650 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1651 dev->host_mem_descs, dev->host_mem_descs_dma);
1652 dev->host_mem_descs = NULL;
1653 dev->nr_host_mem_descs = 0;
1656 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1659 struct nvme_host_mem_buf_desc *descs;
1660 u32 max_entries, len;
1661 dma_addr_t descs_dma;
1666 tmp = (preferred + chunk_size - 1);
1667 do_div(tmp, chunk_size);
1670 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1671 max_entries = dev->ctrl.hmmaxd;
1673 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1674 &descs_dma, GFP_KERNEL);
1678 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1680 goto out_free_descs;
1682 for (size = 0; size < preferred && i < max_entries; size += len) {
1683 dma_addr_t dma_addr;
1685 len = min_t(u64, chunk_size, preferred - size);
1686 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1687 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1691 descs[i].addr = cpu_to_le64(dma_addr);
1692 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1699 dev->nr_host_mem_descs = i;
1700 dev->host_mem_size = size;
1701 dev->host_mem_descs = descs;
1702 dev->host_mem_descs_dma = descs_dma;
1703 dev->host_mem_desc_bufs = bufs;
1708 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1710 dma_free_attrs(dev->dev, size, bufs[i],
1711 le64_to_cpu(descs[i].addr),
1712 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1717 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1720 dev->host_mem_descs = NULL;
1724 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1728 /* start big and work our way down */
1729 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1730 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1732 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1733 if (!min || dev->host_mem_size >= min)
1735 nvme_free_host_mem(dev);
1742 static int nvme_setup_host_mem(struct nvme_dev *dev)
1744 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1745 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1746 u64 min = (u64)dev->ctrl.hmmin * 4096;
1747 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1750 preferred = min(preferred, max);
1752 dev_warn(dev->ctrl.device,
1753 "min host memory (%lld MiB) above limit (%d MiB).\n",
1754 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1755 nvme_free_host_mem(dev);
1760 * If we already have a buffer allocated check if we can reuse it.
1762 if (dev->host_mem_descs) {
1763 if (dev->host_mem_size >= min)
1764 enable_bits |= NVME_HOST_MEM_RETURN;
1766 nvme_free_host_mem(dev);
1769 if (!dev->host_mem_descs) {
1770 if (nvme_alloc_host_mem(dev, min, preferred)) {
1771 dev_warn(dev->ctrl.device,
1772 "failed to allocate host memory buffer.\n");
1773 return 0; /* controller must work without HMB */
1776 dev_info(dev->ctrl.device,
1777 "allocated %lld MiB host memory buffer.\n",
1778 dev->host_mem_size >> ilog2(SZ_1M));
1781 ret = nvme_set_host_mem(dev, enable_bits);
1783 nvme_free_host_mem(dev);
1787 static int nvme_setup_io_queues(struct nvme_dev *dev)
1789 struct nvme_queue *adminq = &dev->queues[0];
1790 struct pci_dev *pdev = to_pci_dev(dev->dev);
1791 int result, nr_io_queues;
1794 nr_io_queues = num_possible_cpus();
1795 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1799 if (nr_io_queues == 0)
1802 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1803 result = nvme_cmb_qdepth(dev, nr_io_queues,
1804 sizeof(struct nvme_command));
1806 dev->q_depth = result;
1808 nvme_release_cmb(dev);
1812 size = db_bar_size(dev, nr_io_queues);
1813 result = nvme_remap_bar(dev, size);
1816 if (!--nr_io_queues)
1819 adminq->q_db = dev->dbs;
1821 /* Deregister the admin queue's interrupt */
1822 pci_free_irq(pdev, 0, adminq);
1825 * If we enable msix early due to not intx, disable it again before
1826 * setting up the full range we need.
1828 pci_free_irq_vectors(pdev);
1829 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1830 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1831 if (nr_io_queues <= 0)
1833 dev->max_qid = nr_io_queues;
1836 * Should investigate if there's a performance win from allocating
1837 * more queues than interrupt vectors; it might allow the submission
1838 * path to scale better, even if the receive path is limited by the
1839 * number of interrupts.
1842 result = queue_request_irq(adminq);
1844 adminq->cq_vector = -1;
1847 return nvme_create_io_queues(dev);
1850 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1852 struct nvme_queue *nvmeq = req->end_io_data;
1854 blk_mq_free_request(req);
1855 complete(&nvmeq->dev->ioq_wait);
1858 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1860 struct nvme_queue *nvmeq = req->end_io_data;
1863 unsigned long flags;
1866 * We might be called with the AQ q_lock held
1867 * and the I/O queue q_lock should always
1868 * nest inside the AQ one.
1870 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1871 SINGLE_DEPTH_NESTING);
1872 nvme_process_cq(nvmeq);
1873 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1876 nvme_del_queue_end(req, error);
1879 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1881 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1882 struct request *req;
1883 struct nvme_command cmd;
1885 memset(&cmd, 0, sizeof(cmd));
1886 cmd.delete_queue.opcode = opcode;
1887 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1889 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1891 return PTR_ERR(req);
1893 req->timeout = ADMIN_TIMEOUT;
1894 req->end_io_data = nvmeq;
1896 blk_execute_rq_nowait(q, NULL, req, false,
1897 opcode == nvme_admin_delete_cq ?
1898 nvme_del_cq_end : nvme_del_queue_end);
1902 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1905 unsigned long timeout;
1906 u8 opcode = nvme_admin_delete_sq;
1908 for (pass = 0; pass < 2; pass++) {
1909 int sent = 0, i = queues;
1911 reinit_completion(&dev->ioq_wait);
1913 timeout = ADMIN_TIMEOUT;
1914 for (; i > 0; i--, sent++)
1915 if (nvme_delete_queue(&dev->queues[i], opcode))
1919 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1925 opcode = nvme_admin_delete_cq;
1930 * Return: error value if an error occurred setting up the queues or calling
1931 * Identify Device. 0 if these succeeded, even if adding some of the
1932 * namespaces failed. At the moment, these failures are silent. TBD which
1933 * failures should be reported.
1935 static int nvme_dev_add(struct nvme_dev *dev)
1937 if (!dev->ctrl.tagset) {
1938 dev->tagset.ops = &nvme_mq_ops;
1939 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1940 dev->tagset.timeout = NVME_IO_TIMEOUT;
1941 dev->tagset.numa_node = dev_to_node(dev->dev);
1942 dev->tagset.queue_depth =
1943 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1944 dev->tagset.cmd_size = nvme_cmd_size(dev);
1945 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1946 dev->tagset.driver_data = dev;
1948 if (blk_mq_alloc_tag_set(&dev->tagset))
1950 dev->ctrl.tagset = &dev->tagset;
1952 nvme_dbbuf_set(dev);
1954 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1956 /* Free previously allocated queues that are no longer usable */
1957 nvme_free_queues(dev, dev->online_queues);
1963 static int nvme_pci_enable(struct nvme_dev *dev)
1965 int result = -ENOMEM;
1966 struct pci_dev *pdev = to_pci_dev(dev->dev);
1968 if (pci_enable_device_mem(pdev))
1971 pci_set_master(pdev);
1973 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1974 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1977 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1983 * Some devices and/or platforms don't advertise or work with INTx
1984 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1985 * adjust this later.
1987 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1991 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1993 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
1995 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
1996 dev->dbs = dev->bar + 4096;
1999 * Temporary fix for the Apple controller found in the MacBook8,1 and
2000 * some MacBook7,1 to avoid controller resets and data loss.
2002 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2004 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2005 "set queue depth=%u to work around controller resets\n",
2007 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2008 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2009 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2011 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2012 "set queue depth=%u\n", dev->q_depth);
2016 * CMBs can currently only exist on >=1.2 PCIe devices. We only
2017 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
2018 * has no name we can pass NULL as final argument to
2019 * sysfs_add_file_to_group.
2022 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
2023 dev->cmb = nvme_map_cmb(dev);
2025 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
2026 &dev_attr_cmb.attr, NULL))
2027 dev_warn(dev->ctrl.device,
2028 "failed to add sysfs attribute for CMB\n");
2032 pci_enable_pcie_error_reporting(pdev);
2033 pci_save_state(pdev);
2037 pci_disable_device(pdev);
2041 static void nvme_dev_unmap(struct nvme_dev *dev)
2045 pci_release_mem_regions(to_pci_dev(dev->dev));
2048 static void nvme_pci_disable(struct nvme_dev *dev)
2050 struct pci_dev *pdev = to_pci_dev(dev->dev);
2052 nvme_release_cmb(dev);
2053 pci_free_irq_vectors(pdev);
2055 if (pci_is_enabled(pdev)) {
2056 pci_disable_pcie_error_reporting(pdev);
2057 pci_disable_device(pdev);
2061 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2065 struct pci_dev *pdev = to_pci_dev(dev->dev);
2067 mutex_lock(&dev->shutdown_lock);
2068 if (pci_is_enabled(pdev)) {
2069 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2071 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2072 dev->ctrl.state == NVME_CTRL_RESETTING)
2073 nvme_start_freeze(&dev->ctrl);
2074 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2075 pdev->error_state != pci_channel_io_normal);
2079 * Give the controller a chance to complete all entered requests if
2080 * doing a safe shutdown.
2084 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2087 * If the controller is still alive tell it to stop using the
2088 * host memory buffer. In theory the shutdown / reset should
2089 * make sure that it doesn't access the host memoery anymore,
2090 * but I'd rather be safe than sorry..
2092 if (dev->host_mem_descs)
2093 nvme_set_host_mem(dev, 0);
2096 nvme_stop_queues(&dev->ctrl);
2098 queues = dev->online_queues - 1;
2099 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
2100 nvme_suspend_queue(&dev->queues[i]);
2103 /* A device might become IO incapable very soon during
2104 * probe, before the admin queue is configured. Thus,
2105 * queue_count can be 0 here.
2107 if (dev->ctrl.queue_count)
2108 nvme_suspend_queue(&dev->queues[0]);
2110 nvme_disable_io_queues(dev, queues);
2111 nvme_disable_admin_queue(dev, shutdown);
2113 nvme_pci_disable(dev);
2115 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2116 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2119 * The driver will not be starting up queues again if shutting down so
2120 * must flush all entered requests to their failed completion to avoid
2121 * deadlocking blk-mq hot-cpu notifier.
2124 nvme_start_queues(&dev->ctrl);
2125 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2126 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2128 mutex_unlock(&dev->shutdown_lock);
2131 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2133 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2134 PAGE_SIZE, PAGE_SIZE, 0);
2135 if (!dev->prp_page_pool)
2138 /* Optimisation for I/Os between 4k and 128k */
2139 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2141 if (!dev->prp_small_pool) {
2142 dma_pool_destroy(dev->prp_page_pool);
2148 static void nvme_release_prp_pools(struct nvme_dev *dev)
2150 dma_pool_destroy(dev->prp_page_pool);
2151 dma_pool_destroy(dev->prp_small_pool);
2154 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2156 struct nvme_dev *dev = to_nvme_dev(ctrl);
2158 nvme_dbbuf_dma_free(dev);
2159 put_device(dev->dev);
2160 if (dev->tagset.tags)
2161 blk_mq_free_tag_set(&dev->tagset);
2162 if (dev->ctrl.admin_q)
2163 blk_put_queue(dev->ctrl.admin_q);
2165 free_opal_dev(dev->ctrl.opal_dev);
2169 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2171 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2173 kref_get(&dev->ctrl.kref);
2174 nvme_dev_disable(dev, false);
2175 if (!schedule_work(&dev->remove_work))
2176 nvme_put_ctrl(&dev->ctrl);
2179 static void nvme_reset_work(struct work_struct *work)
2181 struct nvme_dev *dev =
2182 container_of(work, struct nvme_dev, ctrl.reset_work);
2183 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2184 int result = -ENODEV;
2186 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2190 * If we're called to reset a live controller first shut it down before
2193 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2194 nvme_dev_disable(dev, false);
2196 result = nvme_pci_enable(dev);
2200 result = nvme_pci_configure_admin_queue(dev);
2204 result = nvme_alloc_admin_tags(dev);
2208 result = nvme_init_identify(&dev->ctrl);
2212 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2213 if (!dev->ctrl.opal_dev)
2214 dev->ctrl.opal_dev =
2215 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2216 else if (was_suspend)
2217 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2219 free_opal_dev(dev->ctrl.opal_dev);
2220 dev->ctrl.opal_dev = NULL;
2223 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2224 result = nvme_dbbuf_dma_alloc(dev);
2227 "unable to allocate dma for dbbuf\n");
2230 if (dev->ctrl.hmpre) {
2231 result = nvme_setup_host_mem(dev);
2236 result = nvme_setup_io_queues(dev);
2241 * Keep the controller around but remove all namespaces if we don't have
2242 * any working I/O queue.
2244 if (dev->online_queues < 2) {
2245 dev_warn(dev->ctrl.device, "IO queues not created\n");
2246 nvme_kill_queues(&dev->ctrl);
2247 nvme_remove_namespaces(&dev->ctrl);
2249 nvme_start_queues(&dev->ctrl);
2250 nvme_wait_freeze(&dev->ctrl);
2252 nvme_unfreeze(&dev->ctrl);
2255 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2256 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2260 nvme_start_ctrl(&dev->ctrl);
2264 nvme_remove_dead_ctrl(dev, result);
2267 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2269 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2270 struct pci_dev *pdev = to_pci_dev(dev->dev);
2272 nvme_kill_queues(&dev->ctrl);
2273 if (pci_get_drvdata(pdev))
2274 device_release_driver(&pdev->dev);
2275 nvme_put_ctrl(&dev->ctrl);
2278 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2280 *val = readl(to_nvme_dev(ctrl)->bar + off);
2284 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2286 writel(val, to_nvme_dev(ctrl)->bar + off);
2290 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2292 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2296 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2298 .module = THIS_MODULE,
2299 .flags = NVME_F_METADATA_SUPPORTED,
2300 .reg_read32 = nvme_pci_reg_read32,
2301 .reg_write32 = nvme_pci_reg_write32,
2302 .reg_read64 = nvme_pci_reg_read64,
2303 .free_ctrl = nvme_pci_free_ctrl,
2304 .submit_async_event = nvme_pci_submit_async_event,
2307 static int nvme_dev_map(struct nvme_dev *dev)
2309 struct pci_dev *pdev = to_pci_dev(dev->dev);
2311 if (pci_request_mem_regions(pdev, "nvme"))
2314 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2319 pci_release_mem_regions(pdev);
2323 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2325 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2327 * Several Samsung devices seem to drop off the PCIe bus
2328 * randomly when APST is on and uses the deepest sleep state.
2329 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2330 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2331 * 950 PRO 256GB", but it seems to be restricted to two Dell
2334 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2335 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2336 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2337 return NVME_QUIRK_NO_DEEPEST_PS;
2338 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2340 * Samsung SSD 960 EVO drops off the PCIe bus after system
2341 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2342 * within few minutes after bootup on a Coffee Lake board -
2345 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2346 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2347 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2348 return NVME_QUIRK_NO_APST;
2354 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2356 int node, result = -ENOMEM;
2357 struct nvme_dev *dev;
2358 unsigned long quirks = id->driver_data;
2360 node = dev_to_node(&pdev->dev);
2361 if (node == NUMA_NO_NODE)
2362 set_dev_node(&pdev->dev, first_memory_node);
2364 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2368 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(struct nvme_queue),
2373 dev->dev = get_device(&pdev->dev);
2374 pci_set_drvdata(pdev, dev);
2376 result = nvme_dev_map(dev);
2380 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2381 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2382 mutex_init(&dev->shutdown_lock);
2383 init_completion(&dev->ioq_wait);
2385 result = nvme_setup_prp_pools(dev);
2389 quirks |= check_vendor_combination_bug(pdev);
2391 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2396 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2397 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2399 queue_work(nvme_wq, &dev->ctrl.reset_work);
2403 nvme_release_prp_pools(dev);
2405 nvme_dev_unmap(dev);
2407 put_device(dev->dev);
2414 static void nvme_reset_prepare(struct pci_dev *pdev)
2416 struct nvme_dev *dev = pci_get_drvdata(pdev);
2417 nvme_dev_disable(dev, false);
2420 static void nvme_reset_done(struct pci_dev *pdev)
2422 struct nvme_dev *dev = pci_get_drvdata(pdev);
2423 nvme_reset_ctrl(&dev->ctrl);
2426 static void nvme_shutdown(struct pci_dev *pdev)
2428 struct nvme_dev *dev = pci_get_drvdata(pdev);
2429 nvme_dev_disable(dev, true);
2433 * The driver's remove may be called on a device in a partially initialized
2434 * state. This function must not have any dependencies on the device state in
2437 static void nvme_remove(struct pci_dev *pdev)
2439 struct nvme_dev *dev = pci_get_drvdata(pdev);
2441 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2443 cancel_work_sync(&dev->ctrl.reset_work);
2444 pci_set_drvdata(pdev, NULL);
2446 if (!pci_device_is_present(pdev)) {
2447 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2448 nvme_dev_disable(dev, false);
2451 flush_work(&dev->ctrl.reset_work);
2452 nvme_stop_ctrl(&dev->ctrl);
2453 nvme_remove_namespaces(&dev->ctrl);
2454 nvme_dev_disable(dev, true);
2455 nvme_free_host_mem(dev);
2456 nvme_dev_remove_admin(dev);
2457 nvme_free_queues(dev, 0);
2458 nvme_uninit_ctrl(&dev->ctrl);
2459 nvme_release_prp_pools(dev);
2460 nvme_dev_unmap(dev);
2461 nvme_put_ctrl(&dev->ctrl);
2464 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2469 if (pci_vfs_assigned(pdev)) {
2470 dev_warn(&pdev->dev,
2471 "Cannot disable SR-IOV VFs while assigned\n");
2474 pci_disable_sriov(pdev);
2478 ret = pci_enable_sriov(pdev, numvfs);
2479 return ret ? ret : numvfs;
2482 #ifdef CONFIG_PM_SLEEP
2483 static int nvme_suspend(struct device *dev)
2485 struct pci_dev *pdev = to_pci_dev(dev);
2486 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2488 nvme_dev_disable(ndev, true);
2492 static int nvme_resume(struct device *dev)
2494 struct pci_dev *pdev = to_pci_dev(dev);
2495 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2497 nvme_reset_ctrl(&ndev->ctrl);
2502 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2504 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2505 pci_channel_state_t state)
2507 struct nvme_dev *dev = pci_get_drvdata(pdev);
2510 * A frozen channel requires a reset. When detected, this method will
2511 * shutdown the controller to quiesce. The controller will be restarted
2512 * after the slot reset through driver's slot_reset callback.
2515 case pci_channel_io_normal:
2516 return PCI_ERS_RESULT_CAN_RECOVER;
2517 case pci_channel_io_frozen:
2518 dev_warn(dev->ctrl.device,
2519 "frozen state error detected, reset controller\n");
2520 nvme_dev_disable(dev, false);
2521 return PCI_ERS_RESULT_NEED_RESET;
2522 case pci_channel_io_perm_failure:
2523 dev_warn(dev->ctrl.device,
2524 "failure state error detected, request disconnect\n");
2525 return PCI_ERS_RESULT_DISCONNECT;
2527 return PCI_ERS_RESULT_NEED_RESET;
2530 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2532 struct nvme_dev *dev = pci_get_drvdata(pdev);
2534 dev_info(dev->ctrl.device, "restart after slot reset\n");
2535 pci_restore_state(pdev);
2536 nvme_reset_ctrl(&dev->ctrl);
2537 return PCI_ERS_RESULT_RECOVERED;
2540 static void nvme_error_resume(struct pci_dev *pdev)
2542 struct nvme_dev *dev = pci_get_drvdata(pdev);
2544 flush_work(&dev->ctrl.reset_work);
2545 pci_cleanup_aer_uncorrect_error_status(pdev);
2548 static const struct pci_error_handlers nvme_err_handler = {
2549 .error_detected = nvme_error_detected,
2550 .slot_reset = nvme_slot_reset,
2551 .resume = nvme_error_resume,
2552 .reset_prepare = nvme_reset_prepare,
2553 .reset_done = nvme_reset_done,
2556 static const struct pci_device_id nvme_id_table[] = {
2557 { PCI_VDEVICE(INTEL, 0x0953),
2558 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2559 NVME_QUIRK_DEALLOCATE_ZEROES, },
2560 { PCI_VDEVICE(INTEL, 0x0a53),
2561 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2562 NVME_QUIRK_DEALLOCATE_ZEROES, },
2563 { PCI_VDEVICE(INTEL, 0x0a54),
2564 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2565 NVME_QUIRK_DEALLOCATE_ZEROES, },
2566 { PCI_VDEVICE(INTEL, 0x0a55),
2567 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2568 NVME_QUIRK_DEALLOCATE_ZEROES, },
2569 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2570 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2571 NVME_QUIRK_MEDIUM_PRIO_SQ },
2572 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2573 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2574 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2575 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2576 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2577 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2578 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2579 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2580 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2581 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2582 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2583 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2584 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2585 .driver_data = NVME_QUIRK_LIGHTNVM, },
2586 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2587 .driver_data = NVME_QUIRK_LIGHTNVM, },
2588 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2589 .driver_data = NVME_QUIRK_LIGHTNVM, },
2590 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2591 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
2592 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
2593 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2594 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2597 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2599 static struct pci_driver nvme_driver = {
2601 .id_table = nvme_id_table,
2602 .probe = nvme_probe,
2603 .remove = nvme_remove,
2604 .shutdown = nvme_shutdown,
2606 .pm = &nvme_dev_pm_ops,
2608 .sriov_configure = nvme_pci_sriov_configure,
2609 .err_handler = &nvme_err_handler,
2612 static int __init nvme_init(void)
2614 return pci_register_driver(&nvme_driver);
2617 static void __exit nvme_exit(void)
2619 pci_unregister_driver(&nvme_driver);
2623 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2624 MODULE_LICENSE("GPL");
2625 MODULE_VERSION("1.0");
2626 module_init(nvme_init);
2627 module_exit(nvme_exit);