drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/once.h>
  21 #include <linux/pci.h>
  22 #include <linux/suspend.h>
  23 #include <linux/t10-pi.h>
  24 #include <linux/types.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/io-64-nonatomic-hi-lo.h>
  27 #include <linux/sed-opal.h>
  28 #include <linux/pci-p2pdma.h>
  29
  30 #include "trace.h"
  31 #include "nvme.h"
  32
  33 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  34 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  35
  36 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  37
  38 /*
  39  * These can be higher, but we need to ensure that any command doesn't
  40  * require an sg allocation that needs more than a page of data.
  41  */
  42 #define NVME_MAX_KB_SZ  4096
  43 #define NVME_MAX_SEGS   127
  44
  45 static int use_threaded_interrupts;
  46 module_param(use_threaded_interrupts, int, 0);
  47
  48 static bool use_cmb_sqes = true;
  49 module_param(use_cmb_sqes, bool, 0444);
  50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  51
  52 static unsigned int max_host_mem_size_mb = 128;
  53 module_param(max_host_mem_size_mb, uint, 0444);
  54 MODULE_PARM_DESC(max_host_mem_size_mb,
  55         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  56
  57 static unsigned int sgl_threshold = SZ_32K;
  58 module_param(sgl_threshold, uint, 0644);
  59 MODULE_PARM_DESC(sgl_threshold,
  60                 "Use SGLs when average request segment size is larger or equal to "
  61                 "this size. Use 0 to disable SGLs.");
  62
  63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  64 static const struct kernel_param_ops io_queue_depth_ops = {
  65         .set = io_queue_depth_set,
  66         .get = param_get_uint,
  67 };
  68
  69 static unsigned int io_queue_depth = 1024;
  70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  72
  73 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  74 {
  75         unsigned int n;
  76         int ret;
  77
  78         ret = kstrtouint(val, 10, &n);
  79         if (ret != 0 || n > num_possible_cpus())
  80                 return -EINVAL;
  81         return param_set_uint(val, kp);
  82 }
  83
  84 static const struct kernel_param_ops io_queue_count_ops = {
  85         .set = io_queue_count_set,
  86         .get = param_get_uint,
  87 };
  88
  89 static unsigned int write_queues;
  90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  91 MODULE_PARM_DESC(write_queues,
  92         "Number of queues to use for writes. If not set, reads and writes "
  93         "will share a queue set.");
  94
  95 static unsigned int poll_queues;
  96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  98
  99 static bool noacpi;
 100 module_param(noacpi, bool, 0444);
 101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 102
 103 struct nvme_dev;
 104 struct nvme_queue;
 105
 106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 108
 109 /*
 110  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 111  */
 112 struct nvme_dev {
 113         struct nvme_queue *queues;
 114         struct blk_mq_tag_set tagset;
 115         struct blk_mq_tag_set admin_tagset;
 116         u32 __iomem *dbs;
 117         struct device *dev;
 118         struct dma_pool *prp_page_pool;
 119         struct dma_pool *prp_small_pool;
 120         unsigned online_queues;
 121         unsigned max_qid;
 122         unsigned io_queues[HCTX_MAX_TYPES];
 123         unsigned int num_vecs;
 124         u32 q_depth;
 125         int io_sqes;
 126         u32 db_stride;
 127         void __iomem *bar;
 128         unsigned long bar_mapped_size;
 129         struct work_struct remove_work;
 130         struct mutex shutdown_lock;
 131         bool subsystem;
 132         u64 cmb_size;
 133         bool cmb_use_sqes;
 134         u32 cmbsz;
 135         u32 cmbloc;
 136         struct nvme_ctrl ctrl;
 137         u32 last_ps;
 138
 139         mempool_t *iod_mempool;
 140
 141         /* shadow doorbell buffer support: */
 142         u32 *dbbuf_dbs;
 143         dma_addr_t dbbuf_dbs_dma_addr;
 144         u32 *dbbuf_eis;
 145         dma_addr_t dbbuf_eis_dma_addr;
 146
 147         /* host memory buffer support: */
 148         u64 host_mem_size;
 149         u32 nr_host_mem_descs;
 150         dma_addr_t host_mem_descs_dma;
 151         struct nvme_host_mem_buf_desc *host_mem_descs;
 152         void **host_mem_desc_bufs;
 153         unsigned int nr_allocated_queues;
 154         unsigned int nr_write_queues;
 155         unsigned int nr_poll_queues;
 156 };
 157
 158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 159 {
 160         int ret;
 161         u32 n;
 162
 163         ret = kstrtou32(val, 10, &n);
 164         if (ret != 0 || n < 2)
 165                 return -EINVAL;
 166
 167         return param_set_uint(val, kp);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         u32 *dbbuf_sq_db;
 213         u32 *dbbuf_cq_db;
 214         u32 *dbbuf_sq_ei;
 215         u32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 /*
 220  * The nvme_iod describes the data in an I/O.
 221  *
 222  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 223  * to the actual struct scatterlist.
 224  */
 225 struct nvme_iod {
 226         struct nvme_request req;
 227         struct nvme_command cmd;
 228         struct nvme_queue *nvmeq;
 229         bool use_sgl;
 230         int aborted;
 231         int npages;             /* In the PRP list. 0 means small pool in use */
 232         int nents;              /* Used in scatterlist */
 233         dma_addr_t first_dma;
 234         unsigned int dma_len;   /* length of single DMA segment mapping */
 235         dma_addr_t meta_dma;
 236         struct scatterlist *sg;
 237 };
 238
 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 240 {
 241         return dev->nr_allocated_queues * 8 * dev->db_stride;
 242 }
 243
 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 245 {
 246         unsigned int mem_size = nvme_dbbuf_size(dev);
 247
 248         if (dev->dbbuf_dbs)
 249                 return 0;
 250
 251         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 252                                             &dev->dbbuf_dbs_dma_addr,
 253                                             GFP_KERNEL);
 254         if (!dev->dbbuf_dbs)
 255                 return -ENOMEM;
 256         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 257                                             &dev->dbbuf_eis_dma_addr,
 258                                             GFP_KERNEL);
 259         if (!dev->dbbuf_eis) {
 260                 dma_free_coherent(dev->dev, mem_size,
 261                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 262                 dev->dbbuf_dbs = NULL;
 263                 return -ENOMEM;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 270 {
 271         unsigned int mem_size = nvme_dbbuf_size(dev);
 272
 273         if (dev->dbbuf_dbs) {
 274                 dma_free_coherent(dev->dev, mem_size,
 275                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 276                 dev->dbbuf_dbs = NULL;
 277         }
 278         if (dev->dbbuf_eis) {
 279                 dma_free_coherent(dev->dev, mem_size,
 280                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 281                 dev->dbbuf_eis = NULL;
 282         }
 283 }
 284
 285 static void nvme_dbbuf_init(struct nvme_dev *dev,
 286                             struct nvme_queue *nvmeq, int qid)
 287 {
 288         if (!dev->dbbuf_dbs || !qid)
 289                 return;
 290
 291         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 292         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 293         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 294         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 295 }
 296
 297 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 298 {
 299         if (!nvmeq->qid)
 300                 return;
 301
 302         nvmeq->dbbuf_sq_db = NULL;
 303         nvmeq->dbbuf_cq_db = NULL;
 304         nvmeq->dbbuf_sq_ei = NULL;
 305         nvmeq->dbbuf_cq_ei = NULL;
 306 }
 307
 308 static void nvme_dbbuf_set(struct nvme_dev *dev)
 309 {
 310         struct nvme_command c;
 311         unsigned int i;
 312
 313         if (!dev->dbbuf_dbs)
 314                 return;
 315
 316         memset(&c, 0, sizeof(c));
 317         c.dbbuf.opcode = nvme_admin_dbbuf;
 318         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 319         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 320
 321         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 322                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 323                 /* Free memory and continue on */
 324                 nvme_dbbuf_dma_free(dev);
 325
 326                 for (i = 1; i <= dev->online_queues; i++)
 327                         nvme_dbbuf_free(&dev->queues[i]);
 328         }
 329 }
 330
 331 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 332 {
 333         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 334 }
 335
 336 /* Update dbbuf and return true if an MMIO is required */
 337 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 338                                               volatile u32 *dbbuf_ei)
 339 {
 340         if (dbbuf_db) {
 341                 u16 old_value;
 342
 343                 /*
 344                  * Ensure that the queue is written before updating
 345                  * the doorbell in memory
 346                  */
 347                 wmb();
 348
 349                 old_value = *dbbuf_db;
 350                 *dbbuf_db = value;
 351
 352                 /*
 353                  * Ensure that the doorbell is updated before reading the event
 354                  * index from memory.  The controller needs to provide similar
 355                  * ordering to ensure the envent index is updated before reading
 356                  * the doorbell.
 357                  */
 358                 mb();
 359
 360                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 361                         return false;
 362         }
 363
 364         return true;
 365 }
 366
 367 /*
 368  * Will slightly overestimate the number of pages needed.  This is OK
 369  * as it only leads to a small amount of wasted memory for the lifetime of
 370  * the I/O.
 371  */
 372 static int nvme_pci_npages_prp(void)
 373 {
 374         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 375                                       NVME_CTRL_PAGE_SIZE);
 376         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 377 }
 378
 379 /*
 380  * Calculates the number of pages needed for the SGL segments. For example a 4k
 381  * page can accommodate 256 SGL descriptors.
 382  */
 383 static int nvme_pci_npages_sgl(void)
 384 {
 385         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 386                         PAGE_SIZE);
 387 }
 388
 389 static size_t nvme_pci_iod_alloc_size(void)
 390 {
 391         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 392
 393         return sizeof(__le64 *) * npages +
 394                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 395 }
 396
 397 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 398                                 unsigned int hctx_idx)
 399 {
 400         struct nvme_dev *dev = data;
 401         struct nvme_queue *nvmeq = &dev->queues[0];
 402
 403         WARN_ON(hctx_idx != 0);
 404         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 405
 406         hctx->driver_data = nvmeq;
 407         return 0;
 408 }
 409
 410 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 411                           unsigned int hctx_idx)
 412 {
 413         struct nvme_dev *dev = data;
 414         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 415
 416         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 417         hctx->driver_data = nvmeq;
 418         return 0;
 419 }
 420
 421 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 422                 unsigned int hctx_idx, unsigned int numa_node)
 423 {
 424         struct nvme_dev *dev = set->driver_data;
 425         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 426         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 427         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 428
 429         BUG_ON(!nvmeq);
 430         iod->nvmeq = nvmeq;
 431
 432         nvme_req(req)->ctrl = &dev->ctrl;
 433         return 0;
 434 }
 435
 436 static int queue_irq_offset(struct nvme_dev *dev)
 437 {
 438         /* if we have more than 1 vec, admin queue offsets us by 1 */
 439         if (dev->num_vecs > 1)
 440                 return 1;
 441
 442         return 0;
 443 }
 444
 445 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 446 {
 447         struct nvme_dev *dev = set->driver_data;
 448         int i, qoff, offset;
 449
 450         offset = queue_irq_offset(dev);
 451         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 452                 struct blk_mq_queue_map *map = &set->map[i];
 453
 454                 map->nr_queues = dev->io_queues[i];
 455                 if (!map->nr_queues) {
 456                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 457                         continue;
 458                 }
 459
 460                 /*
 461                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 462                  * affinity), so use the regular blk-mq cpu mapping
 463                  */
 464                 map->queue_offset = qoff;
 465                 if (i != HCTX_TYPE_POLL && offset)
 466                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 467                 else
 468                         blk_mq_map_queues(map);
 469                 qoff += map->nr_queues;
 470                 offset += map->nr_queues;
 471         }
 472
 473         return 0;
 474 }
 475
 476 /*
 477  * Write sq tail if we are asked to, or if the next command would wrap.
 478  */
 479 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 480 {
 481         if (!write_sq) {
 482                 u16 next_tail = nvmeq->sq_tail + 1;
 483
 484                 if (next_tail == nvmeq->q_depth)
 485                         next_tail = 0;
 486                 if (next_tail != nvmeq->last_sq_tail)
 487                         return;
 488         }
 489
 490         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 491                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 492                 writel(nvmeq->sq_tail, nvmeq->q_db);
 493         nvmeq->last_sq_tail = nvmeq->sq_tail;
 494 }
 495
 496 /**
 497  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 498  * @nvmeq: The queue to use
 499  * @cmd: The command to send
 500  * @write_sq: whether to write to the SQ doorbell
 501  */
 502 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 503                             bool write_sq)
 504 {
 505         spin_lock(&nvmeq->sq_lock);
 506         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 507                cmd, sizeof(*cmd));
 508         if (++nvmeq->sq_tail == nvmeq->q_depth)
 509                 nvmeq->sq_tail = 0;
 510         nvme_write_sq_db(nvmeq, write_sq);
 511         spin_unlock(&nvmeq->sq_lock);
 512 }
 513
 514 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 515 {
 516         struct nvme_queue *nvmeq = hctx->driver_data;
 517
 518         spin_lock(&nvmeq->sq_lock);
 519         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 520                 nvme_write_sq_db(nvmeq, true);
 521         spin_unlock(&nvmeq->sq_lock);
 522 }
 523
 524 static void **nvme_pci_iod_list(struct request *req)
 525 {
 526         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 527         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 528 }
 529
 530 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 531 {
 532         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 533         int nseg = blk_rq_nr_phys_segments(req);
 534         unsigned int avg_seg_size;
 535
 536         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 537
 538         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 539                 return false;
 540         if (!iod->nvmeq->qid)
 541                 return false;
 542         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 543                 return false;
 544         return true;
 545 }
 546
 547 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 548 {
 549         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 550         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 551         dma_addr_t dma_addr = iod->first_dma;
 552         int i;
 553
 554         for (i = 0; i < iod->npages; i++) {
 555                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 556                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 557
 558                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 559                 dma_addr = next_dma_addr;
 560         }
 561
 562 }
 563
 564 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 565 {
 566         const int last_sg = SGES_PER_PAGE - 1;
 567         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 568         dma_addr_t dma_addr = iod->first_dma;
 569         int i;
 570
 571         for (i = 0; i < iod->npages; i++) {
 572                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 573                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 574
 575                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 576                 dma_addr = next_dma_addr;
 577         }
 578
 579 }
 580
 581 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 582 {
 583         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 584
 585         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 586                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 587                                     rq_dma_dir(req));
 588         else
 589                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 590 }
 591
 592 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 593 {
 594         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 595
 596         if (iod->dma_len) {
 597                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 598                                rq_dma_dir(req));
 599                 return;
 600         }
 601
 602         WARN_ON_ONCE(!iod->nents);
 603
 604         nvme_unmap_sg(dev, req);
 605         if (iod->npages == 0)
 606                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 607                               iod->first_dma);
 608         else if (iod->use_sgl)
 609                 nvme_free_sgls(dev, req);
 610         else
 611                 nvme_free_prps(dev, req);
 612         mempool_free(iod->sg, dev->iod_mempool);
 613 }
 614
 615 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 616 {
 617         int i;
 618         struct scatterlist *sg;
 619
 620         for_each_sg(sgl, sg, nents, i) {
 621                 dma_addr_t phys = sg_phys(sg);
 622                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 623                         "dma_address:%pad dma_length:%d\n",
 624                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 625                         sg_dma_len(sg));
 626         }
 627 }
 628
 629 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 630                 struct request *req, struct nvme_rw_command *cmnd)
 631 {
 632         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 633         struct dma_pool *pool;
 634         int length = blk_rq_payload_bytes(req);
 635         struct scatterlist *sg = iod->sg;
 636         int dma_len = sg_dma_len(sg);
 637         u64 dma_addr = sg_dma_address(sg);
 638         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 639         __le64 *prp_list;
 640         void **list = nvme_pci_iod_list(req);
 641         dma_addr_t prp_dma;
 642         int nprps, i;
 643
 644         length -= (NVME_CTRL_PAGE_SIZE - offset);
 645         if (length <= 0) {
 646                 iod->first_dma = 0;
 647                 goto done;
 648         }
 649
 650         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 651         if (dma_len) {
 652                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 653         } else {
 654                 sg = sg_next(sg);
 655                 dma_addr = sg_dma_address(sg);
 656                 dma_len = sg_dma_len(sg);
 657         }
 658
 659         if (length <= NVME_CTRL_PAGE_SIZE) {
 660                 iod->first_dma = dma_addr;
 661                 goto done;
 662         }
 663
 664         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 665         if (nprps <= (256 / 8)) {
 666                 pool = dev->prp_small_pool;
 667                 iod->npages = 0;
 668         } else {
 669                 pool = dev->prp_page_pool;
 670                 iod->npages = 1;
 671         }
 672
 673         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 674         if (!prp_list) {
 675                 iod->first_dma = dma_addr;
 676                 iod->npages = -1;
 677                 return BLK_STS_RESOURCE;
 678         }
 679         list[0] = prp_list;
 680         iod->first_dma = prp_dma;
 681         i = 0;
 682         for (;;) {
 683                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 684                         __le64 *old_prp_list = prp_list;
 685                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 686                         if (!prp_list)
 687                                 goto free_prps;
 688                         list[iod->npages++] = prp_list;
 689                         prp_list[0] = old_prp_list[i - 1];
 690                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 691                         i = 1;
 692                 }
 693                 prp_list[i++] = cpu_to_le64(dma_addr);
 694                 dma_len -= NVME_CTRL_PAGE_SIZE;
 695                 dma_addr += NVME_CTRL_PAGE_SIZE;
 696                 length -= NVME_CTRL_PAGE_SIZE;
 697                 if (length <= 0)
 698                         break;
 699                 if (dma_len > 0)
 700                         continue;
 701                 if (unlikely(dma_len < 0))
 702                         goto bad_sgl;
 703                 sg = sg_next(sg);
 704                 dma_addr = sg_dma_address(sg);
 705                 dma_len = sg_dma_len(sg);
 706         }
 707 done:
 708         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 709         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 710         return BLK_STS_OK;
 711 free_prps:
 712         nvme_free_prps(dev, req);
 713         return BLK_STS_RESOURCE;
 714 bad_sgl:
 715         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 716                         "Invalid SGL for payload:%d nents:%d\n",
 717                         blk_rq_payload_bytes(req), iod->nents);
 718         return BLK_STS_IOERR;
 719 }
 720
 721 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 722                 struct scatterlist *sg)
 723 {
 724         sge->addr = cpu_to_le64(sg_dma_address(sg));
 725         sge->length = cpu_to_le32(sg_dma_len(sg));
 726         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 727 }
 728
 729 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 730                 dma_addr_t dma_addr, int entries)
 731 {
 732         sge->addr = cpu_to_le64(dma_addr);
 733         if (entries < SGES_PER_PAGE) {
 734                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 735                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 736         } else {
 737                 sge->length = cpu_to_le32(PAGE_SIZE);
 738                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 739         }
 740 }
 741
 742 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 743                 struct request *req, struct nvme_rw_command *cmd, int entries)
 744 {
 745         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 746         struct dma_pool *pool;
 747         struct nvme_sgl_desc *sg_list;
 748         struct scatterlist *sg = iod->sg;
 749         dma_addr_t sgl_dma;
 750         int i = 0;
 751
 752         /* setting the transfer type as SGL */
 753         cmd->flags = NVME_CMD_SGL_METABUF;
 754
 755         if (entries == 1) {
 756                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 757                 return BLK_STS_OK;
 758         }
 759
 760         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 761                 pool = dev->prp_small_pool;
 762                 iod->npages = 0;
 763         } else {
 764                 pool = dev->prp_page_pool;
 765                 iod->npages = 1;
 766         }
 767
 768         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 769         if (!sg_list) {
 770                 iod->npages = -1;
 771                 return BLK_STS_RESOURCE;
 772         }
 773
 774         nvme_pci_iod_list(req)[0] = sg_list;
 775         iod->first_dma = sgl_dma;
 776
 777         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 778
 779         do {
 780                 if (i == SGES_PER_PAGE) {
 781                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 782                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 783
 784                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 785                         if (!sg_list)
 786                                 goto free_sgls;
 787
 788                         i = 0;
 789                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 790                         sg_list[i++] = *link;
 791                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 792                 }
 793
 794                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 795                 sg = sg_next(sg);
 796         } while (--entries > 0);
 797
 798         return BLK_STS_OK;
 799 free_sgls:
 800         nvme_free_sgls(dev, req);
 801         return BLK_STS_RESOURCE;
 802 }
 803
 804 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 805                 struct request *req, struct nvme_rw_command *cmnd,
 806                 struct bio_vec *bv)
 807 {
 808         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 809         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 810         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 811
 812         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 813         if (dma_mapping_error(dev->dev, iod->first_dma))
 814                 return BLK_STS_RESOURCE;
 815         iod->dma_len = bv->bv_len;
 816
 817         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 818         if (bv->bv_len > first_prp_len)
 819                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 820         return BLK_STS_OK;
 821 }
 822
 823 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 824                 struct request *req, struct nvme_rw_command *cmnd,
 825                 struct bio_vec *bv)
 826 {
 827         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 828
 829         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 830         if (dma_mapping_error(dev->dev, iod->first_dma))
 831                 return BLK_STS_RESOURCE;
 832         iod->dma_len = bv->bv_len;
 833
 834         cmnd->flags = NVME_CMD_SGL_METABUF;
 835         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 836         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 837         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 838         return BLK_STS_OK;
 839 }
 840
 841 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 842                 struct nvme_command *cmnd)
 843 {
 844         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 845         blk_status_t ret = BLK_STS_RESOURCE;
 846         int nr_mapped;
 847
 848         if (blk_rq_nr_phys_segments(req) == 1) {
 849                 struct bio_vec bv = req_bvec(req);
 850
 851                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 852                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 853                                 return nvme_setup_prp_simple(dev, req,
 854                                                              &cmnd->rw, &bv);
 855
 856                         if (iod->nvmeq->qid && sgl_threshold &&
 857                             dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
 858                                 return nvme_setup_sgl_simple(dev, req,
 859                                                              &cmnd->rw, &bv);
 860                 }
 861         }
 862
 863         iod->dma_len = 0;
 864         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 865         if (!iod->sg)
 866                 return BLK_STS_RESOURCE;
 867         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 868         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 869         if (!iod->nents)
 870                 goto out_free_sg;
 871
 872         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 873                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 874                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 875         else
 876                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 877                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 878         if (!nr_mapped)
 879                 goto out_free_sg;
 880
 881         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 882         if (iod->use_sgl)
 883                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 884         else
 885                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 886         if (ret != BLK_STS_OK)
 887                 goto out_unmap_sg;
 888         return BLK_STS_OK;
 889
 890 out_unmap_sg:
 891         nvme_unmap_sg(dev, req);
 892 out_free_sg:
 893         mempool_free(iod->sg, dev->iod_mempool);
 894         return ret;
 895 }
 896
 897 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 898                 struct nvme_command *cmnd)
 899 {
 900         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 901
 902         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 903                         rq_dma_dir(req), 0);
 904         if (dma_mapping_error(dev->dev, iod->meta_dma))
 905                 return BLK_STS_IOERR;
 906         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 907         return BLK_STS_OK;
 908 }
 909
 910 /*
 911  * NOTE: ns is NULL when called on the admin queue.
 912  */
 913 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 914                          const struct blk_mq_queue_data *bd)
 915 {
 916         struct nvme_ns *ns = hctx->queue->queuedata;
 917         struct nvme_queue *nvmeq = hctx->driver_data;
 918         struct nvme_dev *dev = nvmeq->dev;
 919         struct request *req = bd->rq;
 920         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 921         struct nvme_command *cmnd = &iod->cmd;
 922         blk_status_t ret;
 923
 924         iod->aborted = 0;
 925         iod->npages = -1;
 926         iod->nents = 0;
 927
 928         /*
 929          * We should not need to do this, but we're still using this to
 930          * ensure we can drain requests on a dying queue.
 931          */
 932         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 933                 return BLK_STS_IOERR;
 934
 935         ret = nvme_setup_cmd(ns, req, cmnd);
 936         if (ret)
 937                 return ret;
 938
 939         if (blk_rq_nr_phys_segments(req)) {
 940                 ret = nvme_map_data(dev, req, cmnd);
 941                 if (ret)
 942                         goto out_free_cmd;
 943         }
 944
 945         if (blk_integrity_rq(req)) {
 946                 ret = nvme_map_metadata(dev, req, cmnd);
 947                 if (ret)
 948                         goto out_unmap_data;
 949         }
 950
 951         blk_mq_start_request(req);
 952         nvme_submit_cmd(nvmeq, cmnd, bd->last);
 953         return BLK_STS_OK;
 954 out_unmap_data:
 955         nvme_unmap_data(dev, req);
 956 out_free_cmd:
 957         nvme_cleanup_cmd(req);
 958         return ret;
 959 }
 960
 961 static void nvme_pci_complete_rq(struct request *req)
 962 {
 963         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 964         struct nvme_dev *dev = iod->nvmeq->dev;
 965
 966         if (blk_integrity_rq(req))
 967                 dma_unmap_page(dev->dev, iod->meta_dma,
 968                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 969         if (blk_rq_nr_phys_segments(req))
 970                 nvme_unmap_data(dev, req);
 971         nvme_complete_rq(req);
 972 }
 973
 974 /* We read the CQE phase first to check if the rest of the entry is valid */
 975 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 976 {
 977         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 978
 979         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 980 }
 981
 982 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 983 {
 984         u16 head = nvmeq->cq_head;
 985
 986         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 987                                               nvmeq->dbbuf_cq_ei))
 988                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 989 }
 990
 991 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 992 {
 993         if (!nvmeq->qid)
 994                 return nvmeq->dev->admin_tagset.tags[0];
 995         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
 996 }
 997
 998 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 999 {
1000         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1001         __u16 command_id = READ_ONCE(cqe->command_id);
1002         struct request *req;
1003
1004         /*
1005          * AEN requests are special as they don't time out and can
1006          * survive any kind of queue freeze and often don't respond to
1007          * aborts.  We don't even bother to allocate a struct request
1008          * for them but rather special case them here.
1009          */
1010         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1011                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1012                                 cqe->status, &cqe->result);
1013                 return;
1014         }
1015
1016         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1017         if (unlikely(!req)) {
1018                 dev_warn(nvmeq->dev->ctrl.device,
1019                         "invalid id %d completed on queue %d\n",
1020                         command_id, le16_to_cpu(cqe->sq_id));
1021                 return;
1022         }
1023
1024         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1025         if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1026                 nvme_pci_complete_rq(req);
1027 }
1028
1029 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1030 {
1031         u32 tmp = nvmeq->cq_head + 1;
1032
1033         if (tmp == nvmeq->q_depth) {
1034                 nvmeq->cq_head = 0;
1035                 nvmeq->cq_phase ^= 1;
1036         } else {
1037                 nvmeq->cq_head = tmp;
1038         }
1039 }
1040
1041 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1042 {
1043         int found = 0;
1044
1045         while (nvme_cqe_pending(nvmeq)) {
1046                 found++;
1047                 /*
1048                  * load-load control dependency between phase and the rest of
1049                  * the cqe requires a full read memory barrier
1050                  */
1051                 dma_rmb();
1052                 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1053                 nvme_update_cq_head(nvmeq);
1054         }
1055
1056         if (found)
1057                 nvme_ring_cq_doorbell(nvmeq);
1058         return found;
1059 }
1060
1061 static irqreturn_t nvme_irq(int irq, void *data)
1062 {
1063         struct nvme_queue *nvmeq = data;
1064         irqreturn_t ret = IRQ_NONE;
1065
1066         /*
1067          * The rmb/wmb pair ensures we see all updates from a previous run of
1068          * the irq handler, even if that was on another CPU.
1069          */
1070         rmb();
1071         if (nvme_process_cq(nvmeq))
1072                 ret = IRQ_HANDLED;
1073         wmb();
1074
1075         return ret;
1076 }
1077
1078 static irqreturn_t nvme_irq_check(int irq, void *data)
1079 {
1080         struct nvme_queue *nvmeq = data;
1081
1082         if (nvme_cqe_pending(nvmeq))
1083                 return IRQ_WAKE_THREAD;
1084         return IRQ_NONE;
1085 }
1086
1087 /*
1088  * Poll for completions for any interrupt driven queue
1089  * Can be called from any context.
1090  */
1091 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1092 {
1093         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1094
1095         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1096
1097         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1098         nvme_process_cq(nvmeq);
1099         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1100 }
1101
1102 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1103 {
1104         struct nvme_queue *nvmeq = hctx->driver_data;
1105         bool found;
1106
1107         if (!nvme_cqe_pending(nvmeq))
1108                 return 0;
1109
1110         spin_lock(&nvmeq->cq_poll_lock);
1111         found = nvme_process_cq(nvmeq);
1112         spin_unlock(&nvmeq->cq_poll_lock);
1113
1114         return found;
1115 }
1116
1117 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1118 {
1119         struct nvme_dev *dev = to_nvme_dev(ctrl);
1120         struct nvme_queue *nvmeq = &dev->queues[0];
1121         struct nvme_command c;
1122
1123         memset(&c, 0, sizeof(c));
1124         c.common.opcode = nvme_admin_async_event;
1125         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1126         nvme_submit_cmd(nvmeq, &c, true);
1127 }
1128
1129 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1130 {
1131         struct nvme_command c;
1132
1133         memset(&c, 0, sizeof(c));
1134         c.delete_queue.opcode = opcode;
1135         c.delete_queue.qid = cpu_to_le16(id);
1136
1137         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1138 }
1139
1140 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1141                 struct nvme_queue *nvmeq, s16 vector)
1142 {
1143         struct nvme_command c;
1144         int flags = NVME_QUEUE_PHYS_CONTIG;
1145
1146         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1147                 flags |= NVME_CQ_IRQ_ENABLED;
1148
1149         /*
1150          * Note: we (ab)use the fact that the prp fields survive if no data
1151          * is attached to the request.
1152          */
1153         memset(&c, 0, sizeof(c));
1154         c.create_cq.opcode = nvme_admin_create_cq;
1155         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1156         c.create_cq.cqid = cpu_to_le16(qid);
1157         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1158         c.create_cq.cq_flags = cpu_to_le16(flags);
1159         c.create_cq.irq_vector = cpu_to_le16(vector);
1160
1161         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1162 }
1163
1164 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1165                                                 struct nvme_queue *nvmeq)
1166 {
1167         struct nvme_ctrl *ctrl = &dev->ctrl;
1168         struct nvme_command c;
1169         int flags = NVME_QUEUE_PHYS_CONTIG;
1170
1171         /*
1172          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1173          * set. Since URGENT priority is zeroes, it makes all queues
1174          * URGENT.
1175          */
1176         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1177                 flags |= NVME_SQ_PRIO_MEDIUM;
1178
1179         /*
1180          * Note: we (ab)use the fact that the prp fields survive if no data
1181          * is attached to the request.
1182          */
1183         memset(&c, 0, sizeof(c));
1184         c.create_sq.opcode = nvme_admin_create_sq;
1185         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1186         c.create_sq.sqid = cpu_to_le16(qid);
1187         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1188         c.create_sq.sq_flags = cpu_to_le16(flags);
1189         c.create_sq.cqid = cpu_to_le16(qid);
1190
1191         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1192 }
1193
1194 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1195 {
1196         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1197 }
1198
1199 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1200 {
1201         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1202 }
1203
1204 static void abort_endio(struct request *req, blk_status_t error)
1205 {
1206         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1207         struct nvme_queue *nvmeq = iod->nvmeq;
1208
1209         dev_warn(nvmeq->dev->ctrl.device,
1210                  "Abort status: 0x%x", nvme_req(req)->status);
1211         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1212         blk_mq_free_request(req);
1213 }
1214
1215 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1216 {
1217         /* If true, indicates loss of adapter communication, possibly by a
1218          * NVMe Subsystem reset.
1219          */
1220         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1221
1222         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1223         switch (dev->ctrl.state) {
1224         case NVME_CTRL_RESETTING:
1225         case NVME_CTRL_CONNECTING:
1226                 return false;
1227         default:
1228                 break;
1229         }
1230
1231         /* We shouldn't reset unless the controller is on fatal error state
1232          * _or_ if we lost the communication with it.
1233          */
1234         if (!(csts & NVME_CSTS_CFS) && !nssro)
1235                 return false;
1236
1237         return true;
1238 }
1239
1240 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1241 {
1242         /* Read a config register to help see what died. */
1243         u16 pci_status;
1244         int result;
1245
1246         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1247                                       &pci_status);
1248         if (result == PCIBIOS_SUCCESSFUL)
1249                 dev_warn(dev->ctrl.device,
1250                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1251                          csts, pci_status);
1252         else
1253                 dev_warn(dev->ctrl.device,
1254                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1255                          csts, result);
1256 }
1257
1258 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1259 {
1260         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1261         struct nvme_queue *nvmeq = iod->nvmeq;
1262         struct nvme_dev *dev = nvmeq->dev;
1263         struct request *abort_req;
1264         struct nvme_command cmd;
1265         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1266
1267         /* If PCI error recovery process is happening, we cannot reset or
1268          * the recovery mechanism will surely fail.
1269          */
1270         mb();
1271         if (pci_channel_offline(to_pci_dev(dev->dev)))
1272                 return BLK_EH_RESET_TIMER;
1273
1274         /*
1275          * Reset immediately if the controller is failed
1276          */
1277         if (nvme_should_reset(dev, csts)) {
1278                 nvme_warn_reset(dev, csts);
1279                 nvme_dev_disable(dev, false);
1280                 nvme_reset_ctrl(&dev->ctrl);
1281                 return BLK_EH_DONE;
1282         }
1283
1284         /*
1285          * Did we miss an interrupt?
1286          */
1287         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1288                 nvme_poll(req->mq_hctx);
1289         else
1290                 nvme_poll_irqdisable(nvmeq);
1291
1292         if (blk_mq_request_completed(req)) {
1293                 dev_warn(dev->ctrl.device,
1294                          "I/O %d QID %d timeout, completion polled\n",
1295                          req->tag, nvmeq->qid);
1296                 return BLK_EH_DONE;
1297         }
1298
1299         /*
1300          * Shutdown immediately if controller times out while starting. The
1301          * reset work will see the pci device disabled when it gets the forced
1302          * cancellation error. All outstanding requests are completed on
1303          * shutdown, so we return BLK_EH_DONE.
1304          */
1305         switch (dev->ctrl.state) {
1306         case NVME_CTRL_CONNECTING:
1307                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1308                 fallthrough;
1309         case NVME_CTRL_DELETING:
1310                 dev_warn_ratelimited(dev->ctrl.device,
1311                          "I/O %d QID %d timeout, disable controller\n",
1312                          req->tag, nvmeq->qid);
1313                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1314                 nvme_dev_disable(dev, true);
1315                 return BLK_EH_DONE;
1316         case NVME_CTRL_RESETTING:
1317                 return BLK_EH_RESET_TIMER;
1318         default:
1319                 break;
1320         }
1321
1322         /*
1323          * Shutdown the controller immediately and schedule a reset if the
1324          * command was already aborted once before and still hasn't been
1325          * returned to the driver, or if this is the admin queue.
1326          */
1327         if (!nvmeq->qid || iod->aborted) {
1328                 dev_warn(dev->ctrl.device,
1329                          "I/O %d QID %d timeout, reset controller\n",
1330                          req->tag, nvmeq->qid);
1331                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1332                 nvme_dev_disable(dev, false);
1333                 nvme_reset_ctrl(&dev->ctrl);
1334
1335                 return BLK_EH_DONE;
1336         }
1337
1338         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1339                 atomic_inc(&dev->ctrl.abort_limit);
1340                 return BLK_EH_RESET_TIMER;
1341         }
1342         iod->aborted = 1;
1343
1344         memset(&cmd, 0, sizeof(cmd));
1345         cmd.abort.opcode = nvme_admin_abort_cmd;
1346         cmd.abort.cid = nvme_cid(req);
1347         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1348
1349         dev_warn(nvmeq->dev->ctrl.device,
1350                 "I/O %d QID %d timeout, aborting\n",
1351                  req->tag, nvmeq->qid);
1352
1353         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1354                         BLK_MQ_REQ_NOWAIT);
1355         if (IS_ERR(abort_req)) {
1356                 atomic_inc(&dev->ctrl.abort_limit);
1357                 return BLK_EH_RESET_TIMER;
1358         }
1359
1360         abort_req->end_io_data = NULL;
1361         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1362
1363         /*
1364          * The aborted req will be completed on receiving the abort req.
1365          * We enable the timer again. If hit twice, it'll cause a device reset,
1366          * as the device then is in a faulty state.
1367          */
1368         return BLK_EH_RESET_TIMER;
1369 }
1370
1371 static void nvme_free_queue(struct nvme_queue *nvmeq)
1372 {
1373         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1374                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1375         if (!nvmeq->sq_cmds)
1376                 return;
1377
1378         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1379                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1380                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1381         } else {
1382                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1383                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1384         }
1385 }
1386
1387 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1388 {
1389         int i;
1390
1391         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1392                 dev->ctrl.queue_count--;
1393                 nvme_free_queue(&dev->queues[i]);
1394         }
1395 }
1396
1397 /**
1398  * nvme_suspend_queue - put queue into suspended state
1399  * @nvmeq: queue to suspend
1400  */
1401 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1402 {
1403         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1404                 return 1;
1405
1406         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1407         mb();
1408
1409         nvmeq->dev->online_queues--;
1410         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1411                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1412         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1413                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1414         return 0;
1415 }
1416
1417 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1418 {
1419         int i;
1420
1421         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1422                 nvme_suspend_queue(&dev->queues[i]);
1423 }
1424
1425 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1426 {
1427         struct nvme_queue *nvmeq = &dev->queues[0];
1428
1429         if (shutdown)
1430                 nvme_shutdown_ctrl(&dev->ctrl);
1431         else
1432                 nvme_disable_ctrl(&dev->ctrl);
1433
1434         nvme_poll_irqdisable(nvmeq);
1435 }
1436
1437 /*
1438  * Called only on a device that has been disabled and after all other threads
1439  * that can check this device's completion queues have synced, except
1440  * nvme_poll(). This is the last chance for the driver to see a natural
1441  * completion before nvme_cancel_request() terminates all incomplete requests.
1442  */
1443 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1444 {
1445         int i;
1446
1447         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1448                 spin_lock(&dev->queues[i].cq_poll_lock);
1449                 nvme_process_cq(&dev->queues[i]);
1450                 spin_unlock(&dev->queues[i].cq_poll_lock);
1451         }
1452 }
1453
1454 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1455                                 int entry_size)
1456 {
1457         int q_depth = dev->q_depth;
1458         unsigned q_size_aligned = roundup(q_depth * entry_size,
1459                                           NVME_CTRL_PAGE_SIZE);
1460
1461         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1462                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1463
1464                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1465                 q_depth = div_u64(mem_per_q, entry_size);
1466
1467                 /*
1468                  * Ensure the reduced q_depth is above some threshold where it
1469                  * would be better to map queues in system memory with the
1470                  * original depth
1471                  */
1472                 if (q_depth < 64)
1473                         return -ENOMEM;
1474         }
1475
1476         return q_depth;
1477 }
1478
1479 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1480                                 int qid)
1481 {
1482         struct pci_dev *pdev = to_pci_dev(dev->dev);
1483
1484         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1485                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1486                 if (nvmeq->sq_cmds) {
1487                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1488                                                         nvmeq->sq_cmds);
1489                         if (nvmeq->sq_dma_addr) {
1490                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1491                                 return 0;
1492                         }
1493
1494                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1495                 }
1496         }
1497
1498         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1499                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1500         if (!nvmeq->sq_cmds)
1501                 return -ENOMEM;
1502         return 0;
1503 }
1504
1505 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1506 {
1507         struct nvme_queue *nvmeq = &dev->queues[qid];
1508
1509         if (dev->ctrl.queue_count > qid)
1510                 return 0;
1511
1512         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1513         nvmeq->q_depth = depth;
1514         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1515                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1516         if (!nvmeq->cqes)
1517                 goto free_nvmeq;
1518
1519         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1520                 goto free_cqdma;
1521
1522         nvmeq->dev = dev;
1523         spin_lock_init(&nvmeq->sq_lock);
1524         spin_lock_init(&nvmeq->cq_poll_lock);
1525         nvmeq->cq_head = 0;
1526         nvmeq->cq_phase = 1;
1527         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1528         nvmeq->qid = qid;
1529         dev->ctrl.queue_count++;
1530
1531         return 0;
1532
1533  free_cqdma:
1534         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1535                           nvmeq->cq_dma_addr);
1536  free_nvmeq:
1537         return -ENOMEM;
1538 }
1539
1540 static int queue_request_irq(struct nvme_queue *nvmeq)
1541 {
1542         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1543         int nr = nvmeq->dev->ctrl.instance;
1544
1545         if (use_threaded_interrupts) {
1546                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1547                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1548         } else {
1549                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1550                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1551         }
1552 }
1553
1554 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1555 {
1556         struct nvme_dev *dev = nvmeq->dev;
1557
1558         nvmeq->sq_tail = 0;
1559         nvmeq->last_sq_tail = 0;
1560         nvmeq->cq_head = 0;
1561         nvmeq->cq_phase = 1;
1562         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1563         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1564         nvme_dbbuf_init(dev, nvmeq, qid);
1565         dev->online_queues++;
1566         wmb(); /* ensure the first interrupt sees the initialization */
1567 }
1568
1569 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1570 {
1571         struct nvme_dev *dev = nvmeq->dev;
1572         int result;
1573         u16 vector = 0;
1574
1575         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1576
1577         /*
1578          * A queue's vector matches the queue identifier unless the controller
1579          * has only one vector available.
1580          */
1581         if (!polled)
1582                 vector = dev->num_vecs == 1 ? 0 : qid;
1583         else
1584                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1585
1586         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1587         if (result)
1588                 return result;
1589
1590         result = adapter_alloc_sq(dev, qid, nvmeq);
1591         if (result < 0)
1592                 return result;
1593         if (result)
1594                 goto release_cq;
1595
1596         nvmeq->cq_vector = vector;
1597         nvme_init_queue(nvmeq, qid);
1598
1599         if (!polled) {
1600                 result = queue_request_irq(nvmeq);
1601                 if (result < 0)
1602                         goto release_sq;
1603         }
1604
1605         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1606         return result;
1607
1608 release_sq:
1609         dev->online_queues--;
1610         adapter_delete_sq(dev, qid);
1611 release_cq:
1612         adapter_delete_cq(dev, qid);
1613         return result;
1614 }
1615
1616 static const struct blk_mq_ops nvme_mq_admin_ops = {
1617         .queue_rq       = nvme_queue_rq,
1618         .complete       = nvme_pci_complete_rq,
1619         .init_hctx      = nvme_admin_init_hctx,
1620         .init_request   = nvme_init_request,
1621         .timeout        = nvme_timeout,
1622 };
1623
1624 static const struct blk_mq_ops nvme_mq_ops = {
1625         .queue_rq       = nvme_queue_rq,
1626         .complete       = nvme_pci_complete_rq,
1627         .commit_rqs     = nvme_commit_rqs,
1628         .init_hctx      = nvme_init_hctx,
1629         .init_request   = nvme_init_request,
1630         .map_queues     = nvme_pci_map_queues,
1631         .timeout        = nvme_timeout,
1632         .poll           = nvme_poll,
1633 };
1634
1635 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1636 {
1637         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1638                 /*
1639                  * If the controller was reset during removal, it's possible
1640                  * user requests may be waiting on a stopped queue. Start the
1641                  * queue to flush these to completion.
1642                  */
1643                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1644                 blk_cleanup_queue(dev->ctrl.admin_q);
1645                 blk_mq_free_tag_set(&dev->admin_tagset);
1646         }
1647 }
1648
1649 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1650 {
1651         if (!dev->ctrl.admin_q) {
1652                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1653                 dev->admin_tagset.nr_hw_queues = 1;
1654
1655                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1656                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1657                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1658                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1659                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1660                 dev->admin_tagset.driver_data = dev;
1661
1662                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1663                         return -ENOMEM;
1664                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1665
1666                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1667                 if (IS_ERR(dev->ctrl.admin_q)) {
1668                         blk_mq_free_tag_set(&dev->admin_tagset);
1669                         dev->ctrl.admin_q = NULL;
1670                         return -ENOMEM;
1671                 }
1672                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1673                         nvme_dev_remove_admin(dev);
1674                         dev->ctrl.admin_q = NULL;
1675                         return -ENODEV;
1676                 }
1677         } else
1678                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1679
1680         return 0;
1681 }
1682
1683 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1684 {
1685         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1686 }
1687
1688 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1689 {
1690         struct pci_dev *pdev = to_pci_dev(dev->dev);
1691
1692         if (size <= dev->bar_mapped_size)
1693                 return 0;
1694         if (size > pci_resource_len(pdev, 0))
1695                 return -ENOMEM;
1696         if (dev->bar)
1697                 iounmap(dev->bar);
1698         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1699         if (!dev->bar) {
1700                 dev->bar_mapped_size = 0;
1701                 return -ENOMEM;
1702         }
1703         dev->bar_mapped_size = size;
1704         dev->dbs = dev->bar + NVME_REG_DBS;
1705
1706         return 0;
1707 }
1708
1709 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1710 {
1711         int result;
1712         u32 aqa;
1713         struct nvme_queue *nvmeq;
1714
1715         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1716         if (result < 0)
1717                 return result;
1718
1719         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1720                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1721
1722         if (dev->subsystem &&
1723             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1724                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1725
1726         result = nvme_disable_ctrl(&dev->ctrl);
1727         if (result < 0)
1728                 return result;
1729
1730         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1731         if (result)
1732                 return result;
1733
1734         dev->ctrl.numa_node = dev_to_node(dev->dev);
1735
1736         nvmeq = &dev->queues[0];
1737         aqa = nvmeq->q_depth - 1;
1738         aqa |= aqa << 16;
1739
1740         writel(aqa, dev->bar + NVME_REG_AQA);
1741         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1742         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1743
1744         result = nvme_enable_ctrl(&dev->ctrl);
1745         if (result)
1746                 return result;
1747
1748         nvmeq->cq_vector = 0;
1749         nvme_init_queue(nvmeq, 0);
1750         result = queue_request_irq(nvmeq);
1751         if (result) {
1752                 dev->online_queues--;
1753                 return result;
1754         }
1755
1756         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1757         return result;
1758 }
1759
1760 static int nvme_create_io_queues(struct nvme_dev *dev)
1761 {
1762         unsigned i, max, rw_queues;
1763         int ret = 0;
1764
1765         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1766                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1767                         ret = -ENOMEM;
1768                         break;
1769                 }
1770         }
1771
1772         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1773         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1774                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1775                                 dev->io_queues[HCTX_TYPE_READ];
1776         } else {
1777                 rw_queues = max;
1778         }
1779
1780         for (i = dev->online_queues; i <= max; i++) {
1781                 bool polled = i > rw_queues;
1782
1783                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1784                 if (ret)
1785                         break;
1786         }
1787
1788         /*
1789          * Ignore failing Create SQ/CQ commands, we can continue with less
1790          * than the desired amount of queues, and even a controller without
1791          * I/O queues can still be used to issue admin commands.  This might
1792          * be useful to upgrade a buggy firmware for example.
1793          */
1794         return ret >= 0 ? 0 : ret;
1795 }
1796
1797 static ssize_t nvme_cmb_show(struct device *dev,
1798                              struct device_attribute *attr,
1799                              char *buf)
1800 {
1801         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1802
1803         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1804                        ndev->cmbloc, ndev->cmbsz);
1805 }
1806 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1807
1808 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1809 {
1810         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1811
1812         return 1ULL << (12 + 4 * szu);
1813 }
1814
1815 static u32 nvme_cmb_size(struct nvme_dev *dev)
1816 {
1817         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1818 }
1819
1820 static void nvme_map_cmb(struct nvme_dev *dev)
1821 {
1822         u64 size, offset;
1823         resource_size_t bar_size;
1824         struct pci_dev *pdev = to_pci_dev(dev->dev);
1825         int bar;
1826
1827         if (dev->cmb_size)
1828                 return;
1829
1830         if (NVME_CAP_CMBS(dev->ctrl.cap))
1831                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1832
1833         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1834         if (!dev->cmbsz)
1835                 return;
1836         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1837
1838         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1839         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1840         bar = NVME_CMB_BIR(dev->cmbloc);
1841         bar_size = pci_resource_len(pdev, bar);
1842
1843         if (offset > bar_size)
1844                 return;
1845
1846         /*
1847          * Tell the controller about the host side address mapping the CMB,
1848          * and enable CMB decoding for the NVMe 1.4+ scheme:
1849          */
1850         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1851                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1852                              (pci_bus_address(pdev, bar) + offset),
1853                              dev->bar + NVME_REG_CMBMSC);
1854         }
1855
1856         /*
1857          * Controllers may support a CMB size larger than their BAR,
1858          * for example, due to being behind a bridge. Reduce the CMB to
1859          * the reported size of the BAR
1860          */
1861         if (size > bar_size - offset)
1862                 size = bar_size - offset;
1863
1864         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1865                 dev_warn(dev->ctrl.device,
1866                          "failed to register the CMB\n");
1867                 return;
1868         }
1869
1870         dev->cmb_size = size;
1871         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1872
1873         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1874                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1875                 pci_p2pmem_publish(pdev, true);
1876
1877         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1878                                     &dev_attr_cmb.attr, NULL))
1879                 dev_warn(dev->ctrl.device,
1880                          "failed to add sysfs attribute for CMB\n");
1881 }
1882
1883 static inline void nvme_release_cmb(struct nvme_dev *dev)
1884 {
1885         if (dev->cmb_size) {
1886                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1887                                              &dev_attr_cmb.attr, NULL);
1888                 dev->cmb_size = 0;
1889         }
1890 }
1891
1892 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1893 {
1894         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1895         u64 dma_addr = dev->host_mem_descs_dma;
1896         struct nvme_command c;
1897         int ret;
1898
1899         memset(&c, 0, sizeof(c));
1900         c.features.opcode       = nvme_admin_set_features;
1901         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1902         c.features.dword11      = cpu_to_le32(bits);
1903         c.features.dword12      = cpu_to_le32(host_mem_size);
1904         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1905         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1906         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1907
1908         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1909         if (ret) {
1910                 dev_warn(dev->ctrl.device,
1911                          "failed to set host mem (err %d, flags %#x).\n",
1912                          ret, bits);
1913         }
1914         return ret;
1915 }
1916
1917 static void nvme_free_host_mem(struct nvme_dev *dev)
1918 {
1919         int i;
1920
1921         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1922                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1923                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1924
1925                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1926                                le64_to_cpu(desc->addr),
1927                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1928         }
1929
1930         kfree(dev->host_mem_desc_bufs);
1931         dev->host_mem_desc_bufs = NULL;
1932         dma_free_coherent(dev->dev,
1933                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1934                         dev->host_mem_descs, dev->host_mem_descs_dma);
1935         dev->host_mem_descs = NULL;
1936         dev->nr_host_mem_descs = 0;
1937 }
1938
1939 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1940                 u32 chunk_size)
1941 {
1942         struct nvme_host_mem_buf_desc *descs;
1943         u32 max_entries, len;
1944         dma_addr_t descs_dma;
1945         int i = 0;
1946         void **bufs;
1947         u64 size, tmp;
1948
1949         tmp = (preferred + chunk_size - 1);
1950         do_div(tmp, chunk_size);
1951         max_entries = tmp;
1952
1953         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1954                 max_entries = dev->ctrl.hmmaxd;
1955
1956         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1957                                    &descs_dma, GFP_KERNEL);
1958         if (!descs)
1959                 goto out;
1960
1961         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1962         if (!bufs)
1963                 goto out_free_descs;
1964
1965         for (size = 0; size < preferred && i < max_entries; size += len) {
1966                 dma_addr_t dma_addr;
1967
1968                 len = min_t(u64, chunk_size, preferred - size);
1969                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1970                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1971                 if (!bufs[i])
1972                         break;
1973
1974                 descs[i].addr = cpu_to_le64(dma_addr);
1975                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1976                 i++;
1977         }
1978
1979         if (!size)
1980                 goto out_free_bufs;
1981
1982         dev->nr_host_mem_descs = i;
1983         dev->host_mem_size = size;
1984         dev->host_mem_descs = descs;
1985         dev->host_mem_descs_dma = descs_dma;
1986         dev->host_mem_desc_bufs = bufs;
1987         return 0;
1988
1989 out_free_bufs:
1990         while (--i >= 0) {
1991                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1992
1993                 dma_free_attrs(dev->dev, size, bufs[i],
1994                                le64_to_cpu(descs[i].addr),
1995                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1996         }
1997
1998         kfree(bufs);
1999 out_free_descs:
2000         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2001                         descs_dma);
2002 out:
2003         dev->host_mem_descs = NULL;
2004         return -ENOMEM;
2005 }
2006
2007 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2008 {
2009         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2010         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2011         u64 chunk_size;
2012
2013         /* start big and work our way down */
2014         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2015                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2016                         if (!min || dev->host_mem_size >= min)
2017                                 return 0;
2018                         nvme_free_host_mem(dev);
2019                 }
2020         }
2021
2022         return -ENOMEM;
2023 }
2024
2025 static int nvme_setup_host_mem(struct nvme_dev *dev)
2026 {
2027         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2028         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2029         u64 min = (u64)dev->ctrl.hmmin * 4096;
2030         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2031         int ret;
2032
2033         preferred = min(preferred, max);
2034         if (min > max) {
2035                 dev_warn(dev->ctrl.device,
2036                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2037                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2038                 nvme_free_host_mem(dev);
2039                 return 0;
2040         }
2041
2042         /*
2043          * If we already have a buffer allocated check if we can reuse it.
2044          */
2045         if (dev->host_mem_descs) {
2046                 if (dev->host_mem_size >= min)
2047                         enable_bits |= NVME_HOST_MEM_RETURN;
2048                 else
2049                         nvme_free_host_mem(dev);
2050         }
2051
2052         if (!dev->host_mem_descs) {
2053                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2054                         dev_warn(dev->ctrl.device,
2055                                 "failed to allocate host memory buffer.\n");
2056                         return 0; /* controller must work without HMB */
2057                 }
2058
2059                 dev_info(dev->ctrl.device,
2060                         "allocated %lld MiB host memory buffer.\n",
2061                         dev->host_mem_size >> ilog2(SZ_1M));
2062         }
2063
2064         ret = nvme_set_host_mem(dev, enable_bits);
2065         if (ret)
2066                 nvme_free_host_mem(dev);
2067         return ret;
2068 }
2069
2070 /*
2071  * nirqs is the number of interrupts available for write and read
2072  * queues. The core already reserved an interrupt for the admin queue.
2073  */
2074 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2075 {
2076         struct nvme_dev *dev = affd->priv;
2077         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2078
2079         /*
2080          * If there is no interrupt available for queues, ensure that
2081          * the default queue is set to 1. The affinity set size is
2082          * also set to one, but the irq core ignores it for this case.
2083          *
2084          * If only one interrupt is available or 'write_queue' == 0, combine
2085          * write and read queues.
2086          *
2087          * If 'write_queues' > 0, ensure it leaves room for at least one read
2088          * queue.
2089          */
2090         if (!nrirqs) {
2091                 nrirqs = 1;
2092                 nr_read_queues = 0;
2093         } else if (nrirqs == 1 || !nr_write_queues) {
2094                 nr_read_queues = 0;
2095         } else if (nr_write_queues >= nrirqs) {
2096                 nr_read_queues = 1;
2097         } else {
2098                 nr_read_queues = nrirqs - nr_write_queues;
2099         }
2100
2101         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2102         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2103         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2104         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2105         affd->nr_sets = nr_read_queues ? 2 : 1;
2106 }
2107
2108 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2109 {
2110         struct pci_dev *pdev = to_pci_dev(dev->dev);
2111         struct irq_affinity affd = {
2112                 .pre_vectors    = 1,
2113                 .calc_sets      = nvme_calc_irq_sets,
2114                 .priv           = dev,
2115         };
2116         unsigned int irq_queues, poll_queues;
2117
2118         /*
2119          * Poll queues don't need interrupts, but we need at least one I/O queue
2120          * left over for non-polled I/O.
2121          */
2122         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2123         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2124
2125         /*
2126          * Initialize for the single interrupt case, will be updated in
2127          * nvme_calc_irq_sets().
2128          */
2129         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2130         dev->io_queues[HCTX_TYPE_READ] = 0;
2131
2132         /*
2133          * We need interrupts for the admin queue and each non-polled I/O queue,
2134          * but some Apple controllers require all queues to use the first
2135          * vector.
2136          */
2137         irq_queues = 1;
2138         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2139                 irq_queues += (nr_io_queues - poll_queues);
2140         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2141                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2142 }
2143
2144 static void nvme_disable_io_queues(struct nvme_dev *dev)
2145 {
2146         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2147                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2148 }
2149
2150 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2151 {
2152         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2153 }
2154
2155 static int nvme_setup_io_queues(struct nvme_dev *dev)
2156 {
2157         struct nvme_queue *adminq = &dev->queues[0];
2158         struct pci_dev *pdev = to_pci_dev(dev->dev);
2159         unsigned int nr_io_queues;
2160         unsigned long size;
2161         int result;
2162
2163         /*
2164          * Sample the module parameters once at reset time so that we have
2165          * stable values to work with.
2166          */
2167         dev->nr_write_queues = write_queues;
2168         dev->nr_poll_queues = poll_queues;
2169
2170         /*
2171          * If tags are shared with admin queue (Apple bug), then
2172          * make sure we only use one IO queue.
2173          */
2174         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2175                 nr_io_queues = 1;
2176         else
2177                 nr_io_queues = min(nvme_max_io_queues(dev),
2178                                    dev->nr_allocated_queues - 1);
2179
2180         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2181         if (result < 0)
2182                 return result;
2183
2184         if (nr_io_queues == 0)
2185                 return 0;
2186
2187         clear_bit(NVMEQ_ENABLED, &adminq->flags);
2188
2189         if (dev->cmb_use_sqes) {
2190                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2191                                 sizeof(struct nvme_command));
2192                 if (result > 0)
2193                         dev->q_depth = result;
2194                 else
2195                         dev->cmb_use_sqes = false;
2196         }
2197
2198         do {
2199                 size = db_bar_size(dev, nr_io_queues);
2200                 result = nvme_remap_bar(dev, size);
2201                 if (!result)
2202                         break;
2203                 if (!--nr_io_queues)
2204                         return -ENOMEM;
2205         } while (1);
2206         adminq->q_db = dev->dbs;
2207
2208  retry:
2209         /* Deregister the admin queue's interrupt */
2210         pci_free_irq(pdev, 0, adminq);
2211
2212         /*
2213          * If we enable msix early due to not intx, disable it again before
2214          * setting up the full range we need.
2215          */
2216         pci_free_irq_vectors(pdev);
2217
2218         result = nvme_setup_irqs(dev, nr_io_queues);
2219         if (result <= 0)
2220                 return -EIO;
2221
2222         dev->num_vecs = result;
2223         result = max(result - 1, 1);
2224         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2225
2226         /*
2227          * Should investigate if there's a performance win from allocating
2228          * more queues than interrupt vectors; it might allow the submission
2229          * path to scale better, even if the receive path is limited by the
2230          * number of interrupts.
2231          */
2232         result = queue_request_irq(adminq);
2233         if (result)
2234                 return result;
2235         set_bit(NVMEQ_ENABLED, &adminq->flags);
2236
2237         result = nvme_create_io_queues(dev);
2238         if (result || dev->online_queues < 2)
2239                 return result;
2240
2241         if (dev->online_queues - 1 < dev->max_qid) {
2242                 nr_io_queues = dev->online_queues - 1;
2243                 nvme_disable_io_queues(dev);
2244                 nvme_suspend_io_queues(dev);
2245                 goto retry;
2246         }
2247         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2248                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2249                                         dev->io_queues[HCTX_TYPE_READ],
2250                                         dev->io_queues[HCTX_TYPE_POLL]);
2251         return 0;
2252 }
2253
2254 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2255 {
2256         struct nvme_queue *nvmeq = req->end_io_data;
2257
2258         blk_mq_free_request(req);
2259         complete(&nvmeq->delete_done);
2260 }
2261
2262 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2263 {
2264         struct nvme_queue *nvmeq = req->end_io_data;
2265
2266         if (error)
2267                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2268
2269         nvme_del_queue_end(req, error);
2270 }
2271
2272 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2273 {
2274         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2275         struct request *req;
2276         struct nvme_command cmd;
2277
2278         memset(&cmd, 0, sizeof(cmd));
2279         cmd.delete_queue.opcode = opcode;
2280         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2281
2282         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2283         if (IS_ERR(req))
2284                 return PTR_ERR(req);
2285
2286         req->end_io_data = nvmeq;
2287
2288         init_completion(&nvmeq->delete_done);
2289         blk_execute_rq_nowait(q, NULL, req, false,
2290                         opcode == nvme_admin_delete_cq ?
2291                                 nvme_del_cq_end : nvme_del_queue_end);
2292         return 0;
2293 }
2294
2295 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2296 {
2297         int nr_queues = dev->online_queues - 1, sent = 0;
2298         unsigned long timeout;
2299
2300  retry:
2301         timeout = ADMIN_TIMEOUT;
2302         while (nr_queues > 0) {
2303                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2304                         break;
2305                 nr_queues--;
2306                 sent++;
2307         }
2308         while (sent) {
2309                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2310
2311                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2312                                 timeout);
2313                 if (timeout == 0)
2314                         return false;
2315
2316                 sent--;
2317                 if (nr_queues)
2318                         goto retry;
2319         }
2320         return true;
2321 }
2322
2323 static void nvme_dev_add(struct nvme_dev *dev)
2324 {
2325         int ret;
2326
2327         if (!dev->ctrl.tagset) {
2328                 dev->tagset.ops = &nvme_mq_ops;
2329                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2330                 dev->tagset.nr_maps = 2; /* default + read */
2331                 if (dev->io_queues[HCTX_TYPE_POLL])
2332                         dev->tagset.nr_maps++;
2333                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2334                 dev->tagset.numa_node = dev->ctrl.numa_node;
2335                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2336                                                 BLK_MQ_MAX_DEPTH) - 1;
2337                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2338                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2339                 dev->tagset.driver_data = dev;
2340
2341                 /*
2342                  * Some Apple controllers requires tags to be unique
2343                  * across admin and IO queue, so reserve the first 32
2344                  * tags of the IO queue.
2345                  */
2346                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2347                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2348
2349                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2350                 if (ret) {
2351                         dev_warn(dev->ctrl.device,
2352                                 "IO queues tagset allocation failed %d\n", ret);
2353                         return;
2354                 }
2355                 dev->ctrl.tagset = &dev->tagset;
2356         } else {
2357                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2358
2359                 /* Free previously allocated queues that are no longer usable */
2360                 nvme_free_queues(dev, dev->online_queues);
2361         }
2362
2363         nvme_dbbuf_set(dev);
2364 }
2365
2366 static int nvme_pci_enable(struct nvme_dev *dev)
2367 {
2368         int result = -ENOMEM;
2369         struct pci_dev *pdev = to_pci_dev(dev->dev);
2370
2371         if (pci_enable_device_mem(pdev))
2372                 return result;
2373
2374         pci_set_master(pdev);
2375
2376         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2377                 goto disable;
2378
2379         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2380                 result = -ENODEV;
2381                 goto disable;
2382         }
2383
2384         /*
2385          * Some devices and/or platforms don't advertise or work with INTx
2386          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2387          * adjust this later.
2388          */
2389         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2390         if (result < 0)
2391                 return result;
2392
2393         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2394
2395         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2396                                 io_queue_depth);
2397         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2398         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2399         dev->dbs = dev->bar + 4096;
2400
2401         /*
2402          * Some Apple controllers require a non-standard SQE size.
2403          * Interestingly they also seem to ignore the CC:IOSQES register
2404          * so we don't bother updating it here.
2405          */
2406         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2407                 dev->io_sqes = 7;
2408         else
2409                 dev->io_sqes = NVME_NVM_IOSQES;
2410
2411         /*
2412          * Temporary fix for the Apple controller found in the MacBook8,1 and
2413          * some MacBook7,1 to avoid controller resets and data loss.
2414          */
2415         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2416                 dev->q_depth = 2;
2417                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2418                         "set queue depth=%u to work around controller resets\n",
2419                         dev->q_depth);
2420         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2421                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2422                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2423                 dev->q_depth = 64;
2424                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2425                         "set queue depth=%u\n", dev->q_depth);
2426         }
2427
2428         /*
2429          * Controllers with the shared tags quirk need the IO queue to be
2430          * big enough so that we get 32 tags for the admin queue
2431          */
2432         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2433             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2434                 dev->q_depth = NVME_AQ_DEPTH + 2;
2435                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2436                          dev->q_depth);
2437         }
2438
2439
2440         nvme_map_cmb(dev);
2441
2442         pci_enable_pcie_error_reporting(pdev);
2443         pci_save_state(pdev);
2444         return 0;
2445
2446  disable:
2447         pci_disable_device(pdev);
2448         return result;
2449 }
2450
2451 static void nvme_dev_unmap(struct nvme_dev *dev)
2452 {
2453         if (dev->bar)
2454                 iounmap(dev->bar);
2455         pci_release_mem_regions(to_pci_dev(dev->dev));
2456 }
2457
2458 static void nvme_pci_disable(struct nvme_dev *dev)
2459 {
2460         struct pci_dev *pdev = to_pci_dev(dev->dev);
2461
2462         pci_free_irq_vectors(pdev);
2463
2464         if (pci_is_enabled(pdev)) {
2465                 pci_disable_pcie_error_reporting(pdev);
2466                 pci_disable_device(pdev);
2467         }
2468 }
2469
2470 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2471 {
2472         bool dead = true, freeze = false;
2473         struct pci_dev *pdev = to_pci_dev(dev->dev);
2474
2475         mutex_lock(&dev->shutdown_lock);
2476         if (pci_is_enabled(pdev)) {
2477                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2478
2479                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2480                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2481                         freeze = true;
2482                         nvme_start_freeze(&dev->ctrl);
2483                 }
2484                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2485                         pdev->error_state  != pci_channel_io_normal);
2486         }
2487
2488         /*
2489          * Give the controller a chance to complete all entered requests if
2490          * doing a safe shutdown.
2491          */
2492         if (!dead && shutdown && freeze)
2493                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2494
2495         nvme_stop_queues(&dev->ctrl);
2496
2497         if (!dead && dev->ctrl.queue_count > 0) {
2498                 nvme_disable_io_queues(dev);
2499                 nvme_disable_admin_queue(dev, shutdown);
2500         }
2501         nvme_suspend_io_queues(dev);
2502         nvme_suspend_queue(&dev->queues[0]);
2503         nvme_pci_disable(dev);
2504         nvme_reap_pending_cqes(dev);
2505
2506         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2507         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2508         blk_mq_tagset_wait_completed_request(&dev->tagset);
2509         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2510
2511         /*
2512          * The driver will not be starting up queues again if shutting down so
2513          * must flush all entered requests to their failed completion to avoid
2514          * deadlocking blk-mq hot-cpu notifier.
2515          */
2516         if (shutdown) {
2517                 nvme_start_queues(&dev->ctrl);
2518                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2519                         blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2520         }
2521         mutex_unlock(&dev->shutdown_lock);
2522 }
2523
2524 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2525 {
2526         if (!nvme_wait_reset(&dev->ctrl))
2527                 return -EBUSY;
2528         nvme_dev_disable(dev, shutdown);
2529         return 0;
2530 }
2531
2532 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2533 {
2534         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2535                                                 NVME_CTRL_PAGE_SIZE,
2536                                                 NVME_CTRL_PAGE_SIZE, 0);
2537         if (!dev->prp_page_pool)
2538                 return -ENOMEM;
2539
2540         /* Optimisation for I/Os between 4k and 128k */
2541         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2542                                                 256, 256, 0);
2543         if (!dev->prp_small_pool) {
2544                 dma_pool_destroy(dev->prp_page_pool);
2545                 return -ENOMEM;
2546         }
2547         return 0;
2548 }
2549
2550 static void nvme_release_prp_pools(struct nvme_dev *dev)
2551 {
2552         dma_pool_destroy(dev->prp_page_pool);
2553         dma_pool_destroy(dev->prp_small_pool);
2554 }
2555
2556 static void nvme_free_tagset(struct nvme_dev *dev)
2557 {
2558         if (dev->tagset.tags)
2559                 blk_mq_free_tag_set(&dev->tagset);
2560         dev->ctrl.tagset = NULL;
2561 }
2562
2563 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2564 {
2565         struct nvme_dev *dev = to_nvme_dev(ctrl);
2566
2567         nvme_dbbuf_dma_free(dev);
2568         nvme_free_tagset(dev);
2569         if (dev->ctrl.admin_q)
2570                 blk_put_queue(dev->ctrl.admin_q);
2571         free_opal_dev(dev->ctrl.opal_dev);
2572         mempool_destroy(dev->iod_mempool);
2573         put_device(dev->dev);
2574         kfree(dev->queues);
2575         kfree(dev);
2576 }
2577
2578 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2579 {
2580         /*
2581          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2582          * may be holding this pci_dev's device lock.
2583          */
2584         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2585         nvme_get_ctrl(&dev->ctrl);
2586         nvme_dev_disable(dev, false);
2587         nvme_kill_queues(&dev->ctrl);
2588         if (!queue_work(nvme_wq, &dev->remove_work))
2589                 nvme_put_ctrl(&dev->ctrl);
2590 }
2591
2592 static void nvme_reset_work(struct work_struct *work)
2593 {
2594         struct nvme_dev *dev =
2595                 container_of(work, struct nvme_dev, ctrl.reset_work);
2596         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2597         int result;
2598
2599         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2600                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2601                          dev->ctrl.state);
2602                 result = -ENODEV;
2603                 goto out;
2604         }
2605
2606         /*
2607          * If we're called to reset a live controller first shut it down before
2608          * moving on.
2609          */
2610         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2611                 nvme_dev_disable(dev, false);
2612         nvme_sync_queues(&dev->ctrl);
2613
2614         mutex_lock(&dev->shutdown_lock);
2615         result = nvme_pci_enable(dev);
2616         if (result)
2617                 goto out_unlock;
2618
2619         result = nvme_pci_configure_admin_queue(dev);
2620         if (result)
2621                 goto out_unlock;
2622
2623         result = nvme_alloc_admin_tags(dev);
2624         if (result)
2625                 goto out_unlock;
2626
2627         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2628
2629         /*
2630          * Limit the max command size to prevent iod->sg allocations going
2631          * over a single page.
2632          */
2633         dev->ctrl.max_hw_sectors = min_t(u32,
2634                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2635         dev->ctrl.max_segments = NVME_MAX_SEGS;
2636
2637         /*
2638          * Don't limit the IOMMU merged segment size.
2639          */
2640         dma_set_max_seg_size(dev->dev, 0xffffffff);
2641
2642         mutex_unlock(&dev->shutdown_lock);
2643
2644         /*
2645          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2646          * initializing procedure here.
2647          */
2648         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2649                 dev_warn(dev->ctrl.device,
2650                         "failed to mark controller CONNECTING\n");
2651                 result = -EBUSY;
2652                 goto out;
2653         }
2654
2655         /*
2656          * We do not support an SGL for metadata (yet), so we are limited to a
2657          * single integrity segment for the separate metadata pointer.
2658          */
2659         dev->ctrl.max_integrity_segments = 1;
2660
2661         result = nvme_init_identify(&dev->ctrl);
2662         if (result)
2663                 goto out;
2664
2665         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2666                 if (!dev->ctrl.opal_dev)
2667                         dev->ctrl.opal_dev =
2668                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2669                 else if (was_suspend)
2670                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2671         } else {
2672                 free_opal_dev(dev->ctrl.opal_dev);
2673                 dev->ctrl.opal_dev = NULL;
2674         }
2675
2676         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2677                 result = nvme_dbbuf_dma_alloc(dev);
2678                 if (result)
2679                         dev_warn(dev->dev,
2680                                  "unable to allocate dma for dbbuf\n");
2681         }
2682
2683         if (dev->ctrl.hmpre) {
2684                 result = nvme_setup_host_mem(dev);
2685                 if (result < 0)
2686                         goto out;
2687         }
2688
2689         result = nvme_setup_io_queues(dev);
2690         if (result)
2691                 goto out;
2692
2693         /*
2694          * Keep the controller around but remove all namespaces if we don't have
2695          * any working I/O queue.
2696          */
2697         if (dev->online_queues < 2) {
2698                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2699                 nvme_kill_queues(&dev->ctrl);
2700                 nvme_remove_namespaces(&dev->ctrl);
2701                 nvme_free_tagset(dev);
2702         } else {
2703                 nvme_start_queues(&dev->ctrl);
2704                 nvme_wait_freeze(&dev->ctrl);
2705                 nvme_dev_add(dev);
2706                 nvme_unfreeze(&dev->ctrl);
2707         }
2708
2709         /*
2710          * If only admin queue live, keep it to do further investigation or
2711          * recovery.
2712          */
2713         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2714                 dev_warn(dev->ctrl.device,
2715                         "failed to mark controller live state\n");
2716                 result = -ENODEV;
2717                 goto out;
2718         }
2719
2720         nvme_start_ctrl(&dev->ctrl);
2721         return;
2722
2723  out_unlock:
2724         mutex_unlock(&dev->shutdown_lock);
2725  out:
2726         if (result)
2727                 dev_warn(dev->ctrl.device,
2728                          "Removing after probe failure status: %d\n", result);
2729         nvme_remove_dead_ctrl(dev);
2730 }
2731
2732 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2733 {
2734         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2735         struct pci_dev *pdev = to_pci_dev(dev->dev);
2736
2737         if (pci_get_drvdata(pdev))
2738                 device_release_driver(&pdev->dev);
2739         nvme_put_ctrl(&dev->ctrl);
2740 }
2741
2742 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2743 {
2744         *val = readl(to_nvme_dev(ctrl)->bar + off);
2745         return 0;
2746 }
2747
2748 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2749 {
2750         writel(val, to_nvme_dev(ctrl)->bar + off);
2751         return 0;
2752 }
2753
2754 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2755 {
2756         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2757         return 0;
2758 }
2759
2760 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2761 {
2762         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2763
2764         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2765 }
2766
2767 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2768         .name                   = "pcie",
2769         .module                 = THIS_MODULE,
2770         .flags                  = NVME_F_METADATA_SUPPORTED |
2771                                   NVME_F_PCI_P2PDMA,
2772         .reg_read32             = nvme_pci_reg_read32,
2773         .reg_write32            = nvme_pci_reg_write32,
2774         .reg_read64             = nvme_pci_reg_read64,
2775         .free_ctrl              = nvme_pci_free_ctrl,
2776         .submit_async_event     = nvme_pci_submit_async_event,
2777         .get_address            = nvme_pci_get_address,
2778 };
2779
2780 static int nvme_dev_map(struct nvme_dev *dev)
2781 {
2782         struct pci_dev *pdev = to_pci_dev(dev->dev);
2783
2784         if (pci_request_mem_regions(pdev, "nvme"))
2785                 return -ENODEV;
2786
2787         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2788                 goto release;
2789
2790         return 0;
2791   release:
2792         pci_release_mem_regions(pdev);
2793         return -ENODEV;
2794 }
2795
2796 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2797 {
2798         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2799                 /*
2800                  * Several Samsung devices seem to drop off the PCIe bus
2801                  * randomly when APST is on and uses the deepest sleep state.
2802                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2803                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2804                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2805                  * laptops.
2806                  */
2807                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2808                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2809                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2810                         return NVME_QUIRK_NO_DEEPEST_PS;
2811         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2812                 /*
2813                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2814                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2815                  * within few minutes after bootup on a Coffee Lake board -
2816                  * ASUS PRIME Z370-A
2817                  */
2818                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2819                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2820                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2821                         return NVME_QUIRK_NO_APST;
2822         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2823                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2824                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2825                 /*
2826                  * Forcing to use host managed nvme power settings for
2827                  * lowest idle power with quick resume latency on
2828                  * Samsung and Toshiba SSDs based on suspend behavior
2829                  * on Coffee Lake board for LENOVO C640
2830                  */
2831                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2832                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2833                         return NVME_QUIRK_SIMPLE_SUSPEND;
2834         }
2835
2836         return 0;
2837 }
2838
2839 #ifdef CONFIG_ACPI
2840 static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2841 {
2842         struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
2843         u8 val;
2844
2845         /*
2846          * Look for _DSD property specifying that the storage device on the port
2847          * must use D3 to support deep platform power savings during
2848          * suspend-to-idle.
2849          */
2850
2851         if (!adev)
2852                 return false;
2853         if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2854                         &val))
2855                 return false;
2856         return val == 1;
2857 }
2858 #else
2859 static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2860 {
2861         return false;
2862 }
2863 #endif /* CONFIG_ACPI */
2864
2865 static void nvme_async_probe(void *data, async_cookie_t cookie)
2866 {
2867         struct nvme_dev *dev = data;
2868
2869         flush_work(&dev->ctrl.reset_work);
2870         flush_work(&dev->ctrl.scan_work);
2871         nvme_put_ctrl(&dev->ctrl);
2872 }
2873
2874 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2875 {
2876         int node, result = -ENOMEM;
2877         struct nvme_dev *dev;
2878         unsigned long quirks = id->driver_data;
2879         size_t alloc_size;
2880
2881         node = dev_to_node(&pdev->dev);
2882         if (node == NUMA_NO_NODE)
2883                 set_dev_node(&pdev->dev, first_memory_node);
2884
2885         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2886         if (!dev)
2887                 return -ENOMEM;
2888
2889         dev->nr_write_queues = write_queues;
2890         dev->nr_poll_queues = poll_queues;
2891         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2892         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2893                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2894         if (!dev->queues)
2895                 goto free;
2896
2897         dev->dev = get_device(&pdev->dev);
2898         pci_set_drvdata(pdev, dev);
2899
2900         result = nvme_dev_map(dev);
2901         if (result)
2902                 goto put_pci;
2903
2904         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2905         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2906         mutex_init(&dev->shutdown_lock);
2907
2908         result = nvme_setup_prp_pools(dev);
2909         if (result)
2910                 goto unmap;
2911
2912         quirks |= check_vendor_combination_bug(pdev);
2913
2914         if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2915                 /*
2916                  * Some systems use a bios work around to ask for D3 on
2917                  * platforms that support kernel managed suspend.
2918                  */
2919                 dev_info(&pdev->dev,
2920                          "platform quirk: setting simple suspend\n");
2921                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2922         }
2923
2924         /*
2925          * Double check that our mempool alloc size will cover the biggest
2926          * command we support.
2927          */
2928         alloc_size = nvme_pci_iod_alloc_size();
2929         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2930
2931         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2932                                                 mempool_kfree,
2933                                                 (void *) alloc_size,
2934                                                 GFP_KERNEL, node);
2935         if (!dev->iod_mempool) {
2936                 result = -ENOMEM;
2937                 goto release_pools;
2938         }
2939
2940         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2941                         quirks);
2942         if (result)
2943                 goto release_mempool;
2944
2945         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2946
2947         nvme_reset_ctrl(&dev->ctrl);
2948         async_schedule(nvme_async_probe, dev);
2949
2950         return 0;
2951
2952  release_mempool:
2953         mempool_destroy(dev->iod_mempool);
2954  release_pools:
2955         nvme_release_prp_pools(dev);
2956  unmap:
2957         nvme_dev_unmap(dev);
2958  put_pci:
2959         put_device(dev->dev);
2960  free:
2961         kfree(dev->queues);
2962         kfree(dev);
2963         return result;
2964 }
2965
2966 static void nvme_reset_prepare(struct pci_dev *pdev)
2967 {
2968         struct nvme_dev *dev = pci_get_drvdata(pdev);
2969
2970         /*
2971          * We don't need to check the return value from waiting for the reset
2972          * state as pci_dev device lock is held, making it impossible to race
2973          * with ->remove().
2974          */
2975         nvme_disable_prepare_reset(dev, false);
2976         nvme_sync_queues(&dev->ctrl);
2977 }
2978
2979 static void nvme_reset_done(struct pci_dev *pdev)
2980 {
2981         struct nvme_dev *dev = pci_get_drvdata(pdev);
2982
2983         if (!nvme_try_sched_reset(&dev->ctrl))
2984                 flush_work(&dev->ctrl.reset_work);
2985 }
2986
2987 static void nvme_shutdown(struct pci_dev *pdev)
2988 {
2989         struct nvme_dev *dev = pci_get_drvdata(pdev);
2990
2991         nvme_disable_prepare_reset(dev, true);
2992 }
2993
2994 /*
2995  * The driver's remove may be called on a device in a partially initialized
2996  * state. This function must not have any dependencies on the device state in
2997  * order to proceed.
2998  */
2999 static void nvme_remove(struct pci_dev *pdev)
3000 {
3001         struct nvme_dev *dev = pci_get_drvdata(pdev);
3002
3003         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3004         pci_set_drvdata(pdev, NULL);
3005
3006         if (!pci_device_is_present(pdev)) {
3007                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3008                 nvme_dev_disable(dev, true);
3009         }
3010
3011         flush_work(&dev->ctrl.reset_work);
3012         nvme_stop_ctrl(&dev->ctrl);
3013         nvme_remove_namespaces(&dev->ctrl);
3014         nvme_dev_disable(dev, true);
3015         nvme_release_cmb(dev);
3016         nvme_free_host_mem(dev);
3017         nvme_dev_remove_admin(dev);
3018         nvme_free_queues(dev, 0);
3019         nvme_release_prp_pools(dev);
3020         nvme_dev_unmap(dev);
3021         nvme_uninit_ctrl(&dev->ctrl);
3022 }
3023
3024 #ifdef CONFIG_PM_SLEEP
3025 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3026 {
3027         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3028 }
3029
3030 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3031 {
3032         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3033 }
3034
3035 static int nvme_resume(struct device *dev)
3036 {
3037         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3038         struct nvme_ctrl *ctrl = &ndev->ctrl;
3039
3040         if (ndev->last_ps == U32_MAX ||
3041             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3042                 return nvme_try_sched_reset(&ndev->ctrl);
3043         return 0;
3044 }
3045
3046 static int nvme_suspend(struct device *dev)
3047 {
3048         struct pci_dev *pdev = to_pci_dev(dev);
3049         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3050         struct nvme_ctrl *ctrl = &ndev->ctrl;
3051         int ret = -EBUSY;
3052
3053         ndev->last_ps = U32_MAX;
3054
3055         /*
3056          * The platform does not remove power for a kernel managed suspend so
3057          * use host managed nvme power settings for lowest idle power if
3058          * possible. This should have quicker resume latency than a full device
3059          * shutdown.  But if the firmware is involved after the suspend or the
3060          * device does not support any non-default power states, shut down the
3061          * device fully.
3062          *
3063          * If ASPM is not enabled for the device, shut down the device and allow
3064          * the PCI bus layer to put it into D3 in order to take the PCIe link
3065          * down, so as to allow the platform to achieve its minimum low-power
3066          * state (which may not be possible if the link is up).
3067          *
3068          * If a host memory buffer is enabled, shut down the device as the NVMe
3069          * specification allows the device to access the host memory buffer in
3070          * host DRAM from all power states, but hosts will fail access to DRAM
3071          * during S3.
3072          */
3073         if (pm_suspend_via_firmware() || !ctrl->npss ||
3074             !pcie_aspm_enabled(pdev) ||
3075             ndev->nr_host_mem_descs ||
3076             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3077                 return nvme_disable_prepare_reset(ndev, true);
3078
3079         nvme_start_freeze(ctrl);
3080         nvme_wait_freeze(ctrl);
3081         nvme_sync_queues(ctrl);
3082
3083         if (ctrl->state != NVME_CTRL_LIVE)
3084                 goto unfreeze;
3085
3086         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3087         if (ret < 0)
3088                 goto unfreeze;
3089
3090         /*
3091          * A saved state prevents pci pm from generically controlling the
3092          * device's power. If we're using protocol specific settings, we don't
3093          * want pci interfering.
3094          */
3095         pci_save_state(pdev);
3096
3097         ret = nvme_set_power_state(ctrl, ctrl->npss);
3098         if (ret < 0)
3099                 goto unfreeze;
3100
3101         if (ret) {
3102                 /* discard the saved state */
3103                 pci_load_saved_state(pdev, NULL);
3104
3105                 /*
3106                  * Clearing npss forces a controller reset on resume. The
3107                  * correct value will be rediscovered then.
3108                  */
3109                 ret = nvme_disable_prepare_reset(ndev, true);
3110                 ctrl->npss = 0;
3111         }
3112 unfreeze:
3113         nvme_unfreeze(ctrl);
3114         return ret;
3115 }
3116
3117 static int nvme_simple_suspend(struct device *dev)
3118 {
3119         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3120
3121         return nvme_disable_prepare_reset(ndev, true);
3122 }
3123
3124 static int nvme_simple_resume(struct device *dev)
3125 {
3126         struct pci_dev *pdev = to_pci_dev(dev);
3127         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3128
3129         return nvme_try_sched_reset(&ndev->ctrl);
3130 }
3131
3132 static const struct dev_pm_ops nvme_dev_pm_ops = {
3133         .suspend        = nvme_suspend,
3134         .resume         = nvme_resume,
3135         .freeze         = nvme_simple_suspend,
3136         .thaw           = nvme_simple_resume,
3137         .poweroff       = nvme_simple_suspend,
3138         .restore        = nvme_simple_resume,
3139 };
3140 #endif /* CONFIG_PM_SLEEP */
3141
3142 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3143                                                 pci_channel_state_t state)
3144 {
3145         struct nvme_dev *dev = pci_get_drvdata(pdev);
3146
3147         /*
3148          * A frozen channel requires a reset. When detected, this method will
3149          * shutdown the controller to quiesce. The controller will be restarted
3150          * after the slot reset through driver's slot_reset callback.
3151          */
3152         switch (state) {
3153         case pci_channel_io_normal:
3154                 return PCI_ERS_RESULT_CAN_RECOVER;
3155         case pci_channel_io_frozen:
3156                 dev_warn(dev->ctrl.device,
3157                         "frozen state error detected, reset controller\n");
3158                 nvme_dev_disable(dev, false);
3159                 return PCI_ERS_RESULT_NEED_RESET;
3160         case pci_channel_io_perm_failure:
3161                 dev_warn(dev->ctrl.device,
3162                         "failure state error detected, request disconnect\n");
3163                 return PCI_ERS_RESULT_DISCONNECT;
3164         }
3165         return PCI_ERS_RESULT_NEED_RESET;
3166 }
3167
3168 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3169 {
3170         struct nvme_dev *dev = pci_get_drvdata(pdev);
3171
3172         dev_info(dev->ctrl.device, "restart after slot reset\n");
3173         pci_restore_state(pdev);
3174         nvme_reset_ctrl(&dev->ctrl);
3175         return PCI_ERS_RESULT_RECOVERED;
3176 }
3177
3178 static void nvme_error_resume(struct pci_dev *pdev)
3179 {
3180         struct nvme_dev *dev = pci_get_drvdata(pdev);
3181
3182         flush_work(&dev->ctrl.reset_work);
3183 }
3184
3185 static const struct pci_error_handlers nvme_err_handler = {
3186         .error_detected = nvme_error_detected,
3187         .slot_reset     = nvme_slot_reset,
3188         .resume         = nvme_error_resume,
3189         .reset_prepare  = nvme_reset_prepare,
3190         .reset_done     = nvme_reset_done,
3191 };
3192
3193 static const struct pci_device_id nvme_id_table[] = {
3194         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3195                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3196                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3197         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3198                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3199                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3200         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3201                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3202                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3203                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3204         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3205                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3206                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3207         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3208                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3209                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3210                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3211                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3212         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3213                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3214         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3215                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3216                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3217                                 NVME_QUIRK_BOGUS_NID, },
3218         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3219                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3220         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3221                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3222         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3223                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3224                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3225         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3226                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3227         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3228                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3229         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3230                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3231         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3232                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3233         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3234                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3235                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3236                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3237         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3238                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3239                                 NVME_QUIRK_BOGUS_NID, },
3240         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3241                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3242                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3243         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
3244                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3245         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
3246                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3247         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
3248                 .driver_data = NVME_QUIRK_LIGHTNVM, },
3249         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3250                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3251                                 NVME_QUIRK_BOGUS_NID, },
3252         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3253                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3254                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3255         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3256                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3257         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3258                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3259         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3260                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3261         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3262                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3263         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3264                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3265         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3266         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3267                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3268                                 NVME_QUIRK_128_BYTES_SQES |
3269                                 NVME_QUIRK_SHARED_TAGS |
3270                                 NVME_QUIRK_SKIP_CID_GEN },
3271         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3272         { 0, }
3273 };
3274 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3275
3276 static struct pci_driver nvme_driver = {
3277         .name           = "nvme",
3278         .id_table       = nvme_id_table,
3279         .probe          = nvme_probe,
3280         .remove         = nvme_remove,
3281         .shutdown       = nvme_shutdown,
3282 #ifdef CONFIG_PM_SLEEP
3283         .driver         = {
3284                 .pm     = &nvme_dev_pm_ops,
3285         },
3286 #endif
3287         .sriov_configure = pci_sriov_configure_simple,
3288         .err_handler    = &nvme_err_handler,
3289 };
3290
3291 static int __init nvme_init(void)
3292 {
3293         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3294         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3295         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3296         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3297
3298         return pci_register_driver(&nvme_driver);
3299 }
3300
3301 static void __exit nvme_exit(void)
3302 {
3303         pci_unregister_driver(&nvme_driver);
3304         flush_workqueue(nvme_wq);
3305 }
3306
3307 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3308 MODULE_LICENSE("GPL");
3309 MODULE_VERSION("1.0");
3310 module_init(nvme_init);
3311 module_exit(nvme_exit);