1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, MediaTek Inc.
4 * Copyright (c) 2021-2022, Intel Corporation.
7 * Amir Hanania <amir.hanania@intel.com>
8 * Haijun Liu <haijun.liu@mediatek.com>
9 * Moises Veleta <moises.veleta@intel.com>
10 * Ricardo Martinez <ricardo.martinez@linux.intel.com>
13 * Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
14 * Eliot Lee <eliot.lee@intel.com>
15 * Sreehari Kancharla <sreehari.kancharla@intel.com>
18 #ifndef __T7XX_HIF_DPMAIF_H__
19 #define __T7XX_HIF_DPMAIF_H__
21 #include <linux/bitmap.h>
22 #include <linux/mm_types.h>
23 #include <linux/netdevice.h>
24 #include <linux/sched.h>
25 #include <linux/skbuff.h>
26 #include <linux/spinlock.h>
27 #include <linux/types.h>
28 #include <linux/wait.h>
29 #include <linux/workqueue.h>
31 #include "t7xx_dpmaif.h"
33 #include "t7xx_state_monitor.h"
35 /* SKB control buffer */
42 #define T7XX_SKB_CB(__skb) ((struct t7xx_skb_cb *)(__skb)->cb)
49 /* Structure of DL BAT */
50 struct dpmaif_cur_rx_skb_info {
51 bool msg_pit_received;
52 struct sk_buff *cur_skb;
53 unsigned int cur_chn_idx;
54 unsigned int check_sum;
56 unsigned int pkt_type;
61 unsigned int p_buffer_addr;
62 unsigned int buffer_addr_ext;
65 struct dpmaif_bat_skb {
67 dma_addr_t data_bus_addr;
68 unsigned int data_len;
71 struct dpmaif_bat_page {
73 dma_addr_t data_bus_addr;
75 unsigned int data_len;
83 struct dpmaif_bat_request {
85 dma_addr_t bat_bus_addr;
86 unsigned int bat_size_cnt;
87 unsigned int bat_wr_idx;
88 unsigned int bat_release_rd_idx;
90 unsigned int pkt_buf_sz;
91 unsigned long *bat_bitmap;
93 spinlock_t mask_lock; /* Protects BAT mask */
97 struct dpmaif_rx_queue {
103 dma_addr_t pit_bus_addr;
104 unsigned int pit_size_cnt;
106 unsigned int pit_rd_idx;
107 unsigned int pit_wr_idx;
108 unsigned int pit_release_rd_idx;
110 struct dpmaif_bat_request *bat_req;
111 struct dpmaif_bat_request *bat_frag;
113 atomic_t rx_processing;
115 struct dpmaif_ctrl *dpmaif_ctrl;
116 unsigned int expect_pit_seq;
117 unsigned int pit_remain_release_cnt;
118 struct dpmaif_cur_rx_skb_info rx_data_info;
119 struct napi_struct napi;
120 bool sleep_lock_pending;
123 struct dpmaif_tx_queue {
128 dma_addr_t drb_bus_addr;
129 unsigned int drb_size_cnt;
130 unsigned int drb_wr_idx;
131 unsigned int drb_rd_idx;
132 unsigned int drb_release_rd_idx;
134 wait_queue_head_t req_wq;
135 struct workqueue_struct *worker;
136 struct work_struct dpmaif_tx_work;
137 spinlock_t tx_lock; /* Protects txq DRB */
138 atomic_t tx_processing;
140 struct dpmaif_ctrl *dpmaif_ctrl;
141 struct sk_buff_head tx_skb_head;
144 struct dpmaif_isr_para {
145 struct dpmaif_ctrl *dpmaif_ctrl;
146 unsigned char pcie_int;
147 unsigned char dlq_id;
154 DPMAIF_STATE_EXCEPTION,
158 enum dpmaif_txq_state {
159 DMPAIF_TXQ_STATE_IRQ,
160 DMPAIF_TXQ_STATE_FULL,
163 struct dpmaif_callbacks {
164 void (*state_notify)(struct t7xx_pci_dev *t7xx_dev,
165 enum dpmaif_txq_state state, int txq_number);
166 void (*recv_skb)(struct t7xx_ccmni_ctrl *ccmni_ctlb, struct sk_buff *skb,
167 struct napi_struct *napi);
172 struct t7xx_pci_dev *t7xx_dev;
173 struct md_pm_entity dpmaif_pm_entity;
174 enum dpmaif_state state;
175 bool dpmaif_sw_init_done;
176 struct dpmaif_hw_info hw_info;
177 struct dpmaif_tx_queue txq[DPMAIF_TXQ_NUM];
178 struct dpmaif_rx_queue rxq[DPMAIF_RXQ_NUM];
180 unsigned char rxq_int_mapping[DPMAIF_RXQ_NUM];
181 struct dpmaif_isr_para isr_para[DPMAIF_RXQ_NUM];
183 struct dpmaif_bat_request bat_req;
184 struct dpmaif_bat_request bat_frag;
185 struct workqueue_struct *bat_release_wq;
186 struct work_struct bat_release_work;
188 wait_queue_head_t tx_wq;
189 struct task_struct *tx_thread;
191 struct dpmaif_callbacks *callbacks;
194 struct dpmaif_ctrl *t7xx_dpmaif_hif_init(struct t7xx_pci_dev *t7xx_dev,
195 struct dpmaif_callbacks *callbacks);
196 void t7xx_dpmaif_hif_exit(struct dpmaif_ctrl *dpmaif_ctrl);
197 int t7xx_dpmaif_md_state_callback(struct dpmaif_ctrl *dpmaif_ctrl, enum md_state state);
198 unsigned int t7xx_ring_buf_get_next_wr_idx(unsigned int buf_len, unsigned int buf_idx);
199 unsigned int t7xx_ring_buf_rd_wr_count(unsigned int total_cnt, unsigned int rd_idx,
200 unsigned int wr_idx, enum dpmaif_rdwr);
202 #endif /* __T7XX_HIF_DPMAIF_H__ */