1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * This file is part of wl1271
5 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
6 * Copyright (C) 2008-2010 Nokia Corporation
8 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
17 /*************************************************************************
19 Host Interrupt Register (WiLink -> Host)
21 **************************************************************************/
22 /* HW Initiated interrupt Watchdog timer expiration */
23 #define WL1271_ACX_INTR_WATCHDOG BIT(0)
24 /* Init sequence is done (masked interrupt, detection through polling only ) */
25 #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
26 /* Event was entered to Event MBOX #A*/
27 #define WL1271_ACX_INTR_EVENT_A BIT(2)
28 /* Event was entered to Event MBOX #B*/
29 #define WL1271_ACX_INTR_EVENT_B BIT(3)
30 /* Command processing completion*/
31 #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
32 /* Signaling the host on HW wakeup */
33 #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
34 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
35 #define WL1271_ACX_INTR_DATA BIT(6)
36 /* Trace message on MBOX #A */
37 #define WL1271_ACX_INTR_TRACE_A BIT(7)
38 /* Trace message on MBOX #B */
39 #define WL1271_ACX_INTR_TRACE_B BIT(8)
40 /* SW FW Initiated interrupt Watchdog timer expiration */
41 #define WL1271_ACX_SW_INTR_WATCHDOG BIT(9)
43 #define WL1271_ACX_INTR_ALL 0xFFFFFFFF
45 /* all possible interrupts - only appropriate ones will be masked in */
46 #define WLCORE_ALL_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
47 WL1271_ACX_INTR_EVENT_A | \
48 WL1271_ACX_INTR_EVENT_B | \
49 WL1271_ACX_INTR_HW_AVAILABLE | \
50 WL1271_ACX_INTR_DATA | \
51 WL1271_ACX_SW_INTR_WATCHDOG)
53 /* Target's information element */
55 struct wl1271_cmd_header cmd;
57 /* acx (or information element) header */
60 /* payload length (not including headers */
64 struct acx_error_counter {
65 struct acx_header header;
67 /* The number of PLCP errors since the last time this */
68 /* information element was interrogated. This field is */
69 /* automatically cleared when it is interrogated.*/
72 /* The number of FCS errors since the last time this */
73 /* information element was interrogated. This field is */
74 /* automatically cleared when it is interrogated.*/
77 /* The number of MPDUs without PLCP header errors received*/
78 /* since the last time this information element was interrogated. */
79 /* This field is automatically cleared when it is interrogated.*/
82 /* the number of missed sequence numbers in the squentially */
83 /* values of frames seq numbers */
94 WL1271_ROLE_MESH_POINT,
96 WL12XX_INVALID_ROLE_TYPE = 0xff
99 enum wl1271_psm_mode {
103 /* Power save mode */
106 /* Extreme low power */
109 WL1271_PSM_MAX = WL1271_PSM_ELP,
111 /* illegal out of band value of PSM mode */
112 WL1271_PSM_ILLEGAL = 0xff
115 struct acx_sleep_auth {
116 struct acx_header header;
118 /* The sleep level authorization of the device. */
119 /* 0 - Always active*/
120 /* 1 - Power down mode: light / fast sleep*/
121 /* 2 - ELP mode: Deep / Max sleep*/
127 HOSTIF_PCI_MASTER_HOST_INDIRECT,
128 HOSTIF_PCI_MASTER_HOST_DIRECT,
131 HOSTIF_DONTCARE = 0xFF
134 #define DEFAULT_UCAST_PRIORITY 0
135 #define DEFAULT_RX_Q_PRIORITY 0
136 #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
137 #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
138 #define TRACE_BUFFER_MAX_SIZE 256
140 #define DP_RX_PACKET_RING_CHUNK_SIZE 1600
141 #define DP_TX_PACKET_RING_CHUNK_SIZE 1600
142 #define DP_RX_PACKET_RING_CHUNK_NUM 2
143 #define DP_TX_PACKET_RING_CHUNK_NUM 2
144 #define DP_TX_COMPLETE_TIME_OUT 20
146 #define TX_MSDU_LIFETIME_MIN 0
147 #define TX_MSDU_LIFETIME_MAX 3000
148 #define TX_MSDU_LIFETIME_DEF 512
149 #define RX_MSDU_LIFETIME_MIN 0
150 #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
151 #define RX_MSDU_LIFETIME_DEF 512000
153 struct acx_rx_msdu_lifetime {
154 struct acx_header header;
157 * The maximum amount of time, in TU, before the
158 * firmware discards the MSDU.
166 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
167 MAX_SLOT_TIMES = 0xFF
170 #define STATION_WONE_INDEX 0
173 struct acx_header header;
176 u8 wone_index; /* Reserved */
182 #define ACX_MC_ADDRESS_GROUP_MAX (8)
183 #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
185 struct acx_dot11_grp_addr_tbl {
186 struct acx_header header;
192 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
195 struct acx_rx_timeout {
196 struct acx_header header;
200 __le16 ps_poll_timeout;
205 struct acx_rts_threshold {
206 struct acx_header header;
213 struct acx_beacon_filter_option {
214 struct acx_header header;
219 * The number of beacons without the unicast TIM
220 * bit set that the firmware buffers before
221 * signaling the host about ready frames.
222 * When set to 0 and the filter is enabled, beacons
223 * without the unicast TIM bit set are dropped.
230 * ACXBeaconFilterEntry (not 221)
231 * Byte Offset Size (Bytes) Definition
232 * =========== ============ ==========
234 * 1 1 Treatment bit mask
236 * ACXBeaconFilterEntry (221)
237 * Byte Offset Size (Bytes) Definition
238 * =========== ============ ==========
240 * 1 1 Treatment bit mask
246 * Treatment bit mask - The information element handling:
247 * bit 0 - The information element is compared and transferred
249 * bit 1 - The information element is transferred to the host
250 * with each appearance or disappearance.
251 * Note that both bits can be set at the same time.
253 #define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
254 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
255 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
256 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
257 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
258 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
259 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
260 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
262 struct acx_beacon_filter_ie_table {
263 struct acx_header header;
268 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
271 struct acx_conn_monit_params {
272 struct acx_header header;
276 __le32 synch_fail_thold; /* number of beacons missed */
277 __le32 bss_lose_timeout; /* number of TU's from synch fail */
280 struct acx_bt_wlan_coex {
281 struct acx_header header;
287 struct acx_bt_wlan_coex_param {
288 struct acx_header header;
290 __le32 params[WLCORE_CONF_SG_PARAMS_MAX];
295 struct acx_dco_itrim_params {
296 struct acx_header header;
303 struct acx_energy_detection {
304 struct acx_header header;
306 /* The RX Clear Channel Assessment threshold in the PHY */
307 __le16 rx_cca_threshold;
308 u8 tx_energy_detection;
312 struct acx_beacon_broadcast {
313 struct acx_header header;
316 /* Enables receiving of broadcast packets in PS mode */
317 u8 rx_broadcast_in_ps;
319 __le16 beacon_rx_timeout;
320 __le16 broadcast_timeout;
322 /* Consecutive PS Poll failures before updating the host */
323 u8 ps_poll_threshold;
327 struct acx_event_mask {
328 struct acx_header header;
331 __le32 high_event_mask; /* Unused */
334 #define SCAN_PASSIVE BIT(0)
335 #define SCAN_5GHZ_BAND BIT(1)
336 #define SCAN_TRIGGERED BIT(2)
337 #define SCAN_PRIORITY_HIGH BIT(3)
339 /* When set, disable HW encryption */
340 #define DF_ENCRYPTION_DISABLE 0x01
341 #define DF_SNIFF_MODE_ENABLE 0x80
343 struct acx_feature_config {
344 struct acx_header header;
349 __le32 data_flow_options;
352 struct acx_current_tx_power {
353 struct acx_header header;
360 struct acx_wake_up_condition {
361 struct acx_header header;
364 u8 wake_up_event; /* Only one bit can be set */
370 struct acx_header header;
373 * To be set when associated with an AP.
380 enum acx_preamble_type {
381 ACX_PREAMBLE_LONG = 0,
382 ACX_PREAMBLE_SHORT = 1
385 struct acx_preamble {
386 struct acx_header header;
389 * When set, the WiLink transmits the frames with a short preamble and
390 * when cleared, the WiLink transmits the frames with a long preamble.
397 enum acx_ctsprotect_type {
398 CTSPROTECT_DISABLE = 0,
399 CTSPROTECT_ENABLE = 1
402 struct acx_ctsprotect {
403 struct acx_header header;
409 struct acx_rate_class {
410 __le32 enabled_rates;
411 u8 short_retry_limit;
417 struct acx_rate_policy {
418 struct acx_header header;
420 __le32 rate_policy_idx;
421 struct acx_rate_class rate_policy;
425 struct acx_header header;
434 struct acx_tid_config {
435 struct acx_header header;
446 struct acx_frag_threshold {
447 struct acx_header header;
448 __le16 frag_threshold;
452 struct acx_tx_config_options {
453 struct acx_header header;
454 __le16 tx_compl_timeout; /* msec */
455 __le16 tx_compl_threshold; /* number of packets */
458 struct wl12xx_acx_config_memory {
459 struct acx_header header;
462 u8 tx_min_mem_block_num;
464 u8 num_ssid_profiles;
465 __le32 total_tx_descriptors;
474 struct wl1271_acx_mem_map {
475 struct acx_header header;
480 __le32 wep_defkey_start;
481 __le32 wep_defkey_end;
483 __le32 sta_table_start;
484 __le32 sta_table_end;
486 __le32 packet_template_start;
487 __le32 packet_template_end;
489 /* Address of the TX result interface (control block) */
491 __le32 tx_result_queue_start;
493 __le32 queue_memory_start;
494 __le32 queue_memory_end;
496 __le32 packet_memory_pool_start;
497 __le32 packet_memory_pool_end;
499 __le32 debug_buffer1_start;
500 __le32 debug_buffer1_end;
502 __le32 debug_buffer2_start;
503 __le32 debug_buffer2_end;
505 /* Number of blocks FW allocated for TX packets */
506 __le32 num_tx_mem_blocks;
508 /* Number of blocks FW allocated for RX packets */
509 __le32 num_rx_mem_blocks;
511 /* the following 4 fields are valid in SLAVE mode only */
518 struct wl1271_acx_rx_config_opt {
519 struct acx_header header;
521 __le16 mblk_threshold;
529 struct wl1271_acx_bet_enable {
530 struct acx_header header;
538 #define ACX_IPV4_VERSION 4
539 #define ACX_IPV6_VERSION 6
540 #define ACX_IPV4_ADDR_SIZE 4
542 /* bitmap of enabled arp_filter features */
543 #define ACX_ARP_FILTER_ARP_FILTERING BIT(0)
544 #define ACX_ARP_FILTER_AUTO_ARP BIT(1)
546 struct wl1271_acx_arp_filter {
547 struct acx_header header;
549 u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
550 u8 enable; /* bitmap of enabled ARP filtering features */
552 u8 address[16]; /* The configured device IP address - all ARP
553 requests directed to this IP address will pass
554 through. For IPv4, the first four bytes are
558 struct wl1271_acx_pm_config {
559 struct acx_header header;
561 __le32 host_clk_settling_time;
562 u8 host_fast_wakeup_support;
566 struct wl1271_acx_keep_alive_mode {
567 struct acx_header header;
575 ACX_KEEP_ALIVE_NO_TX = 0,
576 ACX_KEEP_ALIVE_PERIOD_ONLY
580 ACX_KEEP_ALIVE_TPL_INVALID = 0,
581 ACX_KEEP_ALIVE_TPL_VALID
584 struct wl1271_acx_keep_alive_config {
585 struct acx_header header;
594 /* TODO: maybe this needs to be moved somewhere else? */
595 #define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0)
596 #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
597 #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)
598 #define HOST_IF_CFG_RX_PAD_TO_SDIO_BLK BIT(4)
599 #define HOST_IF_CFG_ADD_RX_ALIGNMENT BIT(6)
602 WL1271_ACX_TRIG_TYPE_LEVEL = 0,
603 WL1271_ACX_TRIG_TYPE_EDGE,
607 WL1271_ACX_TRIG_DIR_LOW = 0,
608 WL1271_ACX_TRIG_DIR_HIGH,
609 WL1271_ACX_TRIG_DIR_BIDIR,
613 WL1271_ACX_TRIG_ENABLE = 1,
614 WL1271_ACX_TRIG_DISABLE,
618 WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
619 WL1271_ACX_TRIG_METRIC_RSSI_DATA,
620 WL1271_ACX_TRIG_METRIC_SNR_BEACON,
621 WL1271_ACX_TRIG_METRIC_SNR_DATA,
625 WL1271_ACX_TRIG_IDX_RSSI = 0,
626 WL1271_ACX_TRIG_COUNT = 8,
629 struct wl1271_acx_rssi_snr_trigger {
630 struct acx_header header;
637 __le16 pacing; /* 0 - 60000 ms */
644 struct wl1271_acx_rssi_snr_avg_weights {
645 struct acx_header header;
656 /* special capability bit (not employed by the 802.11n spec) */
657 #define WL12XX_HT_CAP_HT_OPERATION BIT(16)
661 * Configure HT capabilities - declare the capabilities of the peer
662 * we are connected to.
664 struct wl1271_acx_ht_capabilities {
665 struct acx_header header;
667 /* bitmask of capability bits supported by the peer */
668 __le32 ht_capabilites;
670 /* Indicates to which link these capabilities apply. */
674 * This the maximum A-MPDU length supported by the AP. The FW may not
675 * exceed this length when sending A-MPDUs
679 /* This is the minimal spacing required when sending A-MPDUs to the AP*/
680 u8 ampdu_min_spacing;
686 * ACX_HT_BSS_OPERATION
687 * Configure HT capabilities - AP rules for behavior in the BSS.
689 struct wl1271_acx_ht_information {
690 struct acx_header header;
694 /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
697 /* Values: 0 - 3 like in spec */
700 /* Values: 0 - GF protection not required, 1 - GF protection required */
703 /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
704 u8 ht_tx_burst_limit;
707 * Values: 0 - Dual CTS protection not required,
708 * 1 - Dual CTS Protection required
709 * Note: When this value is set to 1 FW will protect all TXOP with RTS
710 * frame and will not use CTS-to-self regardless of the value of the
711 * ACX_CTS_PROTECTION information element
713 u8 dual_cts_protection;
718 struct wl1271_acx_ba_initiator_policy {
719 struct acx_header header;
721 /* Specifies role Id, Range 0-7, 0xFF means ANY role. */
725 * Per TID setting for allowing TX BA. Set a bit to 1 to allow
726 * TX BA sessions for the corresponding TID.
730 /* Windows size in number of packets */
735 /* As initiator inactivity timeout in time units(TU) of 1024us */
736 u16 inactivity_timeout;
741 struct wl1271_acx_ba_receiver_setup {
742 struct acx_header header;
744 /* Specifies link id, range 0-31 */
751 /* Windows size in number of packets */
754 /* BA session starting sequence number. RANGE 0-FFF */
760 struct wl12xx_acx_fw_tsf_information {
761 struct acx_header header;
765 __le32 current_tsf_high;
766 __le32 current_tsf_low;
767 __le32 last_bttt_high;
768 __le32 last_tbtt_low;
773 struct wl1271_acx_ps_rx_streaming {
774 struct acx_header header;
780 /* interval between triggers (10-100 msec) */
783 /* timeout before first trigger (0-200 msec) */
788 struct wl1271_acx_ap_max_tx_retry {
789 struct acx_header header;
795 * the number of frames transmission failures before
796 * issuing the aging event.
801 struct wl1271_acx_config_ps {
802 struct acx_header header;
807 __le32 null_data_rate;
810 struct wl1271_acx_inconnection_sta {
811 struct acx_header header;
820 * set the FM co-existence parameters.
822 struct wl1271_acx_fm_coex {
823 struct acx_header header;
824 /* enable(1) / disable(0) the FM Coex feature */
827 * Swallow period used in COEX PLL swallowing mechanism.
828 * 0xFF = use FW default
832 * The N divider used in COEX PLL swallowing mechanism for Fref of
833 * 38.4/19.2 Mhz. 0xFF = use FW default
835 u8 n_divider_fref_set_1;
837 * The N divider used in COEX PLL swallowing mechanism for Fref of
838 * 26/52 Mhz. 0xFF = use FW default
840 u8 n_divider_fref_set_2;
842 * The M divider used in COEX PLL swallowing mechanism for Fref of
843 * 38.4/19.2 Mhz. 0xFFFF = use FW default
845 __le16 m_divider_fref_set_1;
847 * The M divider used in COEX PLL swallowing mechanism for Fref of
848 * 26/52 Mhz. 0xFFFF = use FW default
850 __le16 m_divider_fref_set_2;
852 * The time duration in uSec required for COEX PLL to stabilize.
853 * 0xFFFFFFFF = use FW default
855 __le32 coex_pll_stabilization_time;
857 * The time duration in uSec required for LDO to stabilize.
858 * 0xFFFFFFFF = use FW default
860 __le16 ldo_stabilization_time;
862 * The disturbed frequency band margin around the disturbed frequency
863 * center (single sided).
864 * For example, if 2 is configured, the following channels will be
865 * considered disturbed channel:
866 * 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
867 * 0xFF = use FW default
869 u8 fm_disturbed_band_margin;
871 * The swallow clock difference of the swallowing mechanism.
872 * 0xFF = use FW default
877 #define ACX_RATE_MGMT_ALL_PARAMS 0xff
878 struct wl12xx_acx_set_rate_mgmt_params {
879 struct acx_header header;
881 u8 index; /* 0xff to configure all params */
883 __le16 rate_retry_score;
888 u8 inverse_curiosity_factor;
897 u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
901 struct wl12xx_acx_config_hangover {
902 struct acx_header header;
907 u8 early_termination_mode;
919 struct acx_default_rx_filter {
920 struct acx_header header;
923 /* action of type FILTER_XXX */
930 struct acx_rx_filter_cfg {
931 struct acx_header header;
935 /* 0 - WL1271_MAX_RX_FILTERS-1 */
944 struct acx_roaming_stats {
945 struct acx_header header;
957 ACX_WAKE_UP_CONDITIONS = 0x0000,
958 ACX_MEM_CFG = 0x0001,
961 ACX_MEM_MAP = 0x0004,
963 ACX_MEDIUM_USAGE = 0x0006,
964 ACX_STATISTICS = 0x0007,
965 ACX_PWR_CONSUMPTION_STATISTICS = 0x0008,
966 ACX_TID_CFG = 0x0009,
967 ACX_PS_RX_STREAMING = 0x000A,
968 ACX_BEACON_FILTER_OPT = 0x000B,
969 ACX_NOISE_HIST = 0x000C,
970 ACX_HDK_VERSION = 0x000D,
971 ACX_PD_THRESHOLD = 0x000E,
972 ACX_TX_CONFIG_OPT = 0x000F,
973 ACX_CCA_THRESHOLD = 0x0010,
974 ACX_EVENT_MBOX_MASK = 0x0011,
975 ACX_CONN_MONIT_PARAMS = 0x0012,
976 ACX_DISABLE_BROADCASTS = 0x0013,
977 ACX_BCN_DTIM_OPTIONS = 0x0014,
978 ACX_SG_ENABLE = 0x0015,
980 ACX_FM_COEX_CFG = 0x0017,
981 ACX_BEACON_FILTER_TABLE = 0x0018,
982 ACX_ARP_IP_FILTER = 0x0019,
983 ACX_ROAMING_STATISTICS_TBL = 0x001A,
984 ACX_RATE_POLICY = 0x001B,
985 ACX_CTS_PROTECTION = 0x001C,
986 ACX_SLEEP_AUTH = 0x001D,
987 ACX_PREAMBLE_TYPE = 0x001E,
988 ACX_ERROR_CNT = 0x001F,
989 ACX_IBSS_FILTER = 0x0020,
990 ACX_SERVICE_PERIOD_TIMEOUT = 0x0021,
991 ACX_TSF_INFO = 0x0022,
992 ACX_CONFIG_PS_WMM = 0x0023,
993 ACX_ENABLE_RX_DATA_FILTER = 0x0024,
994 ACX_SET_RX_DATA_FILTER = 0x0025,
995 ACX_GET_DATA_FILTER_STATISTICS = 0x0026,
996 ACX_RX_CONFIG_OPT = 0x0027,
997 ACX_FRAG_CFG = 0x0028,
998 ACX_BET_ENABLE = 0x0029,
999 ACX_RSSI_SNR_TRIGGER = 0x002A,
1000 ACX_RSSI_SNR_WEIGHTS = 0x002B,
1001 ACX_KEEP_ALIVE_MODE = 0x002C,
1002 ACX_SET_KEEP_ALIVE_CONFIG = 0x002D,
1003 ACX_BA_SESSION_INIT_POLICY = 0x002E,
1004 ACX_BA_SESSION_RX_SETUP = 0x002F,
1005 ACX_PEER_HT_CAP = 0x0030,
1006 ACX_HT_BSS_OPERATION = 0x0031,
1007 ACX_COEX_ACTIVITY = 0x0032,
1008 ACX_BURST_MODE = 0x0033,
1009 ACX_SET_RATE_MGMT_PARAMS = 0x0034,
1010 ACX_GET_RATE_MGMT_PARAMS = 0x0035,
1011 ACX_SET_RATE_ADAPT_PARAMS = 0x0036,
1012 ACX_SET_DCO_ITRIM_PARAMS = 0x0037,
1013 ACX_GEN_FW_CMD = 0x0038,
1014 ACX_HOST_IF_CFG_BITMAP = 0x0039,
1015 ACX_MAX_TX_FAILURE = 0x003A,
1016 ACX_UPDATE_INCONNECTION_STA_LIST = 0x003B,
1017 DOT11_RX_MSDU_LIFE_TIME = 0x003C,
1018 DOT11_CUR_TX_PWR = 0x003D,
1019 DOT11_RTS_THRESHOLD = 0x003E,
1020 DOT11_GROUP_ADDRESS_TBL = 0x003F,
1021 ACX_PM_CONFIG = 0x0040,
1022 ACX_CONFIG_PS = 0x0041,
1023 ACX_CONFIG_HANGOVER = 0x0042,
1024 ACX_FEATURE_CFG = 0x0043,
1025 ACX_PROTECTION_CFG = 0x0044,
1029 int wl1271_acx_wake_up_conditions(struct wl1271 *wl,
1030 struct wl12xx_vif *wlvif,
1031 u8 wake_up_event, u8 listen_interval);
1032 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1033 int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1035 int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1036 int wl1271_acx_mem_map(struct wl1271 *wl,
1037 struct acx_header *mem_map, size_t len);
1038 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1039 int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1040 enum acx_slot_type slot_time);
1041 int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1042 bool enable, void *mc_list, u32 mc_list_len);
1043 int wl1271_acx_service_period_timeout(struct wl1271 *wl,
1044 struct wl12xx_vif *wlvif);
1045 int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1047 int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1048 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1049 bool enable_filter);
1050 int wl1271_acx_beacon_filter_table(struct wl1271 *wl,
1051 struct wl12xx_vif *wlvif);
1052 int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1054 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1055 int wl12xx_acx_sg_cfg(struct wl1271 *wl);
1056 int wl1271_acx_cca_threshold(struct wl1271 *wl);
1057 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1058 int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid);
1059 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1060 int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1061 enum acx_preamble_type preamble);
1062 int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1063 enum acx_ctsprotect_type ctsprotect);
1064 int wl1271_acx_statistics(struct wl1271 *wl, void *stats);
1065 int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1066 int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
1068 int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1069 u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
1070 int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1071 u8 queue_id, u8 channel_type,
1072 u8 tsid, u8 ps_scheme, u8 ack_policy,
1073 u32 apsd_conf0, u32 apsd_conf1);
1074 int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1075 int wl1271_acx_tx_config_options(struct wl1271 *wl);
1076 int wl12xx_acx_mem_cfg(struct wl1271 *wl);
1077 int wl1271_acx_init_mem_config(struct wl1271 *wl);
1078 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1079 int wl1271_acx_smart_reflex(struct wl1271 *wl);
1080 int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1082 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1083 u8 enable, __be32 address);
1084 int wl1271_acx_pm_config(struct wl1271 *wl);
1085 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif,
1087 int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1088 u8 index, u8 tpl_valid);
1089 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1090 bool enable, s16 thold, u8 hyst);
1091 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl,
1092 struct wl12xx_vif *wlvif);
1093 int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
1094 struct ieee80211_sta_ht_cap *ht_cap,
1095 bool allow_ht_operation, u8 hlid);
1096 int wl1271_acx_set_ht_information(struct wl1271 *wl,
1097 struct wl12xx_vif *wlvif,
1098 u16 ht_operation_mode);
1099 int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl,
1100 struct wl12xx_vif *wlvif);
1101 int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index,
1102 u16 ssn, bool enable, u8 peer_hlid,
1104 int wl12xx_acx_tsf_info(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1106 int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1108 int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1109 int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1110 int wl1271_acx_set_inconnection_sta(struct wl1271 *wl,
1111 struct wl12xx_vif *wlvif, u8 *addr);
1112 int wl1271_acx_fm_coex(struct wl1271 *wl);
1113 int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl);
1114 int wl12xx_acx_config_hangover(struct wl1271 *wl);
1115 int wlcore_acx_average_rssi(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1118 int wl1271_acx_default_rx_filter_enable(struct wl1271 *wl, bool enable,
1119 enum rx_filter_action action);
1120 int wl1271_acx_set_rx_filter(struct wl1271 *wl, u8 index, bool enable,
1121 struct wl12xx_rx_filter *filter);
1122 #endif /* __WL1271_ACX_H__ */