drivers/net/wireless/ti/wl12xx/main.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24
  25 #include <linux/err.h>
  26
  27 #include "../wlcore/wlcore.h"
  28 #include "../wlcore/debug.h"
  29 #include "../wlcore/io.h"
  30 #include "../wlcore/acx.h"
  31 #include "../wlcore/tx.h"
  32 #include "../wlcore/rx.h"
  33 #include "../wlcore/boot.h"
  34
  35 #include "wl12xx.h"
  36 #include "reg.h"
  37 #include "cmd.h"
  38 #include "acx.h"
  39 #include "scan.h"
  40 #include "event.h"
  41 #include "debugfs.h"
  42
  43 static char *fref_param;
  44 static char *tcxo_param;
  45
  46 static struct wlcore_conf wl12xx_conf = {
  47         .sg = {
  48                 .params = {
  49                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  50                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  51                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  52                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  53                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  54                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  55                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  56                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  57                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  58                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  59                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  60                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  61                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  62                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  63                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  64                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  65                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  66                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  67                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  68                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  69                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  70                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  71                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  72                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  73                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  74                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  75                         /* active scan params */
  76                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  77                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  78                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  79                         /* passive scan params */
  80                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
  81                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
  82                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
  83                         /* passive scan in dual antenna params */
  84                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  85                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
  86                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
  87                         /* general params */
  88                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  89                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
  90                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
  91                         [CONF_SG_DHCP_TIME] = 5000,
  92                         [CONF_SG_RXT] = 1200,
  93                         [CONF_SG_TXT] = 1000,
  94                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  95                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  96                         [CONF_SG_HV3_MAX_SERVED] = 6,
  97                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
  98                         [CONF_SG_UPSD_TIMEOUT] = 10,
  99                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 100                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 101                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 102                         /* AP params */
 103                         [CONF_AP_BEACON_MISS_TX] = 3,
 104                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 105                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 106                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 107                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 108                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 109                         /* CTS Diluting params */
 110                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 111                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 112                 },
 113                 .state = CONF_SG_PROTECTIVE,
 114         },
 115         .rx = {
 116                 .rx_msdu_life_time           = 512000,
 117                 .packet_detection_threshold  = 0,
 118                 .ps_poll_timeout             = 15,
 119                 .upsd_timeout                = 15,
 120                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 121                 .rx_cca_threshold            = 0,
 122                 .irq_blk_threshold           = 0xFFFF,
 123                 .irq_pkt_threshold           = 0,
 124                 .irq_timeout                 = 600,
 125                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 126         },
 127         .tx = {
 128                 .tx_energy_detection         = 0,
 129                 .sta_rc_conf                 = {
 130                         .enabled_rates       = 0,
 131                         .short_retry_limit   = 10,
 132                         .long_retry_limit    = 10,
 133                         .aflags              = 0,
 134                 },
 135                 .ac_conf_count               = 4,
 136                 .ac_conf                     = {
 137                         [CONF_TX_AC_BE] = {
 138                                 .ac          = CONF_TX_AC_BE,
 139                                 .cw_min      = 15,
 140                                 .cw_max      = 63,
 141                                 .aifsn       = 3,
 142                                 .tx_op_limit = 0,
 143                         },
 144                         [CONF_TX_AC_BK] = {
 145                                 .ac          = CONF_TX_AC_BK,
 146                                 .cw_min      = 15,
 147                                 .cw_max      = 63,
 148                                 .aifsn       = 7,
 149                                 .tx_op_limit = 0,
 150                         },
 151                         [CONF_TX_AC_VI] = {
 152                                 .ac          = CONF_TX_AC_VI,
 153                                 .cw_min      = 15,
 154                                 .cw_max      = 63,
 155                                 .aifsn       = CONF_TX_AIFS_PIFS,
 156                                 .tx_op_limit = 3008,
 157                         },
 158                         [CONF_TX_AC_VO] = {
 159                                 .ac          = CONF_TX_AC_VO,
 160                                 .cw_min      = 15,
 161                                 .cw_max      = 63,
 162                                 .aifsn       = CONF_TX_AIFS_PIFS,
 163                                 .tx_op_limit = 1504,
 164                         },
 165                 },
 166                 .max_tx_retries = 100,
 167                 .ap_aging_period = 300,
 168                 .tid_conf_count = 4,
 169                 .tid_conf = {
 170                         [CONF_TX_AC_BE] = {
 171                                 .queue_id    = CONF_TX_AC_BE,
 172                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 173                                 .tsid        = CONF_TX_AC_BE,
 174                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 175                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 176                                 .apsd_conf   = {0, 0},
 177                         },
 178                         [CONF_TX_AC_BK] = {
 179                                 .queue_id    = CONF_TX_AC_BK,
 180                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 181                                 .tsid        = CONF_TX_AC_BK,
 182                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 183                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 184                                 .apsd_conf   = {0, 0},
 185                         },
 186                         [CONF_TX_AC_VI] = {
 187                                 .queue_id    = CONF_TX_AC_VI,
 188                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 189                                 .tsid        = CONF_TX_AC_VI,
 190                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 191                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 192                                 .apsd_conf   = {0, 0},
 193                         },
 194                         [CONF_TX_AC_VO] = {
 195                                 .queue_id    = CONF_TX_AC_VO,
 196                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 197                                 .tsid        = CONF_TX_AC_VO,
 198                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 199                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 200                                 .apsd_conf   = {0, 0},
 201                         },
 202                 },
 203                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 204                 .tx_compl_timeout            = 700,
 205                 .tx_compl_threshold          = 4,
 206                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 207                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 208                 .tmpl_short_retry_limit      = 10,
 209                 .tmpl_long_retry_limit       = 10,
 210                 .tx_watchdog_timeout         = 5000,
 211                 .slow_link_thold             = 3,
 212                 .fast_link_thold             = 10,
 213         },
 214         .conn = {
 215                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 216                 .listen_interval             = 1,
 217                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 218                 .suspend_listen_interval     = 3,
 219                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 220                 .bcn_filt_ie_count           = 3,
 221                 .bcn_filt_ie = {
 222                         [0] = {
 223                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 224                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 225                         },
 226                         [1] = {
 227                                 .ie          = WLAN_EID_HT_OPERATION,
 228                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 229                         },
 230                         [2] = {
 231                                 .ie          = WLAN_EID_ERP_INFO,
 232                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 233                         },
 234                 },
 235                 .synch_fail_thold            = 12,
 236                 .bss_lose_timeout            = 400,
 237                 .beacon_rx_timeout           = 10000,
 238                 .broadcast_timeout           = 20000,
 239                 .rx_broadcast_in_ps          = 1,
 240                 .ps_poll_threshold           = 10,
 241                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 242                 .bet_max_consecutive         = 50,
 243                 .psm_entry_retries           = 8,
 244                 .psm_exit_retries            = 16,
 245                 .psm_entry_nullfunc_retries  = 3,
 246                 .dynamic_ps_timeout          = 1500,
 247                 .forced_ps                   = false,
 248                 .keep_alive_interval         = 55000,
 249                 .max_listen_interval         = 20,
 250                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 251                 .suspend_rx_ba_activity      = 0,
 252         },
 253         .itrim = {
 254                 .enable = false,
 255                 .timeout = 50000,
 256         },
 257         .pm_config = {
 258                 .host_clk_settling_time = 5000,
 259                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 260         },
 261         .roam_trigger = {
 262                 .trigger_pacing               = 1,
 263                 .avg_weight_rssi_beacon       = 20,
 264                 .avg_weight_rssi_data         = 10,
 265                 .avg_weight_snr_beacon        = 20,
 266                 .avg_weight_snr_data          = 10,
 267         },
 268         .scan = {
 269                 .min_dwell_time_active        = 7500,
 270                 .max_dwell_time_active        = 30000,
 271                 .min_dwell_time_active_long   = 25000,
 272                 .max_dwell_time_active_long   = 50000,
 273                 .dwell_time_passive           = 100000,
 274                 .dwell_time_dfs               = 150000,
 275                 .num_probe_reqs               = 2,
 276                 .split_scan_timeout           = 50000,
 277         },
 278         .sched_scan = {
 279                 /*
 280                  * Values are in TU/1000 but since sched scan FW command
 281                  * params are in TUs rounding up may occur.
 282                  */
 283                 .base_dwell_time                = 7500,
 284                 .max_dwell_time_delta           = 22500,
 285                 /* based on 250bits per probe @1Mbps */
 286                 .dwell_time_delta_per_probe     = 2000,
 287                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 288                 .dwell_time_delta_per_probe_5   = 350,
 289                 .dwell_time_passive             = 100000,
 290                 .dwell_time_dfs                 = 150000,
 291                 .num_probe_reqs                 = 2,
 292                 .rssi_threshold                 = -90,
 293                 .snr_threshold                  = 0,
 294         },
 295         .ht = {
 296                 .rx_ba_win_size = 8,
 297                 .tx_ba_win_size = 64,
 298                 .inactivity_timeout = 10000,
 299                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 300         },
 301         /*
 302          * Memory config for wl127x chips is given in the
 303          * wl12xx_default_priv_conf struct. The below configuration is
 304          * for wl128x chips.
 305          */
 306         .mem = {
 307                 .num_stations                 = 1,
 308                 .ssid_profiles                = 1,
 309                 .rx_block_num                 = 40,
 310                 .tx_min_block_num             = 40,
 311                 .dynamic_memory               = 1,
 312                 .min_req_tx_blocks            = 45,
 313                 .min_req_rx_blocks            = 22,
 314                 .tx_min                       = 27,
 315         },
 316         .fm_coex = {
 317                 .enable                       = true,
 318                 .swallow_period               = 5,
 319                 .n_divider_fref_set_1         = 0xff,       /* default */
 320                 .n_divider_fref_set_2         = 12,
 321                 .m_divider_fref_set_1         = 0xffff,
 322                 .m_divider_fref_set_2         = 148,        /* default */
 323                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 324                 .ldo_stabilization_time       = 0xffff,     /* default */
 325                 .fm_disturbed_band_margin     = 0xff,       /* default */
 326                 .swallow_clk_diff             = 0xff,       /* default */
 327         },
 328         .rx_streaming = {
 329                 .duration                      = 150,
 330                 .queues                        = 0x1,
 331                 .interval                      = 20,
 332                 .always                        = 0,
 333         },
 334         .fwlog = {
 335                 .mode                         = WL12XX_FWLOG_CONTINUOUS,
 336                 .mem_blocks                   = 2,
 337                 .severity                     = 0,
 338                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 339                 .output                       = WL12XX_FWLOG_OUTPUT_DBG_PINS,
 340                 .threshold                    = 0,
 341         },
 342         .rate = {
 343                 .rate_retry_score = 32000,
 344                 .per_add = 8192,
 345                 .per_th1 = 2048,
 346                 .per_th2 = 4096,
 347                 .max_per = 8100,
 348                 .inverse_curiosity_factor = 5,
 349                 .tx_fail_low_th = 4,
 350                 .tx_fail_high_th = 10,
 351                 .per_alpha_shift = 4,
 352                 .per_add_shift = 13,
 353                 .per_beta1_shift = 10,
 354                 .per_beta2_shift = 8,
 355                 .rate_check_up = 2,
 356                 .rate_check_down = 12,
 357                 .rate_retry_policy = {
 358                         0x00, 0x00, 0x00, 0x00, 0x00,
 359                         0x00, 0x00, 0x00, 0x00, 0x00,
 360                         0x00, 0x00, 0x00,
 361                 },
 362         },
 363         .hangover = {
 364                 .recover_time               = 0,
 365                 .hangover_period            = 20,
 366                 .dynamic_mode               = 1,
 367                 .early_termination_mode     = 1,
 368                 .max_period                 = 20,
 369                 .min_period                 = 1,
 370                 .increase_delta             = 1,
 371                 .decrease_delta             = 2,
 372                 .quiet_time                 = 4,
 373                 .increase_time              = 1,
 374                 .window_size                = 16,
 375         },
 376         .recovery = {
 377                 .bug_on_recovery            = 0,
 378                 .no_recovery                = 0,
 379         },
 380 };
 381
 382 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
 383         .rf = {
 384                 .tx_per_channel_power_compensation_2 = {
 385                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 386                 },
 387                 .tx_per_channel_power_compensation_5 = {
 388                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 389                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 390                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 391                 },
 392         },
 393         .mem_wl127x = {
 394                 .num_stations                 = 1,
 395                 .ssid_profiles                = 1,
 396                 .rx_block_num                 = 70,
 397                 .tx_min_block_num             = 40,
 398                 .dynamic_memory               = 1,
 399                 .min_req_tx_blocks            = 100,
 400                 .min_req_rx_blocks            = 22,
 401                 .tx_min                       = 27,
 402         },
 403
 404 };
 405
 406 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT        1
 407 #define WL12XX_TX_HW_BLOCK_GEM_SPARE            2
 408 #define WL12XX_TX_HW_BLOCK_SIZE                 252
 409
 410 static const u8 wl12xx_rate_to_idx_2ghz[] = {
 411         /* MCS rates are used only with 11n */
 412         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 413         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 414         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 415         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 416         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 417         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 418         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 419         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 420         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 421
 422         11,                            /* WL12XX_CONF_HW_RXTX_RATE_54   */
 423         10,                            /* WL12XX_CONF_HW_RXTX_RATE_48   */
 424         9,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 425         8,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 426
 427         /* TI-specific rate */
 428         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 429
 430         7,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 431         6,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 432         3,                             /* WL12XX_CONF_HW_RXTX_RATE_11   */
 433         5,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 434         4,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 435         2,                             /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 436         1,                             /* WL12XX_CONF_HW_RXTX_RATE_2    */
 437         0                              /* WL12XX_CONF_HW_RXTX_RATE_1    */
 438 };
 439
 440 static const u8 wl12xx_rate_to_idx_5ghz[] = {
 441         /* MCS rates are used only with 11n */
 442         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 443         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 444         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 445         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 446         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 447         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 448         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 449         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 450         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 451
 452         7,                             /* WL12XX_CONF_HW_RXTX_RATE_54   */
 453         6,                             /* WL12XX_CONF_HW_RXTX_RATE_48   */
 454         5,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 455         4,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 456
 457         /* TI-specific rate */
 458         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 459
 460         3,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 461         2,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 462         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11   */
 463         1,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 464         0,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 465         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 466         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2    */
 467         CONF_HW_RXTX_RATE_UNSUPPORTED  /* WL12XX_CONF_HW_RXTX_RATE_1    */
 468 };
 469
 470 static const u8 *wl12xx_band_rate_to_idx[] = {
 471         [IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
 472         [IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
 473 };
 474
 475 enum wl12xx_hw_rates {
 476         WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
 477         WL12XX_CONF_HW_RXTX_RATE_MCS7,
 478         WL12XX_CONF_HW_RXTX_RATE_MCS6,
 479         WL12XX_CONF_HW_RXTX_RATE_MCS5,
 480         WL12XX_CONF_HW_RXTX_RATE_MCS4,
 481         WL12XX_CONF_HW_RXTX_RATE_MCS3,
 482         WL12XX_CONF_HW_RXTX_RATE_MCS2,
 483         WL12XX_CONF_HW_RXTX_RATE_MCS1,
 484         WL12XX_CONF_HW_RXTX_RATE_MCS0,
 485         WL12XX_CONF_HW_RXTX_RATE_54,
 486         WL12XX_CONF_HW_RXTX_RATE_48,
 487         WL12XX_CONF_HW_RXTX_RATE_36,
 488         WL12XX_CONF_HW_RXTX_RATE_24,
 489         WL12XX_CONF_HW_RXTX_RATE_22,
 490         WL12XX_CONF_HW_RXTX_RATE_18,
 491         WL12XX_CONF_HW_RXTX_RATE_12,
 492         WL12XX_CONF_HW_RXTX_RATE_11,
 493         WL12XX_CONF_HW_RXTX_RATE_9,
 494         WL12XX_CONF_HW_RXTX_RATE_6,
 495         WL12XX_CONF_HW_RXTX_RATE_5_5,
 496         WL12XX_CONF_HW_RXTX_RATE_2,
 497         WL12XX_CONF_HW_RXTX_RATE_1,
 498         WL12XX_CONF_HW_RXTX_RATE_MAX,
 499 };
 500
 501 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
 502         [PART_DOWN] = {
 503                 .mem = {
 504                         .start = 0x00000000,
 505                         .size  = 0x000177c0
 506                 },
 507                 .reg = {
 508                         .start = REGISTERS_BASE,
 509                         .size  = 0x00008800
 510                 },
 511                 .mem2 = {
 512                         .start = 0x00000000,
 513                         .size  = 0x00000000
 514                 },
 515                 .mem3 = {
 516                         .start = 0x00000000,
 517                         .size  = 0x00000000
 518                 },
 519         },
 520
 521         [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
 522                          * partition here */
 523                 .mem = {
 524                         .start = 0x00040000,
 525                         .size  = 0x00014fc0
 526                 },
 527                 .reg = {
 528                         .start = REGISTERS_BASE,
 529                         .size  = 0x00008800
 530                 },
 531                 .mem2 = {
 532                         .start = 0x00000000,
 533                         .size  = 0x00000000
 534                 },
 535                 .mem3 = {
 536                         .start = 0x00000000,
 537                         .size  = 0x00000000
 538                 },
 539         },
 540
 541         [PART_WORK] = {
 542                 .mem = {
 543                         .start = 0x00040000,
 544                         .size  = 0x00014fc0
 545                 },
 546                 .reg = {
 547                         .start = REGISTERS_BASE,
 548                         .size  = 0x0000a000
 549                 },
 550                 .mem2 = {
 551                         .start = 0x003004f8,
 552                         .size  = 0x00000004
 553                 },
 554                 .mem3 = {
 555                         .start = 0x00040404,
 556                         .size  = 0x00000000
 557                 },
 558         },
 559
 560         [PART_DRPW] = {
 561                 .mem = {
 562                         .start = 0x00040000,
 563                         .size  = 0x00014fc0
 564                 },
 565                 .reg = {
 566                         .start = DRPW_BASE,
 567                         .size  = 0x00006000
 568                 },
 569                 .mem2 = {
 570                         .start = 0x00000000,
 571                         .size  = 0x00000000
 572                 },
 573                 .mem3 = {
 574                         .start = 0x00000000,
 575                         .size  = 0x00000000
 576                 }
 577         }
 578 };
 579
 580 static const int wl12xx_rtable[REG_TABLE_LEN] = {
 581         [REG_ECPU_CONTROL]              = WL12XX_REG_ECPU_CONTROL,
 582         [REG_INTERRUPT_NO_CLEAR]        = WL12XX_REG_INTERRUPT_NO_CLEAR,
 583         [REG_INTERRUPT_ACK]             = WL12XX_REG_INTERRUPT_ACK,
 584         [REG_COMMAND_MAILBOX_PTR]       = WL12XX_REG_COMMAND_MAILBOX_PTR,
 585         [REG_EVENT_MAILBOX_PTR]         = WL12XX_REG_EVENT_MAILBOX_PTR,
 586         [REG_INTERRUPT_TRIG]            = WL12XX_REG_INTERRUPT_TRIG,
 587         [REG_INTERRUPT_MASK]            = WL12XX_REG_INTERRUPT_MASK,
 588         [REG_PC_ON_RECOVERY]            = WL12XX_SCR_PAD4,
 589         [REG_CHIP_ID_B]                 = WL12XX_CHIP_ID_B,
 590         [REG_CMD_MBOX_ADDRESS]          = WL12XX_CMD_MBOX_ADDRESS,
 591
 592         /* data access memory addresses, used with partition translation */
 593         [REG_SLV_MEM_DATA]              = WL1271_SLV_MEM_DATA,
 594         [REG_SLV_REG_DATA]              = WL1271_SLV_REG_DATA,
 595
 596         /* raw data access memory addresses */
 597         [REG_RAW_FW_STATUS_ADDR]        = FW_STATUS_ADDR,
 598 };
 599
 600 /* TODO: maybe move to a new header file? */
 601 #define WL127X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 602 #define WL127X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 603 #define WL127X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 604
 605 #define WL128X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 606 #define WL128X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 607 #define WL128X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 608
 609 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
 610 {
 611         int ret;
 612
 613         if (wl->chip.id != CHIP_ID_128X_PG20) {
 614                 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
 615                 struct wl12xx_priv *priv = wl->priv;
 616
 617                 /*
 618                  * Choose the block we want to read
 619                  * For aggregated packets, only the first memory block
 620                  * should be retrieved. The FW takes care of the rest.
 621                  */
 622                 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
 623
 624                 priv->rx_mem_addr->addr = (mem_block << 8) +
 625                         le32_to_cpu(wl_mem_map->packet_memory_pool_start);
 626
 627                 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
 628
 629                 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
 630                                    sizeof(*priv->rx_mem_addr), false);
 631                 if (ret < 0)
 632                         return ret;
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int wl12xx_identify_chip(struct wl1271 *wl)
 639 {
 640         int ret = 0;
 641
 642         switch (wl->chip.id) {
 643         case CHIP_ID_127X_PG10:
 644                 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
 645                                wl->chip.id);
 646
 647                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 648                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 649                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 650                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 651                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 652                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 653                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 654                        sizeof(wl->conf.mem));
 655
 656                 /* read data preparation is only needed by wl127x */
 657                 wl->ops->prepare_read = wl127x_prepare_read;
 658
 659                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 660                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 661                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 662                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 663                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 664                 break;
 665
 666         case CHIP_ID_127X_PG20:
 667                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
 668                              wl->chip.id);
 669
 670                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 671                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 672                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 673                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 674                 wl->plt_fw_name = WL127X_PLT_FW_NAME;
 675                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 676                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 677                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 678                        sizeof(wl->conf.mem));
 679
 680                 /* read data preparation is only needed by wl127x */
 681                 wl->ops->prepare_read = wl127x_prepare_read;
 682
 683                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 684                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 685                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 686                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 687                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 688                 break;
 689
 690         case CHIP_ID_128X_PG20:
 691                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
 692                              wl->chip.id);
 693                 wl->plt_fw_name = WL128X_PLT_FW_NAME;
 694                 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
 695                 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
 696
 697                 /* wl128x requires TX blocksize alignment */
 698                 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 699                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 700                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 701                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 702
 703                 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
 704                               WL128X_IFTYPE_SR_VER,  WL128X_MAJOR_SR_VER,
 705                               WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
 706                               WL128X_IFTYPE_MR_VER,  WL128X_MAJOR_MR_VER,
 707                               WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
 708                 break;
 709         case CHIP_ID_128X_PG10:
 710         default:
 711                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 712                 ret = -ENODEV;
 713                 goto out;
 714         }
 715
 716         wl->fw_mem_block_size = 256;
 717         wl->fwlog_end = 0x2000000;
 718
 719         /* common settings */
 720         wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
 721         wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
 722         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 723         wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 724         wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
 725         wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
 726 out:
 727         return ret;
 728 }
 729
 730 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
 731                                              u16 val)
 732 {
 733         int ret;
 734
 735         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 736         addr = (addr >> 1) + 0x30000;
 737         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 738         if (ret < 0)
 739                 goto out;
 740
 741         /* write value to OCP_POR_WDATA */
 742         ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
 743         if (ret < 0)
 744                 goto out;
 745
 746         /* write 1 to OCP_CMD */
 747         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
 748         if (ret < 0)
 749                 goto out;
 750
 751 out:
 752         return ret;
 753 }
 754
 755 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
 756                                             u16 *out)
 757 {
 758         u32 val;
 759         int timeout = OCP_CMD_LOOP;
 760         int ret;
 761
 762         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 763         addr = (addr >> 1) + 0x30000;
 764         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 765         if (ret < 0)
 766                 return ret;
 767
 768         /* write 2 to OCP_CMD */
 769         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
 770         if (ret < 0)
 771                 return ret;
 772
 773         /* poll for data ready */
 774         do {
 775                 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
 776                 if (ret < 0)
 777                         return ret;
 778         } while (!(val & OCP_READY_MASK) && --timeout);
 779
 780         if (!timeout) {
 781                 wl1271_warning("Top register access timed out.");
 782                 return -ETIMEDOUT;
 783         }
 784
 785         /* check data status and return if OK */
 786         if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
 787                 wl1271_warning("Top register access returned error.");
 788                 return -EIO;
 789         }
 790
 791         if (out)
 792                 *out = val & 0xffff;
 793
 794         return 0;
 795 }
 796
 797 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 798 {
 799         u16 spare_reg;
 800         int ret;
 801
 802         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 803         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 804         if (ret < 0)
 805                 return ret;
 806
 807         if (spare_reg == 0xFFFF)
 808                 return -EFAULT;
 809         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 810         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 811         if (ret < 0)
 812                 return ret;
 813
 814         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 815         ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
 816                                    WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 817         if (ret < 0)
 818                 return ret;
 819
 820         /* Delay execution for 15msec, to let the HW settle */
 821         mdelay(15);
 822
 823         return 0;
 824 }
 825
 826 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 827 {
 828         u16 tcxo_detection;
 829         int ret;
 830
 831         ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
 832         if (ret < 0)
 833                 return false;
 834
 835         if (tcxo_detection & TCXO_DET_FAILED)
 836                 return false;
 837
 838         return true;
 839 }
 840
 841 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 842 {
 843         u16 fref_detection;
 844         int ret;
 845
 846         ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
 847         if (ret < 0)
 848                 return false;
 849
 850         if (fref_detection & FREF_CLK_DETECT_FAIL)
 851                 return false;
 852
 853         return true;
 854 }
 855
 856 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 857 {
 858         int ret;
 859
 860         ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 861         if (ret < 0)
 862                 goto out;
 863
 864         ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 865         if (ret < 0)
 866                 goto out;
 867
 868         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 869                                    MCS_PLL_CONFIG_REG_VAL);
 870
 871 out:
 872         return ret;
 873 }
 874
 875 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 876 {
 877         u16 spare_reg;
 878         u16 pll_config;
 879         u8 input_freq;
 880         struct wl12xx_priv *priv = wl->priv;
 881         int ret;
 882
 883         /* Mask bits [3:1] in the sys_clk_cfg register */
 884         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 885         if (ret < 0)
 886                 return ret;
 887
 888         if (spare_reg == 0xFFFF)
 889                 return -EFAULT;
 890         spare_reg |= BIT(2);
 891         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 892         if (ret < 0)
 893                 return ret;
 894
 895         /* Handle special cases of the TCXO clock */
 896         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 897             priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 898                 return wl128x_manually_configure_mcs_pll(wl);
 899
 900         /* Set the input frequency according to the selected clock source */
 901         input_freq = (clk & 1) + 1;
 902
 903         ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
 904         if (ret < 0)
 905                 return ret;
 906
 907         if (pll_config == 0xFFFF)
 908                 return -EFAULT;
 909         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 910         pll_config |= MCS_PLL_ENABLE_HP;
 911         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 912
 913         return ret;
 914 }
 915
 916 /*
 917  * WL128x has two clocks input - TCXO and FREF.
 918  * TCXO is the main clock of the device, while FREF is used to sync
 919  * between the GPS and the cellular modem.
 920  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 921  * as the WLAN/BT main clock.
 922  */
 923 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 924 {
 925         struct wl12xx_priv *priv = wl->priv;
 926         u16 sys_clk_cfg;
 927         int ret;
 928
 929         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 930         if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 931             priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 932                 if (!wl128x_switch_tcxo_to_fref(wl))
 933                         return -EINVAL;
 934                 goto fref_clk;
 935         }
 936
 937         /* Query the HW, to determine which clock source we should use */
 938         ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
 939         if (ret < 0)
 940                 return ret;
 941
 942         if (sys_clk_cfg == 0xFFFF)
 943                 return -EINVAL;
 944         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 945                 goto fref_clk;
 946
 947         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 948         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 949             priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 950                 if (!wl128x_switch_tcxo_to_fref(wl))
 951                         return -EINVAL;
 952                 goto fref_clk;
 953         }
 954
 955         /* TCXO clock is selected */
 956         if (!wl128x_is_tcxo_valid(wl))
 957                 return -EINVAL;
 958         *selected_clock = priv->tcxo_clock;
 959         goto config_mcs_pll;
 960
 961 fref_clk:
 962         /* FREF clock is selected */
 963         if (!wl128x_is_fref_valid(wl))
 964                 return -EINVAL;
 965         *selected_clock = priv->ref_clock;
 966
 967 config_mcs_pll:
 968         return wl128x_configure_mcs_pll(wl, *selected_clock);
 969 }
 970
 971 static int wl127x_boot_clk(struct wl1271 *wl)
 972 {
 973         struct wl12xx_priv *priv = wl->priv;
 974         u32 pause;
 975         u32 clk;
 976         int ret;
 977
 978         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 979                 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
 980
 981         if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
 982             priv->ref_clock == CONF_REF_CLK_38_4_E ||
 983             priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 984                 /* ref clk: 19.2/38.4/38.4-XTAL */
 985                 clk = 0x3;
 986         else if (priv->ref_clock == CONF_REF_CLK_26_E ||
 987                  priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
 988                  priv->ref_clock == CONF_REF_CLK_52_E)
 989                 /* ref clk: 26/52 */
 990                 clk = 0x5;
 991         else
 992                 return -EINVAL;
 993
 994         if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
 995                 u16 val;
 996                 /* Set clock type (open drain) */
 997                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
 998                 if (ret < 0)
 999                         goto out;
1000
1001                 val &= FREF_CLK_TYPE_BITS;
1002                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
1003                 if (ret < 0)
1004                         goto out;
1005
1006                 /* Set clock pull mode (no pull) */
1007                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
1008                 if (ret < 0)
1009                         goto out;
1010
1011                 val |= NO_PULL;
1012                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1013                 if (ret < 0)
1014                         goto out;
1015         } else {
1016                 u16 val;
1017                 /* Set clock polarity */
1018                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1019                 if (ret < 0)
1020                         goto out;
1021
1022                 val &= FREF_CLK_POLARITY_BITS;
1023                 val |= CLK_REQ_OUTN_SEL;
1024                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1025                 if (ret < 0)
1026                         goto out;
1027         }
1028
1029         ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1030         if (ret < 0)
1031                 goto out;
1032
1033         ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1034         if (ret < 0)
1035                 goto out;
1036
1037         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1038
1039         pause &= ~(WU_COUNTER_PAUSE_VAL);
1040         pause |= WU_COUNTER_PAUSE_VAL;
1041         ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1042
1043 out:
1044         return ret;
1045 }
1046
1047 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1048 {
1049         unsigned long timeout;
1050         u32 boot_data;
1051         int ret = 0;
1052
1053         /* perform soft reset */
1054         ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1055         if (ret < 0)
1056                 goto out;
1057
1058         /* SOFT_RESET is self clearing */
1059         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1060         while (1) {
1061                 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1062                 if (ret < 0)
1063                         goto out;
1064
1065                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1066                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1067                         break;
1068
1069                 if (time_after(jiffies, timeout)) {
1070                         /* 1.2 check pWhalBus->uSelfClearTime if the
1071                          * timeout was reached */
1072                         wl1271_error("soft reset timeout");
1073                         return -1;
1074                 }
1075
1076                 udelay(SOFT_RESET_STALL_TIME);
1077         }
1078
1079         /* disable Rx/Tx */
1080         ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1081         if (ret < 0)
1082                 goto out;
1083
1084         /* disable auto calibration on start*/
1085         ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1086
1087 out:
1088         return ret;
1089 }
1090
1091 static int wl12xx_pre_boot(struct wl1271 *wl)
1092 {
1093         struct wl12xx_priv *priv = wl->priv;
1094         int ret = 0;
1095         u32 clk;
1096         int selected_clock = -1;
1097
1098         if (wl->chip.id == CHIP_ID_128X_PG20) {
1099                 ret = wl128x_boot_clk(wl, &selected_clock);
1100                 if (ret < 0)
1101                         goto out;
1102         } else {
1103                 ret = wl127x_boot_clk(wl);
1104                 if (ret < 0)
1105                         goto out;
1106         }
1107
1108         /* Continue the ELP wake up sequence */
1109         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1110         if (ret < 0)
1111                 goto out;
1112
1113         udelay(500);
1114
1115         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1116         if (ret < 0)
1117                 goto out;
1118
1119         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1120            to be used by DRPw FW. The RTRIM value will be added by the FW
1121            before taking DRPw out of reset */
1122
1123         ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1124         if (ret < 0)
1125                 goto out;
1126
1127         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1128
1129         if (wl->chip.id == CHIP_ID_128X_PG20)
1130                 clk |= ((selected_clock & 0x3) << 1) << 4;
1131         else
1132                 clk |= (priv->ref_clock << 1) << 4;
1133
1134         ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1135         if (ret < 0)
1136                 goto out;
1137
1138         ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1139         if (ret < 0)
1140                 goto out;
1141
1142         /* Disable interrupts */
1143         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1144         if (ret < 0)
1145                 goto out;
1146
1147         ret = wl1271_boot_soft_reset(wl);
1148         if (ret < 0)
1149                 goto out;
1150
1151 out:
1152         return ret;
1153 }
1154
1155 static int wl12xx_pre_upload(struct wl1271 *wl)
1156 {
1157         u32 tmp;
1158         u16 polarity;
1159         int ret;
1160
1161         /* write firmware's last address (ie. it's length) to
1162          * ACX_EEPROMLESS_IND_REG */
1163         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1164
1165         ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1166         if (ret < 0)
1167                 goto out;
1168
1169         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1170         if (ret < 0)
1171                 goto out;
1172
1173         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1174
1175         /* 6. read the EEPROM parameters */
1176         ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1177         if (ret < 0)
1178                 goto out;
1179
1180         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1181          * to upload_fw) */
1182
1183         if (wl->chip.id == CHIP_ID_128X_PG20) {
1184                 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1185                 if (ret < 0)
1186                         goto out;
1187         }
1188
1189         /* polarity must be set before the firmware is loaded */
1190         ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1191         if (ret < 0)
1192                 goto out;
1193
1194         /* We use HIGH polarity, so unset the LOW bit */
1195         polarity &= ~POLARITY_LOW;
1196         ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1197
1198 out:
1199         return ret;
1200 }
1201
1202 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1203 {
1204         int ret;
1205
1206         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1207                                WL12XX_ACX_ALL_EVENTS_VECTOR);
1208         if (ret < 0)
1209                 goto out;
1210
1211         wlcore_enable_interrupts(wl);
1212         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1213                                WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1214         if (ret < 0)
1215                 goto disable_interrupts;
1216
1217         ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1218         if (ret < 0)
1219                 goto disable_interrupts;
1220
1221         return ret;
1222
1223 disable_interrupts:
1224         wlcore_disable_interrupts(wl);
1225
1226 out:
1227         return ret;
1228 }
1229
1230 static int wl12xx_boot(struct wl1271 *wl)
1231 {
1232         int ret;
1233
1234         ret = wl12xx_pre_boot(wl);
1235         if (ret < 0)
1236                 goto out;
1237
1238         ret = wlcore_boot_upload_nvs(wl);
1239         if (ret < 0)
1240                 goto out;
1241
1242         ret = wl12xx_pre_upload(wl);
1243         if (ret < 0)
1244                 goto out;
1245
1246         ret = wlcore_boot_upload_firmware(wl);
1247         if (ret < 0)
1248                 goto out;
1249
1250         wl->event_mask = BSS_LOSE_EVENT_ID |
1251                 REGAINED_BSS_EVENT_ID |
1252                 SCAN_COMPLETE_EVENT_ID |
1253                 ROLE_STOP_COMPLETE_EVENT_ID |
1254                 RSSI_SNR_TRIGGER_0_EVENT_ID |
1255                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1256                 SOFT_GEMINI_SENSE_EVENT_ID |
1257                 PERIODIC_SCAN_REPORT_EVENT_ID |
1258                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1259                 DUMMY_PACKET_EVENT_ID |
1260                 PEER_REMOVE_COMPLETE_EVENT_ID |
1261                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1262                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1263                 INACTIVE_STA_EVENT_ID |
1264                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1265
1266         wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1267
1268         ret = wlcore_boot_run_firmware(wl);
1269         if (ret < 0)
1270                 goto out;
1271
1272         ret = wl12xx_enable_interrupts(wl);
1273
1274 out:
1275         return ret;
1276 }
1277
1278 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1279                                void *buf, size_t len)
1280 {
1281         int ret;
1282
1283         ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1284         if (ret < 0)
1285                 return ret;
1286
1287         ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1288
1289         return ret;
1290 }
1291
1292 static int wl12xx_ack_event(struct wl1271 *wl)
1293 {
1294         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1295                                 WL12XX_INTR_TRIG_EVENT_ACK);
1296 }
1297
1298 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1299 {
1300         u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1301         u32 align_len = wlcore_calc_packet_alignment(wl, len);
1302
1303         return (align_len + blk_size - 1) / blk_size + spare_blks;
1304 }
1305
1306 static void
1307 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1308                           u32 blks, u32 spare_blks)
1309 {
1310         if (wl->chip.id == CHIP_ID_128X_PG20) {
1311                 desc->wl128x_mem.total_mem_blocks = blks;
1312         } else {
1313                 desc->wl127x_mem.extra_blocks = spare_blks;
1314                 desc->wl127x_mem.total_mem_blocks = blks;
1315         }
1316 }
1317
1318 static void
1319 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1320                             struct sk_buff *skb)
1321 {
1322         u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1323
1324         if (wl->chip.id == CHIP_ID_128X_PG20) {
1325                 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1326                 desc->length = cpu_to_le16(aligned_len >> 2);
1327
1328                 wl1271_debug(DEBUG_TX,
1329                              "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1330                              desc->hlid,
1331                              le16_to_cpu(desc->length),
1332                              le16_to_cpu(desc->life_time),
1333                              desc->wl128x_mem.total_mem_blocks,
1334                              desc->wl128x_mem.extra_bytes);
1335         } else {
1336                 /* calculate number of padding bytes */
1337                 int pad = aligned_len - skb->len;
1338                 desc->tx_attr |=
1339                         cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1340
1341                 /* Store the aligned length in terms of words */
1342                 desc->length = cpu_to_le16(aligned_len >> 2);
1343
1344                 wl1271_debug(DEBUG_TX,
1345                              "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1346                              pad, desc->hlid,
1347                              le16_to_cpu(desc->length),
1348                              le16_to_cpu(desc->life_time),
1349                              desc->wl127x_mem.total_mem_blocks);
1350         }
1351 }
1352
1353 static enum wl_rx_buf_align
1354 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1355 {
1356         if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1357                 return WLCORE_RX_BUF_UNALIGNED;
1358
1359         return WLCORE_RX_BUF_ALIGNED;
1360 }
1361
1362 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1363                                     u32 data_len)
1364 {
1365         struct wl1271_rx_descriptor *desc = rx_data;
1366
1367         /* invalid packet */
1368         if (data_len < sizeof(*desc) ||
1369             data_len < sizeof(*desc) + desc->pad_len)
1370                 return 0;
1371
1372         return data_len - sizeof(*desc) - desc->pad_len;
1373 }
1374
1375 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1376 {
1377         if (wl->fw_status->tx_results_counter ==
1378             (wl->tx_results_count & 0xff))
1379                 return 0;
1380
1381         return wlcore_tx_complete(wl);
1382 }
1383
1384 static int wl12xx_hw_init(struct wl1271 *wl)
1385 {
1386         int ret;
1387
1388         if (wl->chip.id == CHIP_ID_128X_PG20) {
1389                 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1390
1391                 ret = wl128x_cmd_general_parms(wl);
1392                 if (ret < 0)
1393                         goto out;
1394
1395                 /*
1396                  * If we are in calibrator based auto detect then we got the FEM nr
1397                  * in wl->fem_manuf. No need to continue further
1398                  */
1399                 if (wl->plt_mode == PLT_FEM_DETECT)
1400                         goto out;
1401
1402                 ret = wl128x_cmd_radio_parms(wl);
1403                 if (ret < 0)
1404                         goto out;
1405
1406                 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1407                         /* Enable SDIO padding */
1408                         host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1409
1410                 /* Must be before wl1271_acx_init_mem_config() */
1411                 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1412                 if (ret < 0)
1413                         goto out;
1414         } else {
1415                 ret = wl1271_cmd_general_parms(wl);
1416                 if (ret < 0)
1417                         goto out;
1418
1419                 /*
1420                  * If we are in calibrator based auto detect then we got the FEM nr
1421                  * in wl->fem_manuf. No need to continue further
1422                  */
1423                 if (wl->plt_mode == PLT_FEM_DETECT)
1424                         goto out;
1425
1426                 ret = wl1271_cmd_radio_parms(wl);
1427                 if (ret < 0)
1428                         goto out;
1429                 ret = wl1271_cmd_ext_radio_parms(wl);
1430                 if (ret < 0)
1431                         goto out;
1432         }
1433 out:
1434         return ret;
1435 }
1436
1437 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1438                                      struct wl_fw_status *fw_status)
1439 {
1440         struct wl12xx_fw_status *int_fw_status = raw_fw_status;
1441
1442         fw_status->intr = le32_to_cpu(int_fw_status->intr);
1443         fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1444         fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1445         fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1446         fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1447
1448         fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1449         fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1450         fw_status->link_fast_bitmap =
1451                         le32_to_cpu(int_fw_status->link_fast_bitmap);
1452         fw_status->total_released_blks =
1453                         le32_to_cpu(int_fw_status->total_released_blks);
1454         fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1455
1456         fw_status->counters.tx_released_pkts =
1457                         int_fw_status->counters.tx_released_pkts;
1458         fw_status->counters.tx_lnk_free_pkts =
1459                         int_fw_status->counters.tx_lnk_free_pkts;
1460         fw_status->counters.tx_voice_released_blks =
1461                         int_fw_status->counters.tx_voice_released_blks;
1462         fw_status->counters.tx_last_rate =
1463                         int_fw_status->counters.tx_last_rate;
1464
1465         fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1466 }
1467
1468 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1469                                        struct wl12xx_vif *wlvif)
1470 {
1471         return wlvif->rate_set;
1472 }
1473
1474 static void wl12xx_conf_init(struct wl1271 *wl)
1475 {
1476         struct wl12xx_priv *priv = wl->priv;
1477
1478         /* apply driver default configuration */
1479         memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1480
1481         /* apply default private configuration */
1482         memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1483 }
1484
1485 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1486 {
1487         bool supported = false;
1488         u8 major, minor;
1489
1490         if (wl->chip.id == CHIP_ID_128X_PG20) {
1491                 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1492                 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1493
1494                 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1495                 if (major > 2 || (major == 2 && minor >= 1))
1496                         supported = true;
1497         } else {
1498                 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1499                 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1500
1501                 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1502                 if (major == 3 && minor >= 1)
1503                         supported = true;
1504         }
1505
1506         wl1271_debug(DEBUG_PROBE,
1507                      "PG Ver major = %d minor = %d, MAC %s present",
1508                      major, minor, supported ? "is" : "is not");
1509
1510         return supported;
1511 }
1512
1513 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1514 {
1515         u32 mac1, mac2;
1516         int ret;
1517
1518         /* Device may be in ELP from the bootloader or kexec */
1519         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1520         if (ret < 0)
1521                 goto out;
1522
1523         usleep_range(500000, 700000);
1524
1525         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1526         if (ret < 0)
1527                 goto out;
1528
1529         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1530         if (ret < 0)
1531                 goto out;
1532
1533         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1534         if (ret < 0)
1535                 goto out;
1536
1537         /* these are the two parts of the BD_ADDR */
1538         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1539                 ((mac1 & 0xff000000) >> 24);
1540         wl->fuse_nic_addr = mac1 & 0xffffff;
1541
1542         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1543
1544 out:
1545         return ret;
1546 }
1547
1548 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1549 {
1550         u16 die_info;
1551         int ret;
1552
1553         if (wl->chip.id == CHIP_ID_128X_PG20)
1554                 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1555                                           &die_info);
1556         else
1557                 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1558                                           &die_info);
1559
1560         if (ret >= 0 && ver)
1561                 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1562
1563         return ret;
1564 }
1565
1566 static int wl12xx_get_mac(struct wl1271 *wl)
1567 {
1568         if (wl12xx_mac_in_fuse(wl))
1569                 return wl12xx_get_fuse_mac(wl);
1570
1571         return 0;
1572 }
1573
1574 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1575                                     struct wl1271_tx_hw_descr *desc,
1576                                     struct sk_buff *skb)
1577 {
1578         desc->wl12xx_reserved = 0;
1579 }
1580
1581 static int wl12xx_plt_init(struct wl1271 *wl)
1582 {
1583         int ret;
1584
1585         ret = wl->ops->boot(wl);
1586         if (ret < 0)
1587                 goto out;
1588
1589         ret = wl->ops->hw_init(wl);
1590         if (ret < 0)
1591                 goto out_irq_disable;
1592
1593         /*
1594          * If we are in calibrator based auto detect then we got the FEM nr
1595          * in wl->fem_manuf. No need to continue further
1596          */
1597         if (wl->plt_mode == PLT_FEM_DETECT)
1598                 goto out;
1599
1600         ret = wl1271_acx_init_mem_config(wl);
1601         if (ret < 0)
1602                 goto out_irq_disable;
1603
1604         ret = wl12xx_acx_mem_cfg(wl);
1605         if (ret < 0)
1606                 goto out_free_memmap;
1607
1608         /* Enable data path */
1609         ret = wl1271_cmd_data_path(wl, 1);
1610         if (ret < 0)
1611                 goto out_free_memmap;
1612
1613         /* Configure for CAM power saving (ie. always active) */
1614         ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1615         if (ret < 0)
1616                 goto out_free_memmap;
1617
1618         /* configure PM */
1619         ret = wl1271_acx_pm_config(wl);
1620         if (ret < 0)
1621                 goto out_free_memmap;
1622
1623         goto out;
1624
1625 out_free_memmap:
1626         kfree(wl->target_mem_map);
1627         wl->target_mem_map = NULL;
1628
1629 out_irq_disable:
1630         mutex_unlock(&wl->mutex);
1631         /* Unlocking the mutex in the middle of handling is
1632            inherently unsafe. In this case we deem it safe to do,
1633            because we need to let any possibly pending IRQ out of
1634            the system (and while we are WL1271_STATE_OFF the IRQ
1635            work function will not do anything.) Also, any other
1636            possible concurrent operations will fail due to the
1637            current state, hence the wl1271 struct should be safe. */
1638         wlcore_disable_interrupts(wl);
1639         mutex_lock(&wl->mutex);
1640 out:
1641         return ret;
1642 }
1643
1644 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1645 {
1646         if (is_gem)
1647                 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1648
1649         return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1650 }
1651
1652 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1653                           struct ieee80211_vif *vif,
1654                           struct ieee80211_sta *sta,
1655                           struct ieee80211_key_conf *key_conf)
1656 {
1657         return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1658 }
1659
1660 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1661                                struct ieee80211_sta_ht_cap *ht_cap,
1662                                bool allow_ht_operation,
1663                                u32 rate_set, u8 hlid)
1664 {
1665         return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1666                                               hlid);
1667 }
1668
1669 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1670                                  struct wl1271_link *lnk)
1671 {
1672         u8 thold;
1673
1674         if (test_bit(hlid, &wl->fw_fast_lnk_map))
1675                 thold = wl->conf.tx.fast_link_thold;
1676         else
1677                 thold = wl->conf.tx.slow_link_thold;
1678
1679         return lnk->allocated_pkts < thold;
1680 }
1681
1682 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1683                                 struct wl1271_link *lnk)
1684 {
1685         /* any link is good for low priority */
1686         return true;
1687 }
1688
1689 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1690 {
1691         return hwaddr << 5;
1692 }
1693
1694 static int wl12xx_setup(struct wl1271 *wl);
1695
1696 static struct wlcore_ops wl12xx_ops = {
1697         .setup                  = wl12xx_setup,
1698         .identify_chip          = wl12xx_identify_chip,
1699         .boot                   = wl12xx_boot,
1700         .plt_init               = wl12xx_plt_init,
1701         .trigger_cmd            = wl12xx_trigger_cmd,
1702         .ack_event              = wl12xx_ack_event,
1703         .wait_for_event         = wl12xx_wait_for_event,
1704         .process_mailbox_events = wl12xx_process_mailbox_events,
1705         .calc_tx_blocks         = wl12xx_calc_tx_blocks,
1706         .set_tx_desc_blocks     = wl12xx_set_tx_desc_blocks,
1707         .set_tx_desc_data_len   = wl12xx_set_tx_desc_data_len,
1708         .get_rx_buf_align       = wl12xx_get_rx_buf_align,
1709         .get_rx_packet_len      = wl12xx_get_rx_packet_len,
1710         .tx_immediate_compl     = NULL,
1711         .tx_delayed_compl       = wl12xx_tx_delayed_compl,
1712         .hw_init                = wl12xx_hw_init,
1713         .init_vif               = NULL,
1714         .convert_fw_status      = wl12xx_convert_fw_status,
1715         .sta_get_ap_rate_mask   = wl12xx_sta_get_ap_rate_mask,
1716         .get_pg_ver             = wl12xx_get_pg_ver,
1717         .get_mac                = wl12xx_get_mac,
1718         .set_tx_desc_csum       = wl12xx_set_tx_desc_csum,
1719         .set_rx_csum            = NULL,
1720         .ap_get_mimo_wide_rate_mask = NULL,
1721         .debugfs_init           = wl12xx_debugfs_add_files,
1722         .scan_start             = wl12xx_scan_start,
1723         .scan_stop              = wl12xx_scan_stop,
1724         .sched_scan_start       = wl12xx_sched_scan_start,
1725         .sched_scan_stop        = wl12xx_scan_sched_scan_stop,
1726         .get_spare_blocks       = wl12xx_get_spare_blocks,
1727         .set_key                = wl12xx_set_key,
1728         .channel_switch         = wl12xx_cmd_channel_switch,
1729         .pre_pkt_send           = NULL,
1730         .set_peer_cap           = wl12xx_set_peer_cap,
1731         .convert_hwaddr         = wl12xx_convert_hwaddr,
1732         .lnk_high_prio          = wl12xx_lnk_high_prio,
1733         .lnk_low_prio           = wl12xx_lnk_low_prio,
1734         .interrupt_notify       = NULL,
1735         .rx_ba_filter           = NULL,
1736         .ap_sleep               = NULL,
1737 };
1738
1739 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1740         .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1741                (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1742         .ht_supported = true,
1743         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1744         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1745         .mcs = {
1746                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1747                 .rx_highest = cpu_to_le16(72),
1748                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1749                 },
1750 };
1751
1752 static const struct ieee80211_iface_limit wl12xx_iface_limits[] = {
1753         {
1754                 .max = 3,
1755                 .types = BIT(NL80211_IFTYPE_STATION),
1756         },
1757         {
1758                 .max = 1,
1759                 .types = BIT(NL80211_IFTYPE_AP) |
1760                          BIT(NL80211_IFTYPE_P2P_GO) |
1761                          BIT(NL80211_IFTYPE_P2P_CLIENT),
1762         },
1763 };
1764
1765 static const struct ieee80211_iface_combination
1766 wl12xx_iface_combinations[] = {
1767         {
1768                 .max_interfaces = 3,
1769                 .limits = wl12xx_iface_limits,
1770                 .n_limits = ARRAY_SIZE(wl12xx_iface_limits),
1771                 .num_different_channels = 1,
1772         },
1773 };
1774
1775 static const struct wl12xx_clock wl12xx_refclock_table[] = {
1776         { 19200000,     false,  WL12XX_REFCLOCK_19      },
1777         { 26000000,     false,  WL12XX_REFCLOCK_26      },
1778         { 26000000,     true,   WL12XX_REFCLOCK_26_XTAL },
1779         { 38400000,     false,  WL12XX_REFCLOCK_38      },
1780         { 38400000,     true,   WL12XX_REFCLOCK_38_XTAL },
1781         { 52000000,     false,  WL12XX_REFCLOCK_52      },
1782         { 0,            false,  0 }
1783 };
1784
1785 static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
1786         { 16368000,     true,   WL12XX_TCXOCLOCK_16_368 },
1787         { 16800000,     true,   WL12XX_TCXOCLOCK_16_8   },
1788         { 19200000,     true,   WL12XX_TCXOCLOCK_19_2   },
1789         { 26000000,     true,   WL12XX_TCXOCLOCK_26     },
1790         { 32736000,     true,   WL12XX_TCXOCLOCK_32_736 },
1791         { 33600000,     true,   WL12XX_TCXOCLOCK_33_6   },
1792         { 38400000,     true,   WL12XX_TCXOCLOCK_38_4   },
1793         { 52000000,     true,   WL12XX_TCXOCLOCK_52     },
1794         { 0,            false,  0 }
1795 };
1796
1797 static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
1798                                 u32 freq, bool xtal)
1799 {
1800         int i;
1801
1802         for (i = 0; table[i].freq != 0; i++)
1803                 if ((table[i].freq == freq) && (table[i].xtal == xtal))
1804                         return table[i].hw_idx;
1805
1806         return -EINVAL;
1807 }
1808
1809 static int wl12xx_setup(struct wl1271 *wl)
1810 {
1811         struct wl12xx_priv *priv = wl->priv;
1812         struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1813
1814         BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
1815         BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
1816
1817         wl->rtable = wl12xx_rtable;
1818         wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1819         wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1820         wl->num_links = WL12XX_MAX_LINKS;
1821         wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1822         wl->iface_combinations = wl12xx_iface_combinations;
1823         wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1824         wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1825         wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1826         wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1827         wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1828         wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1829         wl->fw_status_priv_len = 0;
1830         wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1831         wl->ofdm_only_ap = true;
1832         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
1833         wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
1834         wl12xx_conf_init(wl);
1835
1836         if (!fref_param) {
1837                 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
1838                                                 pdev_data->ref_clock_freq,
1839                                                 pdev_data->ref_clock_xtal);
1840                 if (priv->ref_clock < 0) {
1841                         wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
1842                                      pdev_data->ref_clock_freq,
1843                                      pdev_data->ref_clock_xtal ?
1844                                      "XTAL" : "not XTAL");
1845
1846                         return priv->ref_clock;
1847                 }
1848         } else {
1849                 if (!strcmp(fref_param, "19.2"))
1850                         priv->ref_clock = WL12XX_REFCLOCK_19;
1851                 else if (!strcmp(fref_param, "26"))
1852                         priv->ref_clock = WL12XX_REFCLOCK_26;
1853                 else if (!strcmp(fref_param, "26x"))
1854                         priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1855                 else if (!strcmp(fref_param, "38.4"))
1856                         priv->ref_clock = WL12XX_REFCLOCK_38;
1857                 else if (!strcmp(fref_param, "38.4x"))
1858                         priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1859                 else if (!strcmp(fref_param, "52"))
1860                         priv->ref_clock = WL12XX_REFCLOCK_52;
1861                 else
1862                         wl1271_error("Invalid fref parameter %s", fref_param);
1863         }
1864
1865         if (!tcxo_param && pdev_data->tcxo_clock_freq) {
1866                 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
1867                                                 pdev_data->tcxo_clock_freq,
1868                                                 true);
1869                 if (priv->tcxo_clock < 0) {
1870                         wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
1871                                      pdev_data->tcxo_clock_freq);
1872
1873                         return priv->tcxo_clock;
1874                 }
1875         } else if (tcxo_param) {
1876                 if (!strcmp(tcxo_param, "19.2"))
1877                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1878                 else if (!strcmp(tcxo_param, "26"))
1879                         priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1880                 else if (!strcmp(tcxo_param, "38.4"))
1881                         priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1882                 else if (!strcmp(tcxo_param, "52"))
1883                         priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1884                 else if (!strcmp(tcxo_param, "16.368"))
1885                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1886                 else if (!strcmp(tcxo_param, "32.736"))
1887                         priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1888                 else if (!strcmp(tcxo_param, "16.8"))
1889                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1890                 else if (!strcmp(tcxo_param, "33.6"))
1891                         priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1892                 else
1893                         wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1894         }
1895
1896         priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL);
1897         if (!priv->rx_mem_addr)
1898                 return -ENOMEM;
1899
1900         return 0;
1901 }
1902
1903 static int wl12xx_probe(struct platform_device *pdev)
1904 {
1905         struct wl1271 *wl;
1906         struct ieee80211_hw *hw;
1907         int ret;
1908
1909         hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1910                              WL12XX_AGGR_BUFFER_SIZE,
1911                              sizeof(struct wl12xx_event_mailbox));
1912         if (IS_ERR(hw)) {
1913                 wl1271_error("can't allocate hw");
1914                 ret = PTR_ERR(hw);
1915                 goto out;
1916         }
1917
1918         wl = hw->priv;
1919         wl->ops = &wl12xx_ops;
1920         wl->ptable = wl12xx_ptable;
1921         ret = wlcore_probe(wl, pdev);
1922         if (ret)
1923                 goto out_free;
1924
1925         return ret;
1926
1927 out_free:
1928         wlcore_free_hw(wl);
1929 out:
1930         return ret;
1931 }
1932
1933 static int wl12xx_remove(struct platform_device *pdev)
1934 {
1935         struct wl1271 *wl = platform_get_drvdata(pdev);
1936         struct wl12xx_priv *priv;
1937
1938         if (!wl)
1939                 goto out;
1940         priv = wl->priv;
1941
1942         kfree(priv->rx_mem_addr);
1943
1944 out:
1945         return wlcore_remove(pdev);
1946 }
1947
1948 static const struct platform_device_id wl12xx_id_table[] = {
1949         { "wl12xx", 0 },
1950         {  } /* Terminating Entry */
1951 };
1952 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1953
1954 static struct platform_driver wl12xx_driver = {
1955         .probe          = wl12xx_probe,
1956         .remove         = wl12xx_remove,
1957         .id_table       = wl12xx_id_table,
1958         .driver = {
1959                 .name   = "wl12xx_driver",
1960         }
1961 };
1962
1963 module_platform_driver(wl12xx_driver);
1964
1965 module_param_named(fref, fref_param, charp, 0);
1966 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1967
1968 module_param_named(tcxo, tcxo_param, charp, 0);
1969 MODULE_PARM_DESC(tcxo,
1970                  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1971
1972 MODULE_LICENSE("GPL v2");
1973 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1974 /*(DEBLOBBED)*/