1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-level device IO routines for ST-Ericsson CW1200 drivers
5 * Copyright (c) 2010, ST-Ericsson
6 * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
9 * ST-Ericsson UMAC CW1200 driver, which is
10 * Copyright (c) 2010, ST-Ericsson
11 * Author: Ajitpal Singh <ajitpal.singh@lockless.no>
14 #include <linux/types.h>
20 /* Sdio addr is 4*spi_addr */
21 #define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
22 #define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
23 ((((buf_id) & 0x1F) << 7) \
24 | (((mpf) & 1) << 6) \
25 | (((rfu) & 1) << 5) \
26 | (((reg_id_ofs) & 0x1F) << 0))
30 static int __cw1200_reg_read(struct cw1200_common *priv, u16 addr,
31 void *buf, size_t buf_len, int buf_id)
34 u32 sdio_reg_addr_17bit;
36 /* Check if buffer is aligned to 4 byte boundary */
37 if (WARN_ON(((unsigned long)buf & 3) && (buf_len > 4))) {
38 pr_err("buffer is not aligned.\n");
42 /* Convert to SDIO Register Address */
43 addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
44 sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
46 return priv->hwbus_ops->hwbus_memcpy_fromio(priv->hwbus_priv,
51 static int __cw1200_reg_write(struct cw1200_common *priv, u16 addr,
52 const void *buf, size_t buf_len, int buf_id)
55 u32 sdio_reg_addr_17bit;
57 /* Convert to SDIO Register Address */
58 addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
59 sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
61 return priv->hwbus_ops->hwbus_memcpy_toio(priv->hwbus_priv,
66 static inline int __cw1200_reg_read_32(struct cw1200_common *priv,
70 int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
71 *val = le32_to_cpu(tmp);
75 static inline int __cw1200_reg_write_32(struct cw1200_common *priv,
78 __le32 tmp = cpu_to_le32(val);
79 return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
82 static inline int __cw1200_reg_read_16(struct cw1200_common *priv,
86 int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
87 *val = le16_to_cpu(tmp);
91 static inline int __cw1200_reg_write_16(struct cw1200_common *priv,
94 __le16 tmp = cpu_to_le16(val);
95 return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
98 int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf,
102 priv->hwbus_ops->lock(priv->hwbus_priv);
103 ret = __cw1200_reg_read(priv, addr, buf, buf_len, 0);
104 priv->hwbus_ops->unlock(priv->hwbus_priv);
108 int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf,
112 priv->hwbus_ops->lock(priv->hwbus_priv);
113 ret = __cw1200_reg_write(priv, addr, buf, buf_len, 0);
114 priv->hwbus_ops->unlock(priv->hwbus_priv);
118 int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len)
121 int buf_id_rx = priv->buf_id_rx;
123 priv->hwbus_ops->lock(priv->hwbus_priv);
125 while (retry <= MAX_RETRY) {
126 ret = __cw1200_reg_read(priv,
127 ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
128 buf_len, buf_id_rx + 1);
130 buf_id_rx = (buf_id_rx + 1) & 3;
131 priv->buf_id_rx = buf_id_rx;
136 pr_err("error :[%d]\n", ret);
140 priv->hwbus_ops->unlock(priv->hwbus_priv);
144 int cw1200_data_write(struct cw1200_common *priv, const void *buf,
148 int buf_id_tx = priv->buf_id_tx;
150 priv->hwbus_ops->lock(priv->hwbus_priv);
152 while (retry <= MAX_RETRY) {
153 ret = __cw1200_reg_write(priv,
154 ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
157 buf_id_tx = (buf_id_tx + 1) & 31;
158 priv->buf_id_tx = buf_id_tx;
163 pr_err("error :[%d]\n", ret);
167 priv->hwbus_ops->unlock(priv->hwbus_priv);
171 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
172 size_t buf_len, u32 prefetch, u16 port_addr)
177 if ((buf_len / 2) >= 0x1000) {
178 pr_err("Can't read more than 0xfff words.\n");
182 priv->hwbus_ops->lock(priv->hwbus_priv);
184 ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
186 pr_err("Can't write address register.\n");
190 /* Read CONFIG Register Value - We will read 32 bits */
191 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
193 pr_err("Can't read config register.\n");
197 /* Set PREFETCH bit */
198 ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID,
201 pr_err("Can't write prefetch bit.\n");
205 /* Check for PRE-FETCH bit to be cleared */
206 for (i = 0; i < 20; i++) {
207 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
209 pr_err("Can't check prefetch bit.\n");
212 if (!(val32 & prefetch))
218 if (val32 & prefetch) {
219 pr_err("Prefetch bit is not cleared.\n");
224 ret = __cw1200_reg_read(priv, port_addr, buf, buf_len, 0);
226 pr_err("Can't read data port.\n");
231 priv->hwbus_ops->unlock(priv->hwbus_priv);
235 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
240 if ((buf_len / 2) >= 0x1000) {
241 pr_err("Can't write more than 0xfff words.\n");
245 priv->hwbus_ops->lock(priv->hwbus_priv);
248 ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
250 pr_err("Can't write address register.\n");
254 /* Write data port */
255 ret = __cw1200_reg_write(priv, ST90TDS_SRAM_DPORT_REG_ID,
258 pr_err("Can't write data port.\n");
263 priv->hwbus_ops->unlock(priv->hwbus_priv);
267 int __cw1200_irq_enable(struct cw1200_common *priv, int enable)
273 if (HIF_8601_SILICON == priv->hw_type) {
274 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
276 pr_err("Can't read config register.\n");
281 val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE;
283 val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE;
285 ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32);
287 pr_err("Can't write config register.\n");
291 ret = __cw1200_reg_read_16(priv, ST90TDS_CONFIG_REG_ID, &val16);
293 pr_err("Can't read control register.\n");
298 val16 |= ST90TDS_CONT_IRQ_RDY_ENABLE;
300 val16 &= ~ST90TDS_CONT_IRQ_RDY_ENABLE;
302 ret = __cw1200_reg_write_16(priv, ST90TDS_CONFIG_REG_ID, val16);
304 pr_err("Can't write control register.\n");