2 * Copyright (c) 2017 Redpine Signals Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define FLASH_WRITE_CHUNK_SIZE (4 * 1024)
21 #define FLASH_SECTOR_SIZE (4 * 1024)
23 #define FLASH_SIZE_ADDR 0x04000016
24 #define PING_BUFFER_ADDRESS 0x19000
25 #define PONG_BUFFER_ADDRESS 0x1a000
26 #define SWBL_REGIN 0x41050034
27 #define SWBL_REGOUT 0x4105003c
28 #define PING_WRITE 0x1
29 #define PONG_WRITE 0x2
31 #define BL_CMD_TIMEOUT 2000
32 #define BL_BURN_TIMEOUT (50 * 1000)
34 #define REGIN_VALID 0xA
35 #define REGIN_INPUT 0xA0
36 #define REGOUT_VALID 0xAB
37 #define REGOUT_INVALID (~0xAB)
41 #define LOAD_HOSTED_FW 'A'
42 #define BURN_HOSTED_FW 'B'
43 #define PING_VALID 'I'
44 #define PONG_VALID 'O'
45 #define PING_AVAIL 'I'
46 #define PONG_AVAIL 'O'
47 #define EOF_REACHED 'E'
49 #define POLLING_MODE 'P'
50 #define CONFIG_AUTO_READ_MODE 'R'
51 #define JUMP_TO_ZERO_PC 'J'
52 #define FW_LOADING_SUCCESSFUL 'S'
53 #define LOADING_INITIATED '1'
55 #define RSI_ULP_RESET_REG 0x161
56 #define RSI_WATCH_DOG_TIMER_1 0x16c
57 #define RSI_WATCH_DOG_TIMER_2 0x16d
58 #define RSI_WATCH_DOG_DELAY_TIMER_1 0x16e
59 #define RSI_WATCH_DOG_DELAY_TIMER_2 0x16f
60 #define RSI_WATCH_DOG_TIMER_ENABLE 0x170
62 #define RSI_ULP_WRITE_0 00
63 #define RSI_ULP_WRITE_2 02
64 #define RSI_ULP_WRITE_50 50
66 #define RSI_RESTART_WDT BIT(11)
67 #define RSI_BYPASS_ULP_ON_WDT BIT(1)
69 #define RSI_ULP_TIMER_ENABLE ((0xaa000) | RSI_RESTART_WDT | \
70 RSI_BYPASS_ULP_ON_WDT)
71 #define RSI_RF_SPI_PROG_REG_BASE_ADDR 0x40080000
73 #define RSI_GSPI_CTRL_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR)
74 #define RSI_GSPI_CTRL_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
75 #define RSI_GSPI_DATA_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
76 #define RSI_GSPI_DATA_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
77 #define RSI_GSPI_DATA_REG2 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
79 #define RSI_GSPI_CTRL_REG0_VALUE 0x340
81 #define RSI_GSPI_DMA_MODE BIT(13)
83 #define RSI_GSPI_2_ULP BIT(12)
84 #define RSI_GSPI_TRIG BIT(7)
85 #define RSI_GSPI_READ BIT(6)
86 #define RSI_GSPI_RF_SPI_ACTIVE BIT(8)
88 /* Boot loader commands */
89 #define SEND_RPS_FILE '2'
91 #define FW_IMAGE_MIN_ADDRESS (68 * 1024)
92 #define MAX_FLASH_FILE_SIZE (400 * 1024) //400K
93 #define FLASH_START_ADDRESS 16
95 #define COMMON_HAL_CARD_READY_IND 0x0
97 #define COMMAN_HAL_WAIT_FOR_CARD_READY 1
99 #define RSI_DEV_OPMODE_WIFI_ALONE 1
100 #define RSI_DEV_COEX_MODE_WIFI_ALONE 1
102 #define BBP_INFO_40MHZ 0x6
108 __le32 flash_start_address;
114 unsigned int address;
117 struct rsi_mgmt_desc {
132 struct rsi_data_desc {
146 int rsi_hal_device_init(struct rsi_hw *adapter);
147 int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
148 int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);