1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
5 #ifndef __RTW89_8852A_H__
6 #define __RTW89_8852A_H__
10 #define RF_PATH_NUM_8852A 2
11 #define NTX_NUM_8852A 2
13 enum rtw8852a_pmac_mode {
20 struct rtw8852au_efuse {
22 u8 mac_addr[ETH_ALEN];
25 struct rtw8852ae_efuse {
26 u8 mac_addr[ETH_ALEN];
29 struct rtw8852a_tssi_offset {
30 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
31 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
33 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
36 struct rtw8852a_efuse {
38 struct rtw8852a_tssi_offset path_a_tssi;
40 struct rtw8852a_tssi_offset path_b_tssi;
62 u8 tx_cali_pwr_trk_mode;
63 u8 trx_path_selection;
70 u8 path_a_cck_pwr_idx[6];
71 u8 path_a_bw40_1tx_pwr_idx[5];
72 u8 path_a_ofdm_1tx_pwr_idx_diff:4;
73 u8 path_a_bw20_1tx_pwr_idx_diff:4;
74 u8 path_a_bw20_2tx_pwr_idx_diff:4;
75 u8 path_a_bw40_2tx_pwr_idx_diff:4;
76 u8 path_a_cck_2tx_pwr_idx_diff:4;
77 u8 path_a_ofdm_2tx_pwr_idx_diff:4;
80 struct rtw8852au_efuse u;
81 struct rtw8852ae_efuse e;
85 struct rtw8852a_bb_pmac_info {
96 extern const struct rtw89_chip_info rtw8852a_chip_info;
98 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
99 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
100 struct rtw8852a_bb_pmac_info *tx_info,
101 enum rtw89_phy_idx idx);
102 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
103 u16 tx_cnt, u16 period, u16 tx_time,
104 enum rtw89_phy_idx idx);
105 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
106 enum rtw89_phy_idx idx);
107 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
108 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
109 enum rtw89_phy_idx idx, u8 mode);