1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
10 enum rtw89_efuse_bank {
11 RTW89_EFUSE_BANK_WIFI,
15 static int rtw89_switch_efuse_bank(struct rtw89_dev *rtwdev,
16 enum rtw89_efuse_bank bank)
20 if (rtwdev->chip->chip_id != RTL8852A)
23 val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1,
24 B_AX_EF_CELL_SEL_MASK);
28 rtw89_write32_mask(rtwdev, R_AX_EFUSE_CTRL_1, B_AX_EF_CELL_SEL_MASK,
31 val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1,
32 B_AX_EF_CELL_SEL_MASK);
39 static void rtw89_enable_otp_burst_mode(struct rtw89_dev *rtwdev, bool en)
42 rtw89_write32_set(rtwdev, R_AX_EFUSE_CTRL_1_V1, B_AX_EF_BURST);
44 rtw89_write32_clr(rtwdev, R_AX_EFUSE_CTRL_1_V1, B_AX_EF_BURST);
47 static void rtw89_enable_efuse_pwr_cut_ddv(struct rtw89_dev *rtwdev)
49 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
50 struct rtw89_hal *hal = &rtwdev->hal;
52 if (chip_id == RTL8852A)
55 rtw89_write8_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
56 rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
60 rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
61 rtw89_write16_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
62 if (chip_id == RTL8852B && hal->cv == CHIP_CAV)
63 rtw89_enable_otp_burst_mode(rtwdev, true);
66 static void rtw89_disable_efuse_pwr_cut_ddv(struct rtw89_dev *rtwdev)
68 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
69 struct rtw89_hal *hal = &rtwdev->hal;
71 if (chip_id == RTL8852A)
74 if (chip_id == RTL8852B && hal->cv == CHIP_CAV)
75 rtw89_enable_otp_burst_mode(rtwdev, false);
77 rtw89_write16_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
78 rtw89_write16_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
82 rtw89_write16_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
83 rtw89_write8_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
86 static int rtw89_dump_physical_efuse_map_ddv(struct rtw89_dev *rtwdev, u8 *map,
87 u32 dump_addr, u32 dump_size)
93 rtw89_enable_efuse_pwr_cut_ddv(rtwdev);
95 for (addr = dump_addr; addr < dump_addr + dump_size; addr++) {
96 efuse_ctl = u32_encode_bits(addr, B_AX_EF_ADDR_MASK);
97 rtw89_write32(rtwdev, R_AX_EFUSE_CTRL, efuse_ctl & ~B_AX_EF_RDY);
99 ret = read_poll_timeout_atomic(rtw89_read32, efuse_ctl,
100 efuse_ctl & B_AX_EF_RDY, 1, 1000000,
101 true, rtwdev, R_AX_EFUSE_CTRL);
105 *map++ = (u8)(efuse_ctl & 0xff);
108 rtw89_disable_efuse_pwr_cut_ddv(rtwdev);
113 static int rtw89_dump_physical_efuse_map_dav(struct rtw89_dev *rtwdev, u8 *map,
114 u32 dump_addr, u32 dump_size)
121 for (addr = dump_addr; addr < dump_addr + dump_size; addr++) {
122 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, 0x40, FULL_BIT_MASK);
125 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_LOW_ADDR,
126 addr & 0xff, XTAL_SI_LOW_ADDR_MASK);
129 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, addr >> 8,
130 XTAL_SI_HIGH_ADDR_MASK);
133 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_CTRL, 0,
134 XTAL_SI_MODE_SEL_MASK);
138 ret = read_poll_timeout_atomic(rtw89_mac_read_xtal_si, err,
139 !err && (val8 & XTAL_SI_RDY),
141 rtwdev, XTAL_SI_CTRL, &val8);
143 rtw89_warn(rtwdev, "failed to read dav efuse\n");
147 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_READ_VAL, &val8);
156 static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,
157 u32 dump_addr, u32 dump_size, bool dav)
161 if (!map || dump_size == 0)
164 rtw89_switch_efuse_bank(rtwdev, RTW89_EFUSE_BANK_WIFI);
167 ret = rtw89_dump_physical_efuse_map_dav(rtwdev, map, dump_addr, dump_size);
171 ret = rtw89_dump_physical_efuse_map_ddv(rtwdev, map, dump_addr, dump_size);
179 #define invalid_efuse_header(hdr1, hdr2) \
180 ((hdr1) == 0xff || (hdr2) == 0xff)
181 #define invalid_efuse_content(word_en, i) \
182 (((word_en) & BIT(i)) != 0x0)
183 #define get_efuse_blk_idx(hdr1, hdr2) \
184 ((((hdr2) & 0xf0) >> 4) | (((hdr1) & 0x0f) << 4))
185 #define block_idx_to_logical_idx(blk_idx, i) \
186 (((blk_idx) << 3) + ((i) << 1))
187 static int rtw89_dump_logical_efuse_map(struct rtw89_dev *rtwdev, u8 *phy_map,
190 u32 physical_size = rtwdev->chip->physical_efuse_size;
191 u32 logical_size = rtwdev->chip->logical_efuse_size;
192 u8 sec_ctrl_size = rtwdev->chip->sec_ctrl_efuse_size;
193 u32 phy_idx = sec_ctrl_size;
203 while (phy_idx < physical_size - sec_ctrl_size) {
204 hdr1 = phy_map[phy_idx];
205 hdr2 = phy_map[phy_idx + 1];
206 if (invalid_efuse_header(hdr1, hdr2))
209 blk_idx = get_efuse_blk_idx(hdr1, hdr2);
210 word_en = hdr2 & 0xf;
213 for (i = 0; i < 4; i++) {
214 if (invalid_efuse_content(word_en, i))
217 log_idx = block_idx_to_logical_idx(blk_idx, i);
218 if (phy_idx + 1 > physical_size - sec_ctrl_size - 1 ||
219 log_idx + 1 > logical_size)
222 log_map[log_idx] = phy_map[phy_idx];
223 log_map[log_idx + 1] = phy_map[phy_idx + 1];
230 int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev)
232 u32 phy_size = rtwdev->chip->physical_efuse_size;
233 u32 log_size = rtwdev->chip->logical_efuse_size;
234 u32 dav_phy_size = rtwdev->chip->dav_phy_efuse_size;
235 u32 dav_log_size = rtwdev->chip->dav_log_efuse_size;
236 u32 full_log_size = log_size + dav_log_size;
239 u8 *dav_phy_map = NULL;
240 u8 *dav_log_map = NULL;
243 if (rtw89_read16(rtwdev, R_AX_SYS_WL_EFUSE_CTRL) & B_AX_AUTOLOAD_SUS)
244 rtwdev->efuse.valid = true;
246 rtw89_warn(rtwdev, "failed to check efuse autoload\n");
248 phy_map = kmalloc(phy_size, GFP_KERNEL);
249 log_map = kmalloc(full_log_size, GFP_KERNEL);
250 if (dav_phy_size && dav_log_size) {
251 dav_phy_map = kmalloc(dav_phy_size, GFP_KERNEL);
252 dav_log_map = log_map + log_size;
255 if (!phy_map || !log_map || (dav_phy_size && !dav_phy_map)) {
260 ret = rtw89_dump_physical_efuse_map(rtwdev, phy_map, 0, phy_size, false);
262 rtw89_warn(rtwdev, "failed to dump efuse physical map\n");
265 ret = rtw89_dump_physical_efuse_map(rtwdev, dav_phy_map, 0, dav_phy_size, true);
267 rtw89_warn(rtwdev, "failed to dump efuse dav physical map\n");
271 memset(log_map, 0xff, full_log_size);
272 ret = rtw89_dump_logical_efuse_map(rtwdev, phy_map, log_map);
274 rtw89_warn(rtwdev, "failed to dump efuse logical map\n");
277 ret = rtw89_dump_logical_efuse_map(rtwdev, dav_phy_map, dav_log_map);
279 rtw89_warn(rtwdev, "failed to dump efuse dav logical map\n");
283 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "log_map: ", log_map, full_log_size);
285 ret = rtwdev->chip->ops->read_efuse(rtwdev, log_map);
287 rtw89_warn(rtwdev, "failed to read efuse map\n");
299 int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev)
301 u32 phycap_addr = rtwdev->chip->phycap_addr;
302 u32 phycap_size = rtwdev->chip->phycap_size;
303 u8 *phycap_map = NULL;
309 phycap_map = kmalloc(phycap_size, GFP_KERNEL);
313 ret = rtw89_dump_physical_efuse_map(rtwdev, phycap_map,
314 phycap_addr, phycap_size, false);
316 rtw89_warn(rtwdev, "failed to dump phycap map\n");
320 ret = rtwdev->chip->ops->read_phycap(rtwdev, phycap_map);
322 rtw89_warn(rtwdev, "failed to read phycap map\n");