1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
90 /*Max: define total number.*/
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102 #define ASPM_L1_LATENCY 7
104 #define TOTAL_CAM_ENTRY 32
106 /*slot time for 11g. */
107 #define RTL_SLOT_TIME_9 9
108 #define RTL_SLOT_TIME_20 20
110 /*related to tcp/ip. */
112 #define PROTOC_TYPE_SIZE 2
114 /*related with 802.11 frame*/
115 #define MAC80211_3ADDR_LEN 24
116 #define MAC80211_4ADDR_LEN 30
118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
119 #define CHANNEL_MAX_NUMBER_2G 14
120 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
121 *"phy_GetChnlGroup8812A" and
122 * "Hal_ReadTxPowerInfo8812A"
124 #define CHANNEL_MAX_NUMBER_5G_80M 7
125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
126 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
127 *"phy_GetChnlGroup8812A" and
128 * "Hal_ReadTxPowerInfo8812A"
130 #define CHANNEL_MAX_NUMBER_5G_80M 7
131 #define MAX_PG_GROUP 13
132 #define CHANNEL_GROUP_MAX_2G 3
133 #define CHANNEL_GROUP_IDX_5GL 3
134 #define CHANNEL_GROUP_IDX_5GM 6
135 #define CHANNEL_GROUP_IDX_5GH 9
136 #define CHANNEL_GROUP_MAX_5G 9
137 #define CHANNEL_MAX_NUMBER_2G 14
138 #define AVG_THERMAL_NUM 8
139 #define AVG_THERMAL_NUM_88E 4
140 #define AVG_THERMAL_NUM_8723BE 4
141 #define MAX_TID_COUNT 9
147 enum rtl8192c_h2c_cmd {
154 H2C_MACID_PS_MODE = 7,
155 H2C_P2P_PS_OFFLOAD = 8,
156 H2C_MAC_MODE_SEL = 9,
158 H2C_P2P_PS_CTW_CMD = 24,
162 #define MAX_TX_COUNT 4
163 #define MAX_REGULATION_NUM 4
164 #define MAX_RF_PATH_NUM 4
165 #define MAX_RATE_SECTION_NUM 6
166 #define MAX_2_4G_BANDWITH_NUM 4
167 #define MAX_5G_BANDWITH_NUM 4
168 #define MAX_RF_PATH 4
169 #define MAX_CHNL_GROUP_24G 6
170 #define MAX_CHNL_GROUP_5G 14
172 #define TX_PWR_BY_RATE_NUM_BAND 2
173 #define TX_PWR_BY_RATE_NUM_RF 4
174 #define TX_PWR_BY_RATE_NUM_SECTION 12
175 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
176 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
178 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
180 #define DEL_SW_IDX_SZ 30
183 /* For now, it's just for 8192ee
184 * but not OK yet, keep it 0
186 #define DMA_IS_64BIT 0
187 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
193 RF_TX_NUM_NONIMPLEMENT,
196 #define PACKET_NORMAL 0
197 #define PACKET_DHCP 1
199 #define PACKET_EAPOL 3
201 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
202 #define RSVD_WOL_PATTERN_NUM 1
203 #define WKFMCAM_ADDR_NUM 6
204 #define WKFMCAM_SIZE 24
206 #define MAX_WOL_BIT_MASK_SIZE 16
207 /* MIN LEN keeps 13 here */
208 #define MIN_WOL_PATTERN_SIZE 13
209 #define MAX_WOL_PATTERN_SIZE 128
211 #define WAKE_ON_MAGIC_PACKET BIT(0)
212 #define WAKE_ON_PATTERN_MATCH BIT(1)
214 #define WOL_REASON_PTK_UPDATE BIT(0)
215 #define WOL_REASON_GTK_UPDATE BIT(1)
216 #define WOL_REASON_DISASSOC BIT(2)
217 #define WOL_REASON_DEAUTH BIT(3)
218 #define WOL_REASON_AP_LOST BIT(4)
219 #define WOL_REASON_MAGIC_PKT BIT(5)
220 #define WOL_REASON_UNICAST_PKT BIT(6)
221 #define WOL_REASON_PATTERN_PKT BIT(7)
222 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
223 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
224 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
226 struct rtlwifi_firmware_header {
245 struct txpower_info_2g {
246 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
247 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
248 /*If only one tx, only BW20 and OFDM are used.*/
249 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
250 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
251 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
252 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
253 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
254 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 struct txpower_info_5g {
258 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
259 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
260 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
261 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
262 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
263 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
264 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
288 enum regulation_txpwr_lmt {
294 TXPWR_LMT_MAX_REGULATION_NUM = 4
297 enum rt_eeprom_type {
304 RTL_STATUS_INTERFACE_START = 0,
308 HARDWARE_TYPE_RTL8192E,
309 HARDWARE_TYPE_RTL8192U,
310 HARDWARE_TYPE_RTL8192SE,
311 HARDWARE_TYPE_RTL8192SU,
312 HARDWARE_TYPE_RTL8192CE,
313 HARDWARE_TYPE_RTL8192CU,
314 HARDWARE_TYPE_RTL8192DE,
315 HARDWARE_TYPE_RTL8192DU,
316 HARDWARE_TYPE_RTL8723AE,
317 HARDWARE_TYPE_RTL8723U,
318 HARDWARE_TYPE_RTL8188EE,
319 HARDWARE_TYPE_RTL8723BE,
320 HARDWARE_TYPE_RTL8192EE,
321 HARDWARE_TYPE_RTL8821AE,
322 HARDWARE_TYPE_RTL8812AE,
328 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
329 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
330 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
331 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
332 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
333 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
334 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
335 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
336 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
337 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
338 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
339 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
340 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
341 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
342 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
343 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
344 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
345 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
346 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
347 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
348 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
349 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
350 #define IS_HARDWARE_TYPE_8723(rtlhal) \
351 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
353 #define RX_HAL_IS_CCK_RATE(rxmcs) \
354 ((rxmcs) == DESC_RATE1M || \
355 (rxmcs) == DESC_RATE2M || \
356 (rxmcs) == DESC_RATE5_5M || \
357 (rxmcs) == DESC_RATE11M)
359 enum scan_operation_backup_opt {
361 SCAN_OPT_BACKUP_BAND0 = 0,
362 SCAN_OPT_BACKUP_BAND1,
391 u32 rf_rb; /* rflssi_readback */
392 u32 rf_rbpi; /* rflssi_readbackpi */
396 IO_CMD_PAUSE_DM_BY_SCAN = 0,
397 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
398 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
399 IO_CMD_RESUME_DM_BY_SCAN = 2,
404 HW_VAR_MULTICAST_REG,
408 HW_VAR_SECURITY_CONF,
409 HW_VAR_BEACON_INTERVAL,
411 HW_VAR_LISTEN_INTERVAL,
425 HW_VAR_RATE_FALLBACK_CONTROL,
426 HW_VAR_CONTENTION_WINDOW,
431 HW_VAR_AMPDU_MIN_SPACE,
432 HW_VAR_SHORTGI_DENSITY,
434 HW_VAR_MCS_RATE_AVAILABLE,
437 HW_VAR_DIS_Req_Qsize,
438 HW_VAR_CCX_CHNL_LOAD,
439 HW_VAR_CCX_NOISE_HISTOGRAM,
446 HW_VAR_SET_DEV_POWER,
456 HW_VAR_USER_CONTROL_TURBO_MODE,
462 HW_VAR_AUTOLOAD_STATUS,
463 HW_VAR_RF_2R_DISABLE,
465 HW_VAR_H2C_FW_PWRMODE,
466 HW_VAR_H2C_FW_JOINBSSRPT,
467 HW_VAR_H2C_FW_MEDIASTATUSRPT,
468 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
469 HW_VAR_FW_PSMODE_STATUS,
470 HW_VAR_INIT_RTS_RATE,
471 HW_VAR_RESUME_CLK_ON,
472 HW_VAR_FW_LPS_ACTION,
473 HW_VAR_1X1_RECV_COMBINE,
474 HW_VAR_STOP_SEND_BEACON,
479 HW_VAR_H2C_FW_UPDATE_GTK,
482 HW_VAR_WF_IS_MAC_ADDR,
483 HW_VAR_H2C_FW_OFFLOAD,
486 HW_VAR_HANDLE_FW_C2H,
487 HW_VAR_DL_FW_RSVD_PAGE,
489 HW_VAR_HW_SEQ_ENABLE,
494 HW_VAR_SWITCH_EPHY_WoWLAN,
495 HW_VAR_INT_MIGRATION,
509 enum rt_media_status {
510 RT_MEDIA_DISCONNECT = 0,
516 RT_CID_8187_ALPHA0 = 1,
517 RT_CID_8187_SERCOMM_PS = 2,
518 RT_CID_8187_HW_LED = 3,
519 RT_CID_8187_NETGEAR = 4,
521 RT_CID_819X_CAMEO = 6,
522 RT_CID_819X_RUNTOP = 7,
523 RT_CID_819X_SENAO = 8,
525 RT_CID_819X_NETCORE = 10,
526 RT_CID_NETTRONIX = 11,
530 RT_CID_819X_ALPHA = 15,
531 RT_CID_819X_SITECOM = 16,
533 RT_CID_819X_LENOVO = 18,
534 RT_CID_819X_QMI = 19,
535 RT_CID_819X_EDIMAX_BELKIN = 20,
536 RT_CID_819X_SERCOMM_BELKIN = 21,
537 RT_CID_819X_CAMEO1 = 22,
538 RT_CID_819X_MSI = 23,
539 RT_CID_819X_ACER = 24,
541 RT_CID_819X_CLEVO = 28,
542 RT_CID_819X_ARCADYAN_BELKIN = 29,
543 RT_CID_819X_SAMSUNG = 30,
544 RT_CID_819X_WNC_COREGA = 31,
545 RT_CID_819X_FOXCOON = 32,
546 RT_CID_819X_DELL = 33,
547 RT_CID_819X_PRONETS = 34,
548 RT_CID_819X_EDIMAX_ASUS = 35,
557 HW_DESC_TX_NEXTDESC_ADDR,
566 PRIME_CHNL_OFFSET_DONT_CARE = 0,
567 PRIME_CHNL_OFFSET_LOWER = 1,
568 PRIME_CHNL_OFFSET_UPPER = 2,
578 enum ht_channel_width {
579 HT_CHANNEL_WIDTH_20 = 0,
580 HT_CHANNEL_WIDTH_20_40 = 1,
581 HT_CHANNEL_WIDTH_80 = 2,
584 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
585 Cipher Suites Encryption Algorithms */
588 WEP40_ENCRYPTION = 1,
590 RSERVED_ENCRYPTION = 3,
591 AESCCMP_ENCRYPTION = 4,
592 WEP104_ENCRYPTION = 5,
593 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
598 _HAL_STATE_START = 1,
601 enum rtl_desc92_rate {
604 DESC_RATE5_5M = 0x02,
616 DESC_RATEMCS0 = 0x0c,
617 DESC_RATEMCS1 = 0x0d,
618 DESC_RATEMCS2 = 0x0e,
619 DESC_RATEMCS3 = 0x0f,
620 DESC_RATEMCS4 = 0x10,
621 DESC_RATEMCS5 = 0x11,
622 DESC_RATEMCS6 = 0x12,
623 DESC_RATEMCS7 = 0x13,
624 DESC_RATEMCS8 = 0x14,
625 DESC_RATEMCS9 = 0x15,
626 DESC_RATEMCS10 = 0x16,
627 DESC_RATEMCS11 = 0x17,
628 DESC_RATEMCS12 = 0x18,
629 DESC_RATEMCS13 = 0x19,
630 DESC_RATEMCS14 = 0x1a,
631 DESC_RATEMCS15 = 0x1b,
632 DESC_RATEMCS15_SG = 0x1c,
633 DESC_RATEMCS32 = 0x20,
635 DESC_RATEVHT1SS_MCS0 = 0x2c,
636 DESC_RATEVHT1SS_MCS1 = 0x2d,
637 DESC_RATEVHT1SS_MCS2 = 0x2e,
638 DESC_RATEVHT1SS_MCS3 = 0x2f,
639 DESC_RATEVHT1SS_MCS4 = 0x30,
640 DESC_RATEVHT1SS_MCS5 = 0x31,
641 DESC_RATEVHT1SS_MCS6 = 0x32,
642 DESC_RATEVHT1SS_MCS7 = 0x33,
643 DESC_RATEVHT1SS_MCS8 = 0x34,
644 DESC_RATEVHT1SS_MCS9 = 0x35,
645 DESC_RATEVHT2SS_MCS0 = 0x36,
646 DESC_RATEVHT2SS_MCS1 = 0x37,
647 DESC_RATEVHT2SS_MCS2 = 0x38,
648 DESC_RATEVHT2SS_MCS3 = 0x39,
649 DESC_RATEVHT2SS_MCS4 = 0x3a,
650 DESC_RATEVHT2SS_MCS5 = 0x3b,
651 DESC_RATEVHT2SS_MCS6 = 0x3c,
652 DESC_RATEVHT2SS_MCS7 = 0x3d,
653 DESC_RATEVHT2SS_MCS8 = 0x3e,
654 DESC_RATEVHT2SS_MCS9 = 0x3f,
680 EFUSE_HWSET_MAX_SIZE,
681 EFUSE_MAX_SECTION_MAP,
682 EFUSE_REAL_CONTENT_SIZE,
683 EFUSE_OOB_PROTECT_BYTES_LEN,
699 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
700 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
701 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
702 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
703 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
704 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
705 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
706 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
707 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
708 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
709 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
710 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
711 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
712 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
713 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
714 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
715 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
716 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
717 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
718 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
719 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
720 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
721 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
722 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
723 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
724 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
725 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
726 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
727 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
728 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
729 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
730 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
731 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
732 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
733 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
735 RTL_IMR_C2HCMD, /*fw interrupt*/
737 /*CCK Rates, TxHT = 0 */
743 /*OFDM Rates, TxHT = 0 */
756 RTL_RC_VHT_RATE_1SS_MCS7,
757 RTL_RC_VHT_RATE_1SS_MCS8,
758 RTL_RC_VHT_RATE_1SS_MCS9,
759 RTL_RC_VHT_RATE_2SS_MCS7,
760 RTL_RC_VHT_RATE_2SS_MCS8,
761 RTL_RC_VHT_RATE_2SS_MCS9,
767 /*Firmware PS mode for control LPS.*/
769 FW_PS_ACTIVE_MODE = 0,
774 FW_PS_UAPSD_WMM_MODE = 5,
775 FW_PS_UAPSD_MODE = 6,
777 FW_PS_WWLAN_MODE = 8,
778 FW_PS_PM_Radio_Off = 9,
779 FW_PS_PM_Card_Disable = 10,
783 EACTIVE, /*Active/Continuous access. */
784 EMAXPS, /*Max power save mode. */
785 EFASTPS, /*Fast power save mode. */
786 EAUTOPS, /*Auto power save mode. */
791 LED_CTL_POWER_ON = 1,
796 LED_CTL_SITE_SURVEY = 6,
797 LED_CTL_POWER_OFF = 7,
798 LED_CTL_START_TO_LINK = 8,
799 LED_CTL_START_WPS = 9,
800 LED_CTL_STOP_WPS = 10,
811 /*acm implementation method.*/
813 eAcmWay0_SwAndHw = 0,
819 SINGLEMAC_SINGLEPHY = 0,
832 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
846 WIRELESS_MODE_UNKNOWN = 0x00,
847 WIRELESS_MODE_A = 0x01,
848 WIRELESS_MODE_B = 0x02,
849 WIRELESS_MODE_G = 0x04,
850 WIRELESS_MODE_AUTO = 0x08,
851 WIRELESS_MODE_N_24G = 0x10,
852 WIRELESS_MODE_N_5G = 0x20,
853 WIRELESS_MODE_AC_5G = 0x40,
854 WIRELESS_MODE_AC_24G = 0x80,
855 WIRELESS_MODE_AC_ONLY = 0x100,
856 WIRELESS_MODE_MAX = 0x800
859 #define IS_WIRELESS_MODE_A(wirelessmode) \
860 (wirelessmode == WIRELESS_MODE_A)
861 #define IS_WIRELESS_MODE_B(wirelessmode) \
862 (wirelessmode == WIRELESS_MODE_B)
863 #define IS_WIRELESS_MODE_G(wirelessmode) \
864 (wirelessmode == WIRELESS_MODE_G)
865 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
866 (wirelessmode == WIRELESS_MODE_N_24G)
867 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
868 (wirelessmode == WIRELESS_MODE_N_5G)
870 enum ratr_table_mode {
871 RATR_INX_WIRELESS_NGB = 0,
872 RATR_INX_WIRELESS_NG = 1,
873 RATR_INX_WIRELESS_NB = 2,
874 RATR_INX_WIRELESS_N = 3,
875 RATR_INX_WIRELESS_GB = 4,
876 RATR_INX_WIRELESS_G = 5,
877 RATR_INX_WIRELESS_B = 6,
878 RATR_INX_WIRELESS_MC = 7,
879 RATR_INX_WIRELESS_A = 8,
880 RATR_INX_WIRELESS_AC_5N = 8,
881 RATR_INX_WIRELESS_AC_24N = 9,
884 enum rtl_link_state {
886 MAC80211_LINKING = 1,
888 MAC80211_LINKED_SCANNING = 3,
905 enum rt_polarity_ctl {
906 RT_POLARITY_LOW_ACT = 0,
907 RT_POLARITY_HIGH_ACT = 1,
910 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
911 enum fw_wow_reason_v2 {
912 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
913 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
914 FW_WOW_V2_DISASSOC_EVENT = 0x04,
915 FW_WOW_V2_DEAUTH_EVENT = 0x08,
916 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
917 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
918 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
919 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
920 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
921 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
922 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
923 FW_WOW_V2_REASON_MAX = 0xff,
926 enum wolpattern_type {
928 MULTICAST_PATTERN = 1,
929 BROADCAST_PATTERN = 2,
934 struct octet_string {
939 struct rtl_hdr_3addr {
949 struct rtl_info_element {
955 struct rtl_probe_rsp {
956 struct rtl_hdr_3addr header;
958 __le16 beacon_interval;
960 /*SSID, supported rates, FH params, DS params,
961 CF params, IBSS params, TIM (if beacon), RSN */
962 struct rtl_info_element info_element[0];
966 /*ledpin Identify how to implement this SW led.*/
969 enum rtl_led_pin ledpin;
975 struct rtl_led sw_led0;
976 struct rtl_led sw_led1;
979 struct rtl_qos_parameters {
987 struct rt_smooth_data {
988 u32 elements[100]; /*array to store values */
989 u32 index; /*index to current array to store */
990 u32 total_num; /*num of valid elements */
991 u32 total_val; /*sum of valid elements */
994 struct false_alarm_statistics {
996 u32 cnt_rate_illegal;
999 u32 cnt_fast_fsync_fail;
1000 u32 cnt_sb_search_fail;
1020 struct wireless_stats {
1021 unsigned long txbytesunicast;
1022 unsigned long txbytesmulticast;
1023 unsigned long txbytesbroadcast;
1024 unsigned long rxbytesunicast;
1027 /*Correct smoothed ss in Dbm, only used
1028 in driver to report real power now. */
1029 long recv_signal_power;
1030 long signal_quality;
1031 long last_sigstrength_inpercent;
1033 u32 rssi_calculate_cnt;
1036 /*Transformed, in dbm. Beautified signal
1037 strength for UI, not correct. */
1038 long signal_strength;
1040 u8 rx_rssi_percentage[4];
1042 u8 rx_evm_percentage[2];
1044 u16 rx_cfo_short[4];
1047 struct rt_smooth_data ui_rssi;
1048 struct rt_smooth_data ui_link_quality;
1051 struct rate_adaptive {
1052 u8 rate_adaptive_disabled;
1056 u32 high_rssi_thresh_for_ra;
1057 u32 high2low_rssi_thresh_for_ra;
1058 u8 low2high_rssi_thresh_for_ra40m;
1059 u32 low_rssi_thresh_for_ra40m;
1060 u8 low2high_rssi_thresh_for_ra20m;
1061 u32 low_rssi_thresh_for_ra20m;
1062 u32 upper_rssi_threshold_ratr;
1063 u32 middleupper_rssi_threshold_ratr;
1064 u32 middle_rssi_threshold_ratr;
1065 u32 middlelow_rssi_threshold_ratr;
1066 u32 low_rssi_threshold_ratr;
1067 u32 ultralow_rssi_threshold_ratr;
1068 u32 low_rssi_threshold_ratr_40m;
1069 u32 low_rssi_threshold_ratr_20m;
1070 u8 ping_rssi_enable;
1072 u32 ping_rssi_thresh_for_ra;
1077 bool lower_rts_rate;
1078 bool is_special_data;
1081 struct regd_pair_mapping {
1087 struct dynamic_primary_cca {
1097 struct rtl_regulatory {
1100 u16 max_power_level;
1104 int16_t power_limit;
1105 struct regd_pair_mapping *regpair;
1109 bool rfkill_state; /*0 is off, 1 is on */
1113 #define P2P_MAX_NOA_NUM 2
1116 P2P_ROLE_DISABLE = 0,
1117 P2P_ROLE_DEVICE = 1,
1118 P2P_ROLE_CLIENT = 2,
1126 P2P_PS_SCAN_DONE = 3,
1127 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1132 P2P_PS_CTWINDOW = 1,
1134 P2P_PS_MIX = 3, /* CTWindow and NoA */
1137 struct rtl_p2p_ps_info {
1138 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1139 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1140 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1141 /* Client traffic window. A period of time in TU after TBTT. */
1143 u8 opp_ps; /* opportunistic power save. */
1144 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1145 /* Count for owner, Type of client. */
1146 u8 noa_count_type[P2P_MAX_NOA_NUM];
1147 /* Max duration for owner, preferred or min acceptable duration
1150 u32 noa_duration[P2P_MAX_NOA_NUM];
1151 /* Length of interval for owner, preferred or max acceptable intervali
1154 u32 noa_interval[P2P_MAX_NOA_NUM];
1155 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1156 u32 noa_start_time[P2P_MAX_NOA_NUM];
1159 struct p2p_ps_offload_t {
1161 u8 role:1; /* 1: Owner, 0: Client */
1170 #define IQK_MATRIX_REG_NUM 8
1171 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1173 struct iqk_matrix_regs {
1175 long value[1][IQK_MATRIX_REG_NUM];
1178 struct phy_parameters {
1183 enum hw_param_tab_index {
1198 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1199 struct init_gain initgain_backup;
1200 enum io_type current_io_type;
1205 u8 set_bwmode_inprogress;
1206 u8 sw_chnl_inprogress;
1211 u8 set_io_inprogress;
1214 /* record for power tracking */
1226 u32 reg_c04, reg_c08, reg_874;
1227 u32 adda_backup[16];
1228 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1229 u32 iqk_bb_backup[10];
1230 bool iqk_initialized;
1232 bool rfpath_rx_enable[MAX_RF_PATH];
1236 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1239 bool iqk_in_progress;
1243 /* this is for 88E & 8723A */
1244 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1245 /* MAX_PG_GROUP groups of pwr diff by rates */
1246 u32 mcs_offset[MAX_PG_GROUP][16];
1247 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1248 [TX_PWR_BY_RATE_NUM_RF]
1249 [TX_PWR_BY_RATE_NUM_RF]
1250 [TX_PWR_BY_RATE_NUM_SECTION];
1251 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1252 [TX_PWR_BY_RATE_NUM_RF]
1253 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1254 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1255 [TX_PWR_BY_RATE_NUM_RF]
1256 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1257 u8 default_initialgain[4];
1259 /* the current Tx power level */
1260 u8 cur_cck_txpwridx;
1261 u8 cur_ofdm24g_txpwridx;
1262 u8 cur_bw20_txpwridx;
1263 u8 cur_bw40_txpwridx;
1265 char txpwr_limit_2_4g[MAX_REGULATION_NUM]
1266 [MAX_2_4G_BANDWITH_NUM]
1267 [MAX_RATE_SECTION_NUM]
1268 [CHANNEL_MAX_NUMBER_2G]
1270 char txpwr_limit_5g[MAX_REGULATION_NUM]
1271 [MAX_5G_BANDWITH_NUM]
1272 [MAX_RATE_SECTION_NUM]
1273 [CHANNEL_MAX_NUMBER_5G]
1276 u32 rfreg_chnlval[2];
1278 u32 reg_rf3c[2]; /* pathA / pathB */
1280 u32 backup_rf_0x1a;/*92ee*/
1285 u8 num_total_rfpath;
1286 struct phy_parameters hwparam_tables[MAX_TAB];
1289 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1290 enum rt_polarity_ctl polarity_ctl;
1293 #define MAX_TID_COUNT 9
1294 #define RTL_AGG_STOP 0
1295 #define RTL_AGG_PROGRESS 1
1296 #define RTL_AGG_START 2
1297 #define RTL_AGG_OPERATIONAL 3
1298 #define RTL_AGG_OFF 0
1299 #define RTL_AGG_ON 1
1300 #define RTL_RX_AGG_START 1
1301 #define RTL_RX_AGG_STOP 0
1302 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1303 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1320 struct rtl_tid_data {
1322 struct rtl_ht_agg agg;
1325 struct rtl_sta_info {
1326 struct list_head list;
1330 u8 mac_addr[ETH_ALEN];
1331 struct rtl_tid_data tids[MAX_TID_COUNT];
1333 /* just used for ap adhoc or mesh*/
1334 struct rssi_sta rssi_stat;
1340 struct mutex bb_mutex;
1343 unsigned long pci_mem_end; /*shared mem end */
1344 unsigned long pci_mem_start; /*shared mem start */
1347 unsigned long pci_base_addr; /*device I/O address */
1349 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1350 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1351 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1352 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1355 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1356 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1357 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1362 u8 mac_addr[ETH_ALEN];
1363 u8 mac80211_registered;
1369 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1370 struct ieee80211_hw *hw;
1371 struct ieee80211_vif *vif;
1372 enum nl80211_iftype opmode;
1374 /*Probe Beacon management */
1375 struct rtl_tid_data tids[MAX_TID_COUNT];
1376 enum rtl_link_state link_state;
1382 u8 p2p; /*using p2p role*/
1392 u8 cnt_after_linked;
1396 /* skb wait queue */
1397 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1414 u8 bssid[ETH_ALEN] __aligned(2);
1416 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1417 u32 basic_rates; /* b/g rates */
1422 u16 mode; /* wireless mode */
1427 u8 cur_40_prime_sc_bk;
1436 int beacon_interval;
1439 u8 min_space_cfg; /*For Min spacing configurations */
1441 u8 current_ampdu_factor;
1442 u8 current_ampdu_density;
1445 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1446 struct rtl_qos_parameters ac[AC_MAX];
1451 u32 last_bt_edca_ul;
1452 u32 last_bt_edca_dl;
1458 bool adc_back_off_on;
1460 bool low_penalty_rate_adaptive;
1461 bool rf_rx_lpf_shrink;
1462 bool reject_aggre_pkt;
1470 u8 fw_dac_swing_lvl;
1477 bool sw_dac_swing_on;
1478 u32 sw_dac_swing_lvl;
1483 bool ignore_wlan_act;
1486 struct bt_coexist_8723 {
1487 u32 high_priority_tx;
1488 u32 high_priority_rx;
1489 u32 low_priority_tx;
1490 u32 low_priority_rx;
1492 bool c2h_bt_info_req_sent;
1493 bool c2h_bt_inquiry_page;
1494 u32 bt_inq_page_start_time;
1496 u8 c2h_bt_info_original;
1497 u8 bt_inquiry_page_cnt;
1498 struct btdm_8723 btdm;
1502 struct ieee80211_hw *hw;
1503 bool driver_is_goingto_unload;
1506 bool being_init_adapter;
1508 bool mac_func_enable;
1509 bool pre_edcca_enable;
1510 struct bt_coexist_8723 hal_coex_8723;
1512 enum intf_type interface;
1513 u16 hw_type; /*92c or 92d or 92s and so on */
1516 u32 version; /*version of chip */
1517 u8 state; /*stop 0, start 1 */
1537 bool h2c_setinprogress;
1540 /*Reserve page start offset except beacon in TxQ. */
1541 u8 fw_rsvdpage_startoffset;
1545 /* FW Cmd IO related */
1548 bool set_fwcmd_inprogress;
1549 u8 current_fwcmd_io;
1551 struct p2p_ps_offload_t p2p_ps_offload;
1552 bool fw_clk_change_in_progress;
1553 bool allow_sw_to_change_hwclc;
1556 bool driver_going2unload;
1558 /*AMPDU init min space*/
1559 u8 minspace_cfg; /*For Min spacing configurations */
1562 enum macphy_mode macphymode;
1563 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1564 enum band_type current_bandtypebackup;
1565 enum band_type bandset;
1566 /* dual MAC 0--Mac0 1--Mac1 */
1568 /* just for DualMac S3S4 */
1570 bool earlymode_enable;
1571 u8 max_earlymode_num;
1573 bool during_mac0init_radiob;
1574 bool during_mac1init_radioa;
1575 bool reloadtxpowerindex;
1576 /* True if IMR or IQK have done
1577 for 2.4G in scan progress */
1578 bool load_imrandiqk_setting_for2g;
1580 bool disable_amsdu_8k;
1581 bool master_of_dmsp;
1584 u16 rx_tag;/*for 92ee*/
1589 bool enter_pnp_sleep;
1590 bool wake_from_pnp_sleep;
1592 __kernel_time_t last_suspend_sec;
1594 u8 *wowlan_firmware;
1596 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1598 bool real_wow_v2_enable;
1599 bool re_init_llt_table;
1602 struct rtl_security {
1607 bool use_defaultkey;
1608 /*Encryption Algorithm for Unicast Packet */
1609 enum rt_enc_alg pairwise_enc_algorithm;
1610 /*Encryption Algorithm for Brocast/Multicast */
1611 enum rt_enc_alg group_enc_algorithm;
1612 /*Cam Entry Bitmap */
1613 u32 hwsec_cam_bitmap;
1614 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1615 /*local Key buffer, indx 0 is for
1616 pairwise key 1-4 is for agoup key. */
1617 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1618 u8 key_len[KEY_BUF_SIZE];
1620 /*The pointer of Pairwise Key,
1621 it always points to KeyBuf[4] */
1625 #define ASSOCIATE_ENTRY_NUM 33
1627 struct fast_ant_training {
1629 u8 antsel_rx_keep_0;
1630 u8 antsel_rx_keep_1;
1631 u8 antsel_rx_keep_2;
1637 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1638 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1639 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1640 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1641 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1642 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1643 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1648 struct dm_phy_dbg_info {
1650 u64 num_qry_phy_status;
1651 u64 num_qry_phy_status_cck;
1652 u64 num_qry_phy_status_ofdm;
1653 u16 num_qry_beacon_pkt;
1659 /*PHY status for Dynamic Management */
1660 long entry_min_undec_sm_pwdb;
1662 long undec_sm_pwdb; /*out dm */
1663 long entry_max_undec_sm_pwdb;
1665 bool dm_initialgain_enable;
1666 bool dynamic_txpower_enable;
1667 bool current_turbo_edca;
1668 bool is_any_nonbepkts; /*out dm */
1669 bool is_cur_rdlstate;
1670 bool txpower_trackinginit;
1671 bool disable_framebursting;
1673 bool txpower_tracking;
1675 bool rfpath_rxenable[4];
1676 bool inform_fw_driverctrldm;
1677 bool current_mrc_switch;
1679 u8 powerindex_backup[6];
1681 u8 thermalvalue_rxgain;
1682 u8 thermalvalue_iqk;
1683 u8 thermalvalue_lck;
1686 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1687 u8 thermalvalue_avg_index;
1690 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1691 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1695 u8 txpower_track_control;
1696 bool interrupt_migration;
1697 bool disable_tx_int;
1698 char ofdm_index[MAX_RF_PATH];
1699 u8 default_ofdm_index;
1700 u8 default_cck_index;
1702 char delta_power_index[MAX_RF_PATH];
1703 char delta_power_index_last[MAX_RF_PATH];
1704 char power_index_offset[MAX_RF_PATH];
1705 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1706 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1707 char remnant_cck_idx;
1708 bool modify_txagc_flag_path_a;
1709 bool modify_txagc_flag_path_b;
1711 bool one_entry_only;
1712 struct dm_phy_dbg_info dbginfo;
1714 /* Dynamic ATC switch */
1723 u32 packet_count_pre;
1726 /*88e tx power tracking*/
1727 u8 swing_idx_ofdm[MAX_RF_PATH];
1728 u8 swing_idx_ofdm_cur;
1729 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1730 bool swing_flag_ofdm;
1732 u8 swing_idx_cck_cur;
1733 u8 swing_idx_cck_base;
1734 bool swing_flag_cck;
1739 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1740 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1741 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1742 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1743 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1744 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1745 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1746 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1747 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1748 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1749 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1750 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1751 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1752 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1755 bool supp_phymode_switch;
1758 struct fast_ant_training fat_table;
1775 #define EFUSE_MAX_LOGICAL_SIZE 512
1780 u16 max_physical_size;
1782 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1783 u16 efuse_usedbytes;
1784 u8 efuse_usedpercentage;
1785 #ifdef EFUSE_REPG_WORKAROUND
1786 bool efuse_re_pg_sec1flag;
1787 u8 efuse_re_pg_data[8];
1790 u8 autoload_failflag;
1799 u16 eeprom_channelplan;
1807 u8 antenna_div_type;
1809 bool txpwr_fromeprom;
1810 u8 eeprom_crystalcap;
1812 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1813 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1814 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1815 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1816 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1817 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1819 u8 internal_pa_5g[2]; /* pathA / pathB */
1823 /*For power group */
1824 u8 eeprom_pwrgroup[2][3];
1825 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1826 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1828 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1829 /*For HT 40MHZ pwr */
1830 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1831 /*For HT 40MHZ pwr */
1832 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1834 /*--------------------------------------------------------*
1835 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1836 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1837 * define new arrays in Windows code.
1838 * BUT, in linux code, we use the same array for all ICs.
1840 * The Correspondance relation between two arrays is:
1841 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1842 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1843 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1844 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1846 * Sizes of these arrays are decided by the larger ones.
1848 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1849 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1850 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1851 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1853 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1854 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1855 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1856 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1857 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1858 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1860 u8 txpwr_safetyflag; /* Band edge enable flag */
1861 u16 eeprom_txpowerdiff;
1862 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1863 u8 antenna_txpwdiff[3];
1865 u8 eeprom_regulatory;
1866 u8 eeprom_thermalmeter;
1867 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1869 u8 crystalcap; /* CrystalCap. */
1873 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1874 bool apk_thermalmeterignore;
1876 bool b1x1_recvcombine;
1884 bool pwrdomain_protect;
1885 bool in_powersavemode;
1886 bool rfchange_inprogress;
1887 bool swrf_processing;
1890 * just for PCIE ASPM
1891 * If it supports ASPM, Offset[560h] = 0x40,
1892 * otherwise Offset[560h] = 0x00.
1895 bool support_backdoor;
1898 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1903 /*For Fw control LPS mode */
1905 /*Record Fw PS mode status. */
1906 bool fw_current_inpsmode;
1907 u8 reg_max_lps_awakeintvl;
1909 bool low_power_enable;/*for 32k*/
1920 /*just for PCIE ASPM */
1921 u8 const_amdpci_aspm;
1924 enum rf_pwrstate inactive_pwrstate;
1925 enum rf_pwrstate rfpwr_state; /*cur power state */
1931 bool multi_buffered;
1933 unsigned int dtim_counter;
1934 unsigned int sleep_ms;
1935 unsigned long last_sleep_jiffies;
1936 unsigned long last_awake_jiffies;
1937 unsigned long last_delaylps_stamp_jiffies;
1938 unsigned long last_dtim;
1939 unsigned long last_beacon;
1940 unsigned long last_action;
1941 unsigned long last_slept;
1944 struct rtl_p2p_ps_info p2p_ps_info;
1948 /* wake up on line */
1950 u8 arp_offload_enable;
1951 u8 gtk_offload_enable;
1952 /* Used for WOL, indicates the reason for waking event.*/
1954 /* Record the last waking time for comparison with setting key. */
1955 u64 last_wakeup_time;
1959 u8 psaddr[ETH_ALEN];
1964 u8 rate; /* hw desc rate */
1965 u8 received_channel;
1974 u8 signalquality; /*in 0-100 index. */
1976 * Real power in dBm for this packet,
1977 * no beautification and aggregation.
1979 s32 recvsignalpower;
1980 s8 rxpower; /*in dBm Translate from PWdB */
1981 u8 signalstrength; /*in 0-100 index. */
1985 u16 shortpreamble:1;
1997 bool rx_is40Mhzpacket;
2000 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2001 s8 rx_mimo_signalquality[4];
2002 u8 rx_mimo_evm_dbm[4];
2003 u16 cfo_short[4]; /* per-path's Cfo_short */
2006 s8 rx_mimo_sig_qual[4];
2007 u8 rx_pwr[4]; /* per-path's pwdb */
2008 u8 rx_snr[4]; /* per-path's SNR */
2010 u8 bt_coex_pwr_adjust;
2011 bool packet_matchbssid;
2015 bool packet_beacon; /*for rssi */
2016 char cck_adc_pwdb[4]; /*for rx path selection */
2022 u8 packet_report_type;
2026 u32 bt_rx_rssi_percentage;
2027 u32 macid_valid_entry[2];
2031 struct rt_link_detect {
2032 /* count for roaming */
2033 u32 bcn_rx_inperiod;
2036 u32 num_tx_in4period[4];
2037 u32 num_rx_in4period[4];
2039 u32 num_tx_inperiod;
2040 u32 num_rx_inperiod;
2043 bool tx_busy_traffic;
2044 bool rx_busy_traffic;
2045 bool higher_busytraffic;
2046 bool higher_busyrxtraffic;
2048 u32 tidtx_in4period[MAX_TID_COUNT][4];
2049 u32 tidtx_inperiod[MAX_TID_COUNT];
2050 bool higher_busytxtraffic[MAX_TID_COUNT];
2053 struct rtl_tcb_desc {
2061 u8 rts_use_shortpreamble:1;
2062 u8 rts_use_shortgi:1;
2068 u8 use_shortpreamble:1;
2069 u8 use_driver_rate:1;
2070 u8 disable_ratefallback:1;
2082 /* The max value by HW */
2084 bool tx_enable_sw_calc_duration;
2087 struct rtl_wow_pattern {
2093 struct rtl_hal_ops {
2094 int (*init_sw_vars) (struct ieee80211_hw *hw);
2095 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2096 void (*read_chip_version)(struct ieee80211_hw *hw);
2097 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2098 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2099 u32 *p_inta, u32 *p_intb);
2100 int (*hw_init) (struct ieee80211_hw *hw);
2101 void (*hw_disable) (struct ieee80211_hw *hw);
2102 void (*hw_suspend) (struct ieee80211_hw *hw);
2103 void (*hw_resume) (struct ieee80211_hw *hw);
2104 void (*enable_interrupt) (struct ieee80211_hw *hw);
2105 void (*disable_interrupt) (struct ieee80211_hw *hw);
2106 int (*set_network_type) (struct ieee80211_hw *hw,
2107 enum nl80211_iftype type);
2108 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2110 void (*set_bw_mode) (struct ieee80211_hw *hw,
2111 enum nl80211_channel_type ch_type);
2112 u8(*switch_channel) (struct ieee80211_hw *hw);
2113 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2114 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2115 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2116 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2117 u32 add_msr, u32 rm_msr);
2118 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2119 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2120 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2121 struct ieee80211_sta *sta, u8 rssi_level);
2122 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2123 u8 *desc, u8 queue_index,
2124 struct sk_buff *skb, dma_addr_t addr);
2125 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2126 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2128 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2130 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2131 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2133 struct ieee80211_tx_info *info,
2134 struct ieee80211_sta *sta,
2135 struct sk_buff *skb, u8 hw_queue,
2136 struct rtl_tcb_desc *ptcb_desc);
2137 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2138 u32 buffer_len, bool bIsPsPoll);
2139 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2140 bool firstseg, bool lastseg,
2141 struct sk_buff *skb);
2142 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2143 struct rtl_stats *stats,
2144 struct ieee80211_rx_status *rx_status,
2145 u8 *pdesc, struct sk_buff *skb);
2146 void (*set_channel_access) (struct ieee80211_hw *hw);
2147 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2148 void (*dm_watchdog) (struct ieee80211_hw *hw);
2149 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2150 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2151 enum rf_pwrstate rfpwr_state);
2152 void (*led_control) (struct ieee80211_hw *hw,
2153 enum led_ctl_mode ledaction);
2154 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2155 u8 desc_name, u8 *val);
2156 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2157 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2158 u8 hw_queue, u16 index);
2159 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2160 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2161 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2162 u8 *macaddr, bool is_group, u8 enc_algo,
2163 bool is_wepkey, bool clear_all);
2164 void (*init_sw_leds) (struct ieee80211_hw *hw);
2165 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2166 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2167 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2169 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2170 u32 regaddr, u32 bitmask);
2171 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2172 u32 regaddr, u32 bitmask, u32 data);
2173 void (*linked_set_reg) (struct ieee80211_hw *hw);
2174 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2175 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2176 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2177 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2178 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2180 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2181 u8 *ppowerlevel, u8 channel);
2182 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2184 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2186 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2187 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2188 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2189 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2190 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2192 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2193 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2194 u32 cmd_len, u8 *p_cmdbuffer);
2195 bool (*get_btc_status) (void);
2196 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2197 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2198 struct rtl_stats status, struct sk_buff *skb);
2199 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2200 struct rtl_wow_pattern *rtl_pattern,
2202 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2205 struct rtl_intf_ops {
2207 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2208 int (*adapter_start) (struct ieee80211_hw *hw);
2209 void (*adapter_stop) (struct ieee80211_hw *hw);
2210 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2211 struct rtl_priv **buddy_priv);
2213 int (*adapter_tx) (struct ieee80211_hw *hw,
2214 struct ieee80211_sta *sta,
2215 struct sk_buff *skb,
2216 struct rtl_tcb_desc *ptcb_desc);
2217 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2218 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2219 bool (*waitq_insert) (struct ieee80211_hw *hw,
2220 struct ieee80211_sta *sta,
2221 struct sk_buff *skb);
2224 void (*disable_aspm) (struct ieee80211_hw *hw);
2225 void (*enable_aspm) (struct ieee80211_hw *hw);
2230 struct rtl_mod_params {
2231 /* default: 0 = using hardware encryption */
2234 /* default: 0 = DBG_EMERG (0)*/
2237 /* default: 1 = using no linked power save */
2240 /* default: 1 = using linked sw power save */
2243 /* default: 1 = using linked fw power save */
2246 /* default: 0 = not using MSI interrupts mode
2247 * submodules should set their own default value
2251 /* default 0: 1 means disable */
2252 bool disable_watchdog;
2254 /* default 0: 1 means do not disable interrupts */
2257 /* select antenna */
2261 struct rtl_hal_usbint_cfg {
2268 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2269 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2270 struct sk_buff_head *);
2273 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2274 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2276 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2277 struct sk_buff_head *);
2279 /* endpoint mapping */
2280 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2281 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2284 struct rtl_hal_cfg {
2286 bool write_readback;
2290 char *wowlan_fw_name;
2291 struct rtl_hal_ops *ops;
2292 struct rtl_mod_params *mod_params;
2293 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2295 /*this map used for some registers or vars
2296 defined int HAL but used in MAIN */
2297 u32 maps[RTL_VAR_MAP_MAX];
2303 struct mutex conf_mutex;
2304 struct mutex ps_mutex;
2307 spinlock_t ips_lock;
2308 spinlock_t irq_th_lock;
2309 spinlock_t irq_pci_lock;
2311 spinlock_t h2c_lock;
2312 spinlock_t rf_ps_lock;
2314 spinlock_t lps_lock;
2315 spinlock_t waitq_lock;
2316 spinlock_t entry_list_lock;
2317 spinlock_t usb_lock;
2319 /*FW clock change */
2320 spinlock_t fw_ps_lock;
2323 spinlock_t cck_and_rw_pagea_lock;
2326 spinlock_t check_sendpkt_lock;
2328 spinlock_t iqk_lock;
2332 struct ieee80211_hw *hw;
2335 struct timer_list watchdog_timer;
2336 struct timer_list dualmac_easyconcurrent_retrytimer;
2337 struct timer_list fw_clockoff_timer;
2338 struct timer_list fast_antenna_training_timer;
2340 struct tasklet_struct irq_tasklet;
2341 struct tasklet_struct irq_prepare_bcn_tasklet;
2344 struct workqueue_struct *rtl_wq;
2345 struct delayed_work watchdog_wq;
2346 struct delayed_work ips_nic_off_wq;
2349 struct delayed_work ps_work;
2350 struct delayed_work ps_rfon_wq;
2351 struct delayed_work fwevt_wq;
2353 struct work_struct lps_change_work;
2354 struct work_struct fill_h2c_cmd;
2358 u32 dbgp_type[DBGP_TYPE_MAX];
2359 int global_debuglevel;
2360 u64 global_debugcomponents;
2362 /* add for proc debug */
2363 struct proc_dir_entry *proc_dir;
2367 #define MIMO_PS_STATIC 0
2368 #define MIMO_PS_DYNAMIC 1
2369 #define MIMO_PS_NOLIMIT 3
2371 struct rtl_dualmac_easy_concurrent_ctl {
2372 enum band_type currentbandtype_backfordmdp;
2373 bool close_bbandrf_for_dmsp;
2374 bool change_to_dmdp;
2375 bool change_to_dmsp;
2376 bool switch_in_process;
2379 struct rtl_dmsp_ctl {
2380 bool activescan_for_slaveofdmsp;
2381 bool scan_for_anothermac_fordmsp;
2382 bool scan_for_itself_fordmsp;
2383 bool writedig_for_anothermacofdmsp;
2384 u32 curdigvalue_for_anothermacofdmsp;
2385 bool changecckpdstate_for_anothermacofdmsp;
2386 u8 curcckpdstate_for_anothermacofdmsp;
2387 bool changetxhighpowerlvl_for_anothermacofdmsp;
2388 u8 curtxhighlvl_for_anothermacofdmsp;
2389 long rssivalmin_for_anothermacofdmsp;
2403 u32 rssi_highthresh;
2406 long last_min_undec_pwdb_for_dm;
2407 long rssi_highpower_lowthresh;
2408 long rssi_highpower_highthresh;
2414 u8 dig_ext_port_stage;
2416 u8 dig_twoport_algorithm;
2418 u8 dig_slgorithm_switch;
2421 u8 curmultista_cstate;
2424 char back_range_max;
2425 char back_range_min;
2428 u8 min_undec_pwdb_for_dm;
2430 u8 pre_cck_cca_thres;
2431 u8 cur_cck_cca_thres;
2432 u8 pre_cck_pd_state;
2433 u8 cur_cck_pd_state;
2434 u8 pre_cck_fa_state;
2435 u8 cur_cck_fa_state;
2441 u8 dig_highpwrstate;
2448 u8 cur_cs_ratiostate;
2449 u8 pre_cs_ratiostate;
2450 u8 backoff_enable_flag;
2451 char backoffval_range_max;
2452 char backoffval_range_min;
2456 bool media_connect_0;
2457 bool media_connect_1;
2459 u32 antdiv_rssi_max;
2463 struct rtl_global_var {
2464 /* from this list we can get
2465 * other adapter's rtl_priv */
2466 struct list_head glb_priv_list;
2467 spinlock_t glb_list_lock;
2470 struct rtl_btc_info {
2476 struct bt_coexist_info {
2477 struct rtl_btc_ops *btc_ops;
2478 struct rtl_btc_info btc_info;
2479 /* EEPROM BT info. */
2480 u8 eeprom_bt_coexist;
2482 u8 eeprom_bt_ant_num;
2483 u8 eeprom_bt_ant_isol;
2484 u8 eeprom_bt_radio_shared;
2490 u8 bt_cur_state; /* 0:on, 1:off */
2491 u8 bt_ant_isolation; /* 0:good, 1:bad */
2492 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2494 u8 bt_radio_shared_type;
2495 u8 bt_rfreg_origin_1e;
2496 u8 bt_rfreg_origin_1f;
2504 bool bt_busy_traffic;
2505 bool bt_traffic_mode_set;
2506 bool bt_non_traffic_mode_set;
2508 bool fw_coexist_all_off;
2509 bool sw_coexist_all_off;
2510 bool hw_coexist_all_off;
2514 u32 previous_state_h;
2516 u8 bt_pre_rssi_state;
2517 u8 bt_pre_rssi_state1;
2522 u8 bt_active_zero_cnt;
2523 bool cur_bt_disabled;
2524 bool pre_bt_disabled;
2527 u8 bt_profile_action;
2529 bool hold_for_bt_operation;
2533 struct rtl_btc_ops {
2534 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2535 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2536 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2537 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2538 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2539 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2540 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2541 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2542 enum rt_media_status mstatus);
2543 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2544 void (*btc_halt_notify) (void);
2545 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2546 u8 *tmp_buf, u8 length);
2547 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2548 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2549 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2550 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2557 void *proximity_priv;
2558 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2559 struct sk_buff *skb);
2560 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2564 struct ieee80211_hw *hw;
2565 struct completion firmware_loading_complete;
2566 struct list_head list;
2567 struct rtl_priv *buddy_priv;
2568 struct rtl_global_var *glb_var;
2569 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2570 struct rtl_dmsp_ctl dmsp_ctl;
2571 struct rtl_locks locks;
2572 struct rtl_works works;
2573 struct rtl_mac mac80211;
2574 struct rtl_hal rtlhal;
2575 struct rtl_regulatory regd;
2576 struct rtl_rfkill rfkill;
2580 struct rtl_security sec;
2581 struct rtl_efuse efuse;
2583 struct rtl_ps_ctl psc;
2584 struct rate_adaptive ra;
2585 struct dynamic_primary_cca primarycca;
2586 struct wireless_stats stats;
2587 struct rt_link_detect link_info;
2588 struct false_alarm_statistics falsealm_cnt;
2590 struct rtl_rate_priv *rate_priv;
2592 /* sta entry list for ap adhoc or mesh */
2593 struct list_head entry_list;
2595 struct rtl_debug dbg;
2599 *hal_cfg : for diff cards
2600 *intf_ops : for diff interrface usb/pcie
2602 struct rtl_hal_cfg *cfg;
2603 struct rtl_intf_ops *intf_ops;
2605 /*this var will be set by set_bit,
2606 and was used to indicate status of
2607 interface or hardware */
2608 unsigned long status;
2611 struct dig_t dm_digtable;
2612 struct ps_t dm_pstable;
2618 bool reg_init; /* true if regs saved */
2619 bool bt_operation_on;
2623 bool enter_ps; /* true when entering PS */
2626 /* intel Proximity, should be alloc mem
2627 * in intel Proximity module and can only
2628 * be used in intel Proximity mode
2630 struct proxim proximity;
2632 /*for bt coexist use*/
2633 struct bt_coexist_info btcoexist;
2635 /* separate 92ee from other ICs,
2636 * 92ee use new trx flow.
2638 bool use_new_trx_flow;
2641 struct wiphy_wowlan_support wowlan;
2643 /*This must be the last item so
2644 that it points to the data allocated
2645 beyond this structure like:
2646 rtl_pci_priv or rtl_usb_priv */
2647 u8 priv[0] __aligned(sizeof(void *));
2650 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2651 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2652 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2653 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2654 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2657 /***************************************
2658 Bluetooth Co-existence Related
2659 ****************************************/
2680 enum bt_total_ant_num {
2690 enum bt_service_type {
2697 BT_OTHER_ACTION = 6,
2703 enum bt_radio_shared {
2704 BT_RADIO_SHARED = 0,
2705 BT_RADIO_INDIVIDUAL = 1,
2709 /****************************************
2710 mem access macro define start
2711 Call endian free function when
2712 1. Read/write packet content.
2713 2. Before write integer to IO.
2714 3. After read integer from IO.
2715 ****************************************/
2716 /* Convert little data endian to host ordering */
2717 #define EF1BYTE(_val) \
2719 #define EF2BYTE(_val) \
2721 #define EF4BYTE(_val) \
2724 /* Read data from memory */
2725 #define READEF1BYTE(_ptr) \
2726 EF1BYTE(*((u8 *)(_ptr)))
2727 /* Read le16 data from memory and convert to host ordering */
2728 #define READEF2BYTE(_ptr) \
2730 #define READEF4BYTE(_ptr) \
2733 /* Write data to memory */
2734 #define WRITEEF1BYTE(_ptr, _val) \
2735 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2736 /* Write le16 data to memory in host ordering */
2737 #define WRITEEF2BYTE(_ptr, _val) \
2738 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2739 #define WRITEEF4BYTE(_ptr, _val) \
2740 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2742 /* Create a bit mask
2744 * BIT_LEN_MASK_32(0) => 0x00000000
2745 * BIT_LEN_MASK_32(1) => 0x00000001
2746 * BIT_LEN_MASK_32(2) => 0x00000003
2747 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2749 #define BIT_LEN_MASK_32(__bitlen) \
2750 (0xFFFFFFFF >> (32 - (__bitlen)))
2751 #define BIT_LEN_MASK_16(__bitlen) \
2752 (0xFFFF >> (16 - (__bitlen)))
2753 #define BIT_LEN_MASK_8(__bitlen) \
2754 (0xFF >> (8 - (__bitlen)))
2756 /* Create an offset bit mask
2758 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2759 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2761 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2762 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2763 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2764 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2765 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2766 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2769 * Return 4-byte value in host byte ordering from
2770 * 4-byte pointer in little-endian system.
2772 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2773 (EF4BYTE(*((__le32 *)(__pstart))))
2774 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2775 (EF2BYTE(*((__le16 *)(__pstart))))
2776 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2777 (EF1BYTE(*((u8 *)(__pstart))))
2780 Translate subfield (continuous bits in little-endian) of 4-byte
2781 value to host byte ordering.*/
2782 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2784 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2785 BIT_LEN_MASK_32(__bitlen) \
2787 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2789 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2790 BIT_LEN_MASK_16(__bitlen) \
2792 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2794 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2795 BIT_LEN_MASK_8(__bitlen) \
2799 * Mask subfield (continuous bits in little-endian) of 4-byte value
2800 * and return the result in 4-byte value in host byte ordering.
2802 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2804 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2805 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2807 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2809 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2810 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2812 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2814 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2815 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2819 * Set subfield of little-endian 4-byte value to specified value.
2821 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2822 *((u32 *)(__pstart)) = \
2824 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2825 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2827 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2828 *((u16 *)(__pstart)) = \
2830 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2831 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2833 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2834 *((u8 *)(__pstart)) = EF1BYTE \
2836 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2837 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2840 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2841 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2843 /****************************************
2844 mem access macro define end
2845 ****************************************/
2847 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2849 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2850 #define RTL_WATCH_DOG_TIME 2000
2851 #define MSECS(t) msecs_to_jiffies(t)
2852 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2853 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2854 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2855 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2856 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2858 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2859 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2860 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2861 /*NIC halt, re-initialize hw parameters*/
2862 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2863 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2864 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2865 /*Always enable ASPM and Clock Req in initialization.*/
2866 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2867 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2868 #define RT_PS_LEVEL_ASPM BIT(7)
2869 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2870 #define RT_RF_LPS_DISALBE_2R BIT(30)
2871 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2872 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2873 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2874 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2875 (ppsc->cur_ps_level &= (~(_ps_flg)))
2876 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2877 (ppsc->cur_ps_level |= _ps_flg)
2879 #define container_of_dwork_rtl(x, y, z) \
2880 container_of(container_of(x, struct delayed_work, work), y, z)
2882 #define FILL_OCTET_STRING(_os, _octet, _len) \
2883 (_os).octet = (u8 *)(_octet); \
2884 (_os).length = (_len);
2886 #define CP_MACADDR(des, src) \
2887 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2888 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2889 (des)[4] = (src)[4], (des)[5] = (src)[5])
2891 #define LDPC_HT_ENABLE_RX BIT(0)
2892 #define LDPC_HT_ENABLE_TX BIT(1)
2893 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2894 #define LDPC_HT_CAP_TX BIT(3)
2896 #define STBC_HT_ENABLE_RX BIT(0)
2897 #define STBC_HT_ENABLE_TX BIT(1)
2898 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2899 #define STBC_HT_CAP_TX BIT(3)
2901 #define LDPC_VHT_ENABLE_RX BIT(0)
2902 #define LDPC_VHT_ENABLE_TX BIT(1)
2903 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2904 #define LDPC_VHT_CAP_TX BIT(3)
2906 #define STBC_VHT_ENABLE_RX BIT(0)
2907 #define STBC_VHT_ENABLE_TX BIT(1)
2908 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2909 #define STBC_VHT_CAP_TX BIT(3)
2911 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2913 return rtlpriv->io.read8_sync(rtlpriv, addr);
2916 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2918 return rtlpriv->io.read16_sync(rtlpriv, addr);
2921 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2923 return rtlpriv->io.read32_sync(rtlpriv, addr);
2926 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2928 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2930 if (rtlpriv->cfg->write_readback)
2931 rtlpriv->io.read8_sync(rtlpriv, addr);
2934 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2936 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2938 if (rtlpriv->cfg->write_readback)
2939 rtlpriv->io.read16_sync(rtlpriv, addr);
2942 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2943 u32 addr, u32 val32)
2945 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2947 if (rtlpriv->cfg->write_readback)
2948 rtlpriv->io.read32_sync(rtlpriv, addr);
2951 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2952 u32 regaddr, u32 bitmask)
2954 struct rtl_priv *rtlpriv = hw->priv;
2956 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2959 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2960 u32 bitmask, u32 data)
2962 struct rtl_priv *rtlpriv = hw->priv;
2964 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2967 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2968 enum radio_path rfpath, u32 regaddr,
2971 struct rtl_priv *rtlpriv = hw->priv;
2973 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2976 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2977 enum radio_path rfpath, u32 regaddr,
2978 u32 bitmask, u32 data)
2980 struct rtl_priv *rtlpriv = hw->priv;
2982 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2985 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2987 return (_HAL_STATE_STOP == rtlhal->state);
2990 static inline void set_hal_start(struct rtl_hal *rtlhal)
2992 rtlhal->state = _HAL_STATE_START;
2995 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2997 rtlhal->state = _HAL_STATE_STOP;
3000 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3002 return rtlphy->rf_type;
3005 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3007 return (struct ieee80211_hdr *)(skb->data);
3010 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3012 return rtl_get_hdr(skb)->frame_control;
3015 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3017 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3020 static inline u16 rtl_get_tid(struct sk_buff *skb)
3022 return rtl_get_tid_h(rtl_get_hdr(skb));
3025 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3026 struct ieee80211_vif *vif,
3029 return ieee80211_find_sta(vif, bssid);
3032 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3035 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3036 return ieee80211_find_sta(mac->vif, mac_addr);