1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
90 /*Max: define total number.*/
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102 #define ASPM_L1_LATENCY 7
104 #define TOTAL_CAM_ENTRY 32
106 /*slot time for 11g. */
107 #define RTL_SLOT_TIME_9 9
108 #define RTL_SLOT_TIME_20 20
110 /*related to tcp/ip. */
112 #define PROTOC_TYPE_SIZE 2
114 /*related with 802.11 frame*/
115 #define MAC80211_3ADDR_LEN 24
116 #define MAC80211_4ADDR_LEN 30
118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
119 #define CHANNEL_MAX_NUMBER_2G 14
120 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
121 *"phy_GetChnlGroup8812A" and
122 * "Hal_ReadTxPowerInfo8812A"
124 #define CHANNEL_MAX_NUMBER_5G_80M 7
125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
126 #define MAX_PG_GROUP 13
127 #define CHANNEL_GROUP_MAX_2G 3
128 #define CHANNEL_GROUP_IDX_5GL 3
129 #define CHANNEL_GROUP_IDX_5GM 6
130 #define CHANNEL_GROUP_IDX_5GH 9
131 #define CHANNEL_GROUP_MAX_5G 9
132 #define CHANNEL_MAX_NUMBER_2G 14
133 #define AVG_THERMAL_NUM 8
134 #define AVG_THERMAL_NUM_88E 4
135 #define AVG_THERMAL_NUM_8723BE 4
136 #define MAX_TID_COUNT 9
142 enum rtl8192c_h2c_cmd {
149 H2C_MACID_PS_MODE = 7,
150 H2C_P2P_PS_OFFLOAD = 8,
151 H2C_MAC_MODE_SEL = 9,
153 H2C_P2P_PS_CTW_CMD = 24,
157 #define MAX_TX_COUNT 4
158 #define MAX_REGULATION_NUM 4
159 #define MAX_RF_PATH_NUM 4
160 #define MAX_RATE_SECTION_NUM 6
161 #define MAX_2_4G_BANDWIDTH_NUM 4
162 #define MAX_5G_BANDWIDTH_NUM 4
163 #define MAX_RF_PATH 4
164 #define MAX_CHNL_GROUP_24G 6
165 #define MAX_CHNL_GROUP_5G 14
167 #define TX_PWR_BY_RATE_NUM_BAND 2
168 #define TX_PWR_BY_RATE_NUM_RF 4
169 #define TX_PWR_BY_RATE_NUM_SECTION 12
170 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
171 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
173 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
175 #define DEL_SW_IDX_SZ 30
178 /* For now, it's just for 8192ee
179 * but not OK yet, keep it 0
181 #define DMA_IS_64BIT 0
182 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
188 RF_TX_NUM_NONIMPLEMENT,
191 #define PACKET_NORMAL 0
192 #define PACKET_DHCP 1
194 #define PACKET_EAPOL 3
196 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
197 #define RSVD_WOL_PATTERN_NUM 1
198 #define WKFMCAM_ADDR_NUM 6
199 #define WKFMCAM_SIZE 24
201 #define MAX_WOL_BIT_MASK_SIZE 16
202 /* MIN LEN keeps 13 here */
203 #define MIN_WOL_PATTERN_SIZE 13
204 #define MAX_WOL_PATTERN_SIZE 128
206 #define WAKE_ON_MAGIC_PACKET BIT(0)
207 #define WAKE_ON_PATTERN_MATCH BIT(1)
209 #define WOL_REASON_PTK_UPDATE BIT(0)
210 #define WOL_REASON_GTK_UPDATE BIT(1)
211 #define WOL_REASON_DISASSOC BIT(2)
212 #define WOL_REASON_DEAUTH BIT(3)
213 #define WOL_REASON_AP_LOST BIT(4)
214 #define WOL_REASON_MAGIC_PKT BIT(5)
215 #define WOL_REASON_UNICAST_PKT BIT(6)
216 #define WOL_REASON_PATTERN_PKT BIT(7)
217 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
218 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
219 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
221 struct rtlwifi_firmware_header {
240 struct txpower_info_2g {
241 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
242 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
243 /*If only one tx, only BW20 and OFDM are used.*/
244 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
245 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
246 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
248 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
249 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
252 struct txpower_info_5g {
253 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
254 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
255 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
256 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
283 enum regulation_txpwr_lmt {
289 TXPWR_LMT_MAX_REGULATION_NUM = 4
292 enum rt_eeprom_type {
299 RTL_STATUS_INTERFACE_START = 0,
303 HARDWARE_TYPE_RTL8192E,
304 HARDWARE_TYPE_RTL8192U,
305 HARDWARE_TYPE_RTL8192SE,
306 HARDWARE_TYPE_RTL8192SU,
307 HARDWARE_TYPE_RTL8192CE,
308 HARDWARE_TYPE_RTL8192CU,
309 HARDWARE_TYPE_RTL8192DE,
310 HARDWARE_TYPE_RTL8192DU,
311 HARDWARE_TYPE_RTL8723AE,
312 HARDWARE_TYPE_RTL8723U,
313 HARDWARE_TYPE_RTL8188EE,
314 HARDWARE_TYPE_RTL8723BE,
315 HARDWARE_TYPE_RTL8192EE,
316 HARDWARE_TYPE_RTL8821AE,
317 HARDWARE_TYPE_RTL8812AE,
318 HARDWARE_TYPE_RTL8822BE,
324 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
325 #define IS_NEW_GENERATION_IC(rtlpriv) \
326 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
327 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
328 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
329 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
330 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
331 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
332 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
333 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
334 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
335 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
336 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
337 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
338 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
339 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
340 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
342 #define RX_HAL_IS_CCK_RATE(rxmcs) \
343 ((rxmcs) == DESC_RATE1M || \
344 (rxmcs) == DESC_RATE2M || \
345 (rxmcs) == DESC_RATE5_5M || \
346 (rxmcs) == DESC_RATE11M)
348 enum scan_operation_backup_opt {
350 SCAN_OPT_BACKUP_BAND0 = 0,
351 SCAN_OPT_BACKUP_BAND1,
380 u32 rf_rb; /* rflssi_readback */
381 u32 rf_rbpi; /* rflssi_readbackpi */
385 IO_CMD_PAUSE_DM_BY_SCAN = 0,
386 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
387 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
388 IO_CMD_RESUME_DM_BY_SCAN = 2,
392 HW_VAR_ETHER_ADDR = 0x0,
393 HW_VAR_MULTICAST_REG = 0x1,
394 HW_VAR_BASIC_RATE = 0x2,
396 HW_VAR_MEDIA_STATUS= 0x4,
397 HW_VAR_SECURITY_CONF= 0x5,
398 HW_VAR_BEACON_INTERVAL = 0x6,
399 HW_VAR_ATIM_WINDOW = 0x7,
400 HW_VAR_LISTEN_INTERVAL = 0x8,
401 HW_VAR_CS_COUNTER = 0x9,
402 HW_VAR_DEFAULTKEY0 = 0xa,
403 HW_VAR_DEFAULTKEY1 = 0xb,
404 HW_VAR_DEFAULTKEY2 = 0xc,
405 HW_VAR_DEFAULTKEY3 = 0xd,
407 HW_VAR_R2T_SIFS = 0xf,
410 HW_VAR_SLOT_TIME = 0x12,
411 HW_VAR_ACK_PREAMBLE = 0x13,
412 HW_VAR_CW_CONFIG = 0x14,
413 HW_VAR_CW_VALUES = 0x15,
414 HW_VAR_RATE_FALLBACK_CONTROL= 0x16,
415 HW_VAR_CONTENTION_WINDOW = 0x17,
416 HW_VAR_RETRY_COUNT = 0x18,
417 HW_VAR_TR_SWITCH = 0x19,
418 HW_VAR_COMMAND = 0x1a,
419 HW_VAR_WPA_CONFIG = 0x1b,
420 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
421 HW_VAR_SHORTGI_DENSITY = 0x1d,
422 HW_VAR_AMPDU_FACTOR = 0x1e,
423 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
424 HW_VAR_AC_PARAM = 0x20,
425 HW_VAR_ACM_CTRL = 0x21,
426 HW_VAR_DIS_Req_Qsize = 0x22,
427 HW_VAR_CCX_CHNL_LOAD = 0x23,
428 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
429 HW_VAR_CCX_CLM_NHM = 0x25,
430 HW_VAR_TxOPLimit = 0x26,
431 HW_VAR_TURBO_MODE = 0x27,
432 HW_VAR_RF_STATE = 0x28,
433 HW_VAR_RF_OFF_BY_HW = 0x29,
434 HW_VAR_BUS_SPEED = 0x2a,
435 HW_VAR_SET_DEV_POWER = 0x2b,
438 HW_VAR_RATR_0 = 0x2d,
440 HW_VAR_CPU_RST = 0x2f,
441 HW_VAR_CHECK_BSSID = 0x30,
442 HW_VAR_LBK_MODE = 0x31,
443 HW_VAR_AES_11N_FIX = 0x32,
444 HW_VAR_USB_RX_AGGR = 0x33,
445 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
446 HW_VAR_RETRY_LIMIT = 0x35,
447 HW_VAR_INIT_TX_RATE = 0x36,
448 HW_VAR_TX_RATE_REG = 0x37,
449 HW_VAR_EFUSE_USAGE = 0x38,
450 HW_VAR_EFUSE_BYTES = 0x39,
451 HW_VAR_AUTOLOAD_STATUS = 0x3a,
452 HW_VAR_RF_2R_DISABLE = 0x3b,
453 HW_VAR_SET_RPWM = 0x3c,
454 HW_VAR_H2C_FW_PWRMODE = 0x3d,
455 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
456 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
457 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
458 HW_VAR_FW_PSMODE_STATUS = 0x41,
459 HW_VAR_INIT_RTS_RATE = 0x42,
460 HW_VAR_RESUME_CLK_ON = 0x43,
461 HW_VAR_FW_LPS_ACTION = 0x44,
462 HW_VAR_1X1_RECV_COMBINE = 0x45,
463 HW_VAR_STOP_SEND_BEACON = 0x46,
464 HW_VAR_TSF_TIMER = 0x47,
465 HW_VAR_IO_CMD = 0x48,
467 HW_VAR_RF_RECOVERY = 0x49,
468 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
469 HW_VAR_WF_MASK = 0x4b,
470 HW_VAR_WF_CRC = 0x4c,
471 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
472 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
473 HW_VAR_RESET_WFCRC = 0x4f,
475 HW_VAR_HANDLE_FW_C2H = 0x50,
476 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
478 HW_VAR_HW_SEQ_ENABLE = 0x53,
479 HW_VAR_CORRECT_TSF = 0x54,
480 HW_VAR_BCN_VALID = 0x55,
481 HW_VAR_FWLPS_RF_ON = 0x56,
482 HW_VAR_DUAL_TSF_RST = 0x57,
483 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58,
484 HW_VAR_INT_MIGRATION = 0x59,
485 HW_VAR_INT_AC = 0x5a,
486 HW_VAR_RF_TIMING = 0x5b,
488 HAL_DEF_WOWLAN = 0x5c,
490 HW_VAR_KEEP_ALIVE = 0x5e,
491 HW_VAR_NAV_UPPER = 0x5f,
493 HW_VAR_MGT_FILTER = 0x60,
494 HW_VAR_CTRL_FILTER = 0x61,
495 HW_VAR_DATA_FILTER = 0x62,
498 enum rt_media_status {
499 RT_MEDIA_DISCONNECT = 0,
505 RT_CID_8187_ALPHA0 = 1,
506 RT_CID_8187_SERCOMM_PS = 2,
507 RT_CID_8187_HW_LED = 3,
508 RT_CID_8187_NETGEAR = 4,
510 RT_CID_819X_CAMEO = 6,
511 RT_CID_819X_RUNTOP = 7,
512 RT_CID_819X_SENAO = 8,
514 RT_CID_819X_NETCORE = 10,
515 RT_CID_NETTRONIX = 11,
519 RT_CID_819X_ALPHA = 15,
520 RT_CID_819X_SITECOM = 16,
522 RT_CID_819X_LENOVO = 18,
523 RT_CID_819X_QMI = 19,
524 RT_CID_819X_EDIMAX_BELKIN = 20,
525 RT_CID_819X_SERCOMM_BELKIN = 21,
526 RT_CID_819X_CAMEO1 = 22,
527 RT_CID_819X_MSI = 23,
528 RT_CID_819X_ACER = 24,
530 RT_CID_819X_CLEVO = 28,
531 RT_CID_819X_ARCADYAN_BELKIN = 29,
532 RT_CID_819X_SAMSUNG = 30,
533 RT_CID_819X_WNC_COREGA = 31,
534 RT_CID_819X_FOXCOON = 32,
535 RT_CID_819X_DELL = 33,
536 RT_CID_819X_PRONETS = 34,
537 RT_CID_819X_EDIMAX_ASUS = 35,
546 HW_DESC_TX_NEXTDESC_ADDR,
555 PRIME_CHNL_OFFSET_DONT_CARE = 0,
556 PRIME_CHNL_OFFSET_LOWER = 1,
557 PRIME_CHNL_OFFSET_UPPER = 2,
567 enum ht_channel_width {
568 HT_CHANNEL_WIDTH_20 = 0,
569 HT_CHANNEL_WIDTH_20_40 = 1,
570 HT_CHANNEL_WIDTH_80 = 2,
573 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
574 Cipher Suites Encryption Algorithms */
577 WEP40_ENCRYPTION = 1,
579 RSERVED_ENCRYPTION = 3,
580 AESCCMP_ENCRYPTION = 4,
581 WEP104_ENCRYPTION = 5,
582 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
587 _HAL_STATE_START = 1,
593 DESC_RATE5_5M = 0x02,
605 DESC_RATEMCS0 = 0x0c,
606 DESC_RATEMCS1 = 0x0d,
607 DESC_RATEMCS2 = 0x0e,
608 DESC_RATEMCS3 = 0x0f,
609 DESC_RATEMCS4 = 0x10,
610 DESC_RATEMCS5 = 0x11,
611 DESC_RATEMCS6 = 0x12,
612 DESC_RATEMCS7 = 0x13,
613 DESC_RATEMCS8 = 0x14,
614 DESC_RATEMCS9 = 0x15,
615 DESC_RATEMCS10 = 0x16,
616 DESC_RATEMCS11 = 0x17,
617 DESC_RATEMCS12 = 0x18,
618 DESC_RATEMCS13 = 0x19,
619 DESC_RATEMCS14 = 0x1a,
620 DESC_RATEMCS15 = 0x1b,
621 DESC_RATEMCS15_SG = 0x1c,
622 DESC_RATEMCS32 = 0x20,
624 DESC_RATEVHT1SS_MCS0 = 0x2c,
625 DESC_RATEVHT1SS_MCS1 = 0x2d,
626 DESC_RATEVHT1SS_MCS2 = 0x2e,
627 DESC_RATEVHT1SS_MCS3 = 0x2f,
628 DESC_RATEVHT1SS_MCS4 = 0x30,
629 DESC_RATEVHT1SS_MCS5 = 0x31,
630 DESC_RATEVHT1SS_MCS6 = 0x32,
631 DESC_RATEVHT1SS_MCS7 = 0x33,
632 DESC_RATEVHT1SS_MCS8 = 0x34,
633 DESC_RATEVHT1SS_MCS9 = 0x35,
634 DESC_RATEVHT2SS_MCS0 = 0x36,
635 DESC_RATEVHT2SS_MCS1 = 0x37,
636 DESC_RATEVHT2SS_MCS2 = 0x38,
637 DESC_RATEVHT2SS_MCS3 = 0x39,
638 DESC_RATEVHT2SS_MCS4 = 0x3a,
639 DESC_RATEVHT2SS_MCS5 = 0x3b,
640 DESC_RATEVHT2SS_MCS6 = 0x3c,
641 DESC_RATEVHT2SS_MCS7 = 0x3d,
642 DESC_RATEVHT2SS_MCS8 = 0x3e,
643 DESC_RATEVHT2SS_MCS9 = 0x3f,
669 EFUSE_HWSET_MAX_SIZE,
670 EFUSE_MAX_SECTION_MAP,
671 EFUSE_REAL_CONTENT_SIZE,
672 EFUSE_OOB_PROTECT_BYTES_LEN,
688 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
689 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
690 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
691 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
692 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
693 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
694 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
695 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
696 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
697 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
698 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
699 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
700 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
701 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
702 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
703 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
704 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
705 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
706 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
707 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
708 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
709 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
710 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
711 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
712 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
713 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
714 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
715 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
716 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
717 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
718 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
719 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
720 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
721 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
722 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
724 RTL_IMR_C2HCMD, /*fw interrupt*/
726 /*CCK Rates, TxHT = 0 */
732 /*OFDM Rates, TxHT = 0 */
745 RTL_RC_VHT_RATE_1SS_MCS7,
746 RTL_RC_VHT_RATE_1SS_MCS8,
747 RTL_RC_VHT_RATE_1SS_MCS9,
748 RTL_RC_VHT_RATE_2SS_MCS7,
749 RTL_RC_VHT_RATE_2SS_MCS8,
750 RTL_RC_VHT_RATE_2SS_MCS9,
756 /*Firmware PS mode for control LPS.*/
758 FW_PS_ACTIVE_MODE = 0,
763 FW_PS_UAPSD_WMM_MODE = 5,
764 FW_PS_UAPSD_MODE = 6,
766 FW_PS_WWLAN_MODE = 8,
767 FW_PS_PM_Radio_Off = 9,
768 FW_PS_PM_Card_Disable = 10,
772 EACTIVE, /*Active/Continuous access. */
773 EMAXPS, /*Max power save mode. */
774 EFASTPS, /*Fast power save mode. */
775 EAUTOPS, /*Auto power save mode. */
780 LED_CTL_POWER_ON = 1,
785 LED_CTL_SITE_SURVEY = 6,
786 LED_CTL_POWER_OFF = 7,
787 LED_CTL_START_TO_LINK = 8,
788 LED_CTL_START_WPS = 9,
789 LED_CTL_STOP_WPS = 10,
800 /*acm implementation method.*/
802 eAcmWay0_SwAndHw = 0,
808 SINGLEMAC_SINGLEPHY = 0,
821 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
835 WIRELESS_MODE_UNKNOWN = 0x00,
836 WIRELESS_MODE_A = 0x01,
837 WIRELESS_MODE_B = 0x02,
838 WIRELESS_MODE_G = 0x04,
839 WIRELESS_MODE_AUTO = 0x08,
840 WIRELESS_MODE_N_24G = 0x10,
841 WIRELESS_MODE_N_5G = 0x20,
842 WIRELESS_MODE_AC_5G = 0x40,
843 WIRELESS_MODE_AC_24G = 0x80,
844 WIRELESS_MODE_AC_ONLY = 0x100,
845 WIRELESS_MODE_MAX = 0x800
848 #define IS_WIRELESS_MODE_A(wirelessmode) \
849 (wirelessmode == WIRELESS_MODE_A)
850 #define IS_WIRELESS_MODE_B(wirelessmode) \
851 (wirelessmode == WIRELESS_MODE_B)
852 #define IS_WIRELESS_MODE_G(wirelessmode) \
853 (wirelessmode == WIRELESS_MODE_G)
854 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
855 (wirelessmode == WIRELESS_MODE_N_24G)
856 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
857 (wirelessmode == WIRELESS_MODE_N_5G)
859 enum ratr_table_mode {
860 RATR_INX_WIRELESS_NGB = 0,
861 RATR_INX_WIRELESS_NG = 1,
862 RATR_INX_WIRELESS_NB = 2,
863 RATR_INX_WIRELESS_N = 3,
864 RATR_INX_WIRELESS_GB = 4,
865 RATR_INX_WIRELESS_G = 5,
866 RATR_INX_WIRELESS_B = 6,
867 RATR_INX_WIRELESS_MC = 7,
868 RATR_INX_WIRELESS_A = 8,
869 RATR_INX_WIRELESS_AC_5N = 8,
870 RATR_INX_WIRELESS_AC_24N = 9,
873 enum rtl_link_state {
875 MAC80211_LINKING = 1,
877 MAC80211_LINKED_SCANNING = 3,
894 enum rt_polarity_ctl {
895 RT_POLARITY_LOW_ACT = 0,
896 RT_POLARITY_HIGH_ACT = 1,
899 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
900 enum fw_wow_reason_v2 {
901 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
902 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
903 FW_WOW_V2_DISASSOC_EVENT = 0x04,
904 FW_WOW_V2_DEAUTH_EVENT = 0x08,
905 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
906 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
907 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
908 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
909 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
910 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
911 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
912 FW_WOW_V2_REASON_MAX = 0xff,
915 enum wolpattern_type {
917 MULTICAST_PATTERN = 1,
918 BROADCAST_PATTERN = 2,
931 struct octet_string {
936 struct rtl_hdr_3addr {
946 struct rtl_info_element {
952 struct rtl_probe_rsp {
953 struct rtl_hdr_3addr header;
955 __le16 beacon_interval;
957 /*SSID, supported rates, FH params, DS params,
958 CF params, IBSS params, TIM (if beacon), RSN */
959 struct rtl_info_element info_element[0];
963 /*ledpin Identify how to implement this SW led.*/
966 enum rtl_led_pin ledpin;
972 struct rtl_led sw_led0;
973 struct rtl_led sw_led1;
976 struct rtl_qos_parameters {
984 struct rt_smooth_data {
985 u32 elements[100]; /*array to store values */
986 u32 index; /*index to current array to store */
987 u32 total_num; /*num of valid elements */
988 u32 total_val; /*sum of valid elements */
991 struct false_alarm_statistics {
993 u32 cnt_rate_illegal;
996 u32 cnt_fast_fsync_fail;
997 u32 cnt_sb_search_fail;
1017 struct wireless_stats {
1018 unsigned long txbytesunicast;
1019 unsigned long txbytesmulticast;
1020 unsigned long txbytesbroadcast;
1021 unsigned long rxbytesunicast;
1024 /*Correct smoothed ss in Dbm, only used
1025 in driver to report real power now. */
1026 long recv_signal_power;
1027 long signal_quality;
1028 long last_sigstrength_inpercent;
1030 u32 rssi_calculate_cnt;
1033 /*Transformed, in dbm. Beautified signal
1034 strength for UI, not correct. */
1035 long signal_strength;
1037 u8 rx_rssi_percentage[4];
1039 u8 rx_evm_percentage[2];
1041 u16 rx_cfo_short[4];
1044 struct rt_smooth_data ui_rssi;
1045 struct rt_smooth_data ui_link_quality;
1048 struct rate_adaptive {
1049 u8 rate_adaptive_disabled;
1053 u32 high_rssi_thresh_for_ra;
1054 u32 high2low_rssi_thresh_for_ra;
1055 u8 low2high_rssi_thresh_for_ra40m;
1056 u32 low_rssi_thresh_for_ra40m;
1057 u8 low2high_rssi_thresh_for_ra20m;
1058 u32 low_rssi_thresh_for_ra20m;
1059 u32 upper_rssi_threshold_ratr;
1060 u32 middleupper_rssi_threshold_ratr;
1061 u32 middle_rssi_threshold_ratr;
1062 u32 middlelow_rssi_threshold_ratr;
1063 u32 low_rssi_threshold_ratr;
1064 u32 ultralow_rssi_threshold_ratr;
1065 u32 low_rssi_threshold_ratr_40m;
1066 u32 low_rssi_threshold_ratr_20m;
1067 u8 ping_rssi_enable;
1069 u32 ping_rssi_thresh_for_ra;
1074 bool lower_rts_rate;
1075 bool is_special_data;
1078 struct regd_pair_mapping {
1084 struct dynamic_primary_cca {
1094 struct rtl_regulatory {
1097 u16 max_power_level;
1101 int16_t power_limit;
1102 struct regd_pair_mapping *regpair;
1106 bool rfkill_state; /*0 is off, 1 is on */
1110 #define P2P_MAX_NOA_NUM 2
1113 P2P_ROLE_DISABLE = 0,
1114 P2P_ROLE_DEVICE = 1,
1115 P2P_ROLE_CLIENT = 2,
1123 P2P_PS_SCAN_DONE = 3,
1124 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1129 P2P_PS_CTWINDOW = 1,
1131 P2P_PS_MIX = 3, /* CTWindow and NoA */
1134 struct rtl_p2p_ps_info {
1135 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1136 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1137 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1138 /* Client traffic window. A period of time in TU after TBTT. */
1140 u8 opp_ps; /* opportunistic power save. */
1141 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1142 /* Count for owner, Type of client. */
1143 u8 noa_count_type[P2P_MAX_NOA_NUM];
1144 /* Max duration for owner, preferred or min acceptable duration
1147 u32 noa_duration[P2P_MAX_NOA_NUM];
1148 /* Length of interval for owner, preferred or max acceptable intervali
1151 u32 noa_interval[P2P_MAX_NOA_NUM];
1152 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1153 u32 noa_start_time[P2P_MAX_NOA_NUM];
1156 struct p2p_ps_offload_t {
1158 u8 role:1; /* 1: Owner, 0: Client */
1167 #define IQK_MATRIX_REG_NUM 8
1168 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1170 struct iqk_matrix_regs {
1172 long value[1][IQK_MATRIX_REG_NUM];
1175 struct phy_parameters {
1180 enum hw_param_tab_index {
1195 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1196 struct init_gain initgain_backup;
1197 enum io_type current_io_type;
1202 u8 set_bwmode_inprogress;
1203 u8 sw_chnl_inprogress;
1208 u8 set_io_inprogress;
1211 /* record for power tracking */
1223 u32 reg_c04, reg_c08, reg_874;
1224 u32 adda_backup[16];
1225 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1226 u32 iqk_bb_backup[10];
1227 bool iqk_initialized;
1229 bool rfpath_rx_enable[MAX_RF_PATH];
1233 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1236 bool iqk_in_progress;
1240 /* this is for 88E & 8723A */
1241 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1242 /* MAX_PG_GROUP groups of pwr diff by rates */
1243 u32 mcs_offset[MAX_PG_GROUP][16];
1244 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1245 [TX_PWR_BY_RATE_NUM_RF]
1246 [TX_PWR_BY_RATE_NUM_RF]
1247 [TX_PWR_BY_RATE_NUM_SECTION];
1248 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1249 [TX_PWR_BY_RATE_NUM_RF]
1250 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1251 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1252 [TX_PWR_BY_RATE_NUM_RF]
1253 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1254 u8 default_initialgain[4];
1256 /* the current Tx power level */
1257 u8 cur_cck_txpwridx;
1258 u8 cur_ofdm24g_txpwridx;
1259 u8 cur_bw20_txpwridx;
1260 u8 cur_bw40_txpwridx;
1262 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1263 [MAX_2_4G_BANDWIDTH_NUM]
1264 [MAX_RATE_SECTION_NUM]
1265 [CHANNEL_MAX_NUMBER_2G]
1267 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1268 [MAX_5G_BANDWIDTH_NUM]
1269 [MAX_RATE_SECTION_NUM]
1270 [CHANNEL_MAX_NUMBER_5G]
1273 u32 rfreg_chnlval[2];
1275 u32 reg_rf3c[2]; /* pathA / pathB */
1277 u32 backup_rf_0x1a;/*92ee*/
1282 u8 num_total_rfpath;
1283 struct phy_parameters hwparam_tables[MAX_TAB];
1286 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1287 enum rt_polarity_ctl polarity_ctl;
1290 #define MAX_TID_COUNT 9
1291 #define RTL_AGG_STOP 0
1292 #define RTL_AGG_PROGRESS 1
1293 #define RTL_AGG_START 2
1294 #define RTL_AGG_OPERATIONAL 3
1295 #define RTL_AGG_OFF 0
1296 #define RTL_AGG_ON 1
1297 #define RTL_RX_AGG_START 1
1298 #define RTL_RX_AGG_STOP 0
1299 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1300 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1317 struct rtl_tid_data {
1319 struct rtl_ht_agg agg;
1322 struct rtl_sta_info {
1323 struct list_head list;
1324 struct rtl_tid_data tids[MAX_TID_COUNT];
1325 /* just used for ap adhoc or mesh*/
1326 struct rssi_sta rssi_stat;
1330 u8 mac_addr[ETH_ALEN];
1336 struct mutex bb_mutex;
1339 unsigned long pci_mem_end; /*shared mem end */
1340 unsigned long pci_mem_start; /*shared mem start */
1343 unsigned long pci_base_addr; /*device I/O address */
1345 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1346 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1347 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1348 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1351 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1352 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1353 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1358 u8 mac_addr[ETH_ALEN];
1359 u8 mac80211_registered;
1365 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1366 struct ieee80211_hw *hw;
1367 struct ieee80211_vif *vif;
1368 enum nl80211_iftype opmode;
1370 /*Probe Beacon management */
1371 struct rtl_tid_data tids[MAX_TID_COUNT];
1372 enum rtl_link_state link_state;
1378 u8 p2p; /*using p2p role*/
1388 u8 cnt_after_linked;
1392 /* skb wait queue */
1393 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1410 u8 bssid[ETH_ALEN] __aligned(2);
1412 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1413 u32 basic_rates; /* b/g rates */
1418 u16 mode; /* wireless mode */
1423 u8 cur_40_prime_sc_bk;
1432 int beacon_interval;
1435 u8 min_space_cfg; /*For Min spacing configurations */
1437 u8 current_ampdu_factor;
1438 u8 current_ampdu_density;
1441 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1442 struct rtl_qos_parameters ac[AC_MAX];
1447 u32 last_bt_edca_ul;
1448 u32 last_bt_edca_dl;
1454 bool adc_back_off_on;
1456 bool low_penalty_rate_adaptive;
1457 bool rf_rx_lpf_shrink;
1458 bool reject_aggre_pkt;
1466 u8 fw_dac_swing_lvl;
1473 bool sw_dac_swing_on;
1474 u32 sw_dac_swing_lvl;
1479 bool ignore_wlan_act;
1482 struct bt_coexist_8723 {
1483 u32 high_priority_tx;
1484 u32 high_priority_rx;
1485 u32 low_priority_tx;
1486 u32 low_priority_rx;
1488 bool c2h_bt_info_req_sent;
1489 bool c2h_bt_inquiry_page;
1490 u32 bt_inq_page_start_time;
1492 u8 c2h_bt_info_original;
1493 u8 bt_inquiry_page_cnt;
1494 struct btdm_8723 btdm;
1498 struct ieee80211_hw *hw;
1499 bool driver_is_goingto_unload;
1502 bool being_init_adapter;
1504 bool mac_func_enable;
1505 bool pre_edcca_enable;
1506 struct bt_coexist_8723 hal_coex_8723;
1508 enum intf_type interface;
1509 u16 hw_type; /*92c or 92d or 92s and so on */
1512 u32 version; /*version of chip */
1513 u8 state; /*stop 0, start 1 */
1538 bool h2c_setinprogress;
1541 /*Reserve page start offset except beacon in TxQ. */
1542 u8 fw_rsvdpage_startoffset;
1546 /* FW Cmd IO related */
1549 bool set_fwcmd_inprogress;
1550 u8 current_fwcmd_io;
1552 struct p2p_ps_offload_t p2p_ps_offload;
1553 bool fw_clk_change_in_progress;
1554 bool allow_sw_to_change_hwclc;
1557 bool driver_going2unload;
1559 /*AMPDU init min space*/
1560 u8 minspace_cfg; /*For Min spacing configurations */
1563 enum macphy_mode macphymode;
1564 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1565 enum band_type current_bandtypebackup;
1566 enum band_type bandset;
1567 /* dual MAC 0--Mac0 1--Mac1 */
1569 /* just for DualMac S3S4 */
1571 bool earlymode_enable;
1572 u8 max_earlymode_num;
1574 bool during_mac0init_radiob;
1575 bool during_mac1init_radioa;
1576 bool reloadtxpowerindex;
1577 /* True if IMR or IQK have done
1578 for 2.4G in scan progress */
1579 bool load_imrandiqk_setting_for2g;
1581 bool disable_amsdu_8k;
1582 bool master_of_dmsp;
1585 u16 rx_tag;/*for 92ee*/
1590 bool enter_pnp_sleep;
1591 bool wake_from_pnp_sleep;
1593 __kernel_time_t last_suspend_sec;
1595 u8 *wowlan_firmware;
1597 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1599 bool real_wow_v2_enable;
1600 bool re_init_llt_table;
1603 struct rtl_security {
1608 bool use_defaultkey;
1609 /*Encryption Algorithm for Unicast Packet */
1610 enum rt_enc_alg pairwise_enc_algorithm;
1611 /*Encryption Algorithm for Brocast/Multicast */
1612 enum rt_enc_alg group_enc_algorithm;
1613 /*Cam Entry Bitmap */
1614 u32 hwsec_cam_bitmap;
1615 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1616 /*local Key buffer, indx 0 is for
1617 pairwise key 1-4 is for agoup key. */
1618 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1619 u8 key_len[KEY_BUF_SIZE];
1621 /*The pointer of Pairwise Key,
1622 it always points to KeyBuf[4] */
1626 #define ASSOCIATE_ENTRY_NUM 33
1628 struct fast_ant_training {
1630 u8 antsel_rx_keep_0;
1631 u8 antsel_rx_keep_1;
1632 u8 antsel_rx_keep_2;
1638 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1639 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1640 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1641 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1642 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1643 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1644 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1649 struct dm_phy_dbg_info {
1651 u64 num_qry_phy_status;
1652 u64 num_qry_phy_status_cck;
1653 u64 num_qry_phy_status_ofdm;
1654 u16 num_qry_beacon_pkt;
1660 /*PHY status for Dynamic Management */
1661 long entry_min_undec_sm_pwdb;
1663 long undec_sm_pwdb; /*out dm */
1664 long entry_max_undec_sm_pwdb;
1666 bool dm_initialgain_enable;
1667 bool dynamic_txpower_enable;
1668 bool current_turbo_edca;
1669 bool is_any_nonbepkts; /*out dm */
1670 bool is_cur_rdlstate;
1671 bool txpower_trackinginit;
1672 bool disable_framebursting;
1674 bool txpower_tracking;
1676 bool rfpath_rxenable[4];
1677 bool inform_fw_driverctrldm;
1678 bool current_mrc_switch;
1680 u8 powerindex_backup[6];
1682 u8 thermalvalue_rxgain;
1683 u8 thermalvalue_iqk;
1684 u8 thermalvalue_lck;
1687 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1688 u8 thermalvalue_avg_index;
1691 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1692 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1696 u8 txpower_track_control;
1697 bool interrupt_migration;
1698 bool disable_tx_int;
1699 s8 ofdm_index[MAX_RF_PATH];
1700 u8 default_ofdm_index;
1701 u8 default_cck_index;
1703 s8 delta_power_index[MAX_RF_PATH];
1704 s8 delta_power_index_last[MAX_RF_PATH];
1705 s8 power_index_offset[MAX_RF_PATH];
1706 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1707 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1709 bool modify_txagc_flag_path_a;
1710 bool modify_txagc_flag_path_b;
1712 bool one_entry_only;
1713 struct dm_phy_dbg_info dbginfo;
1715 /* Dynamic ATC switch */
1724 u32 packet_count_pre;
1727 /*88e tx power tracking*/
1728 u8 swing_idx_ofdm[MAX_RF_PATH];
1729 u8 swing_idx_ofdm_cur;
1730 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1731 bool swing_flag_ofdm;
1733 u8 swing_idx_cck_cur;
1734 u8 swing_idx_cck_base;
1735 bool swing_flag_cck;
1740 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1741 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1742 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1743 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1744 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1745 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1746 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1747 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1748 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1749 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1750 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1751 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1752 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1753 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1756 bool supp_phymode_switch;
1759 struct fast_ant_training fat_table;
1776 #define EFUSE_MAX_LOGICAL_SIZE 512
1781 u16 max_physical_size;
1783 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1784 u16 efuse_usedbytes;
1785 u8 efuse_usedpercentage;
1786 #ifdef EFUSE_REPG_WORKAROUND
1787 bool efuse_re_pg_sec1flag;
1788 u8 efuse_re_pg_data[8];
1791 u8 autoload_failflag;
1800 u16 eeprom_channelplan;
1808 u8 antenna_div_type;
1810 bool txpwr_fromeprom;
1811 u8 eeprom_crystalcap;
1813 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1814 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1815 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1816 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1817 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1818 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1820 u8 internal_pa_5g[2]; /* pathA / pathB */
1824 /*For power group */
1825 u8 eeprom_pwrgroup[2][3];
1826 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1827 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1829 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1830 /*For HT 40MHZ pwr */
1831 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1832 /*For HT 40MHZ pwr */
1833 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1835 /*--------------------------------------------------------*
1836 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1837 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1838 * define new arrays in Windows code.
1839 * BUT, in linux code, we use the same array for all ICs.
1841 * The Correspondance relation between two arrays is:
1842 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1843 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1844 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1845 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1847 * Sizes of these arrays are decided by the larger ones.
1849 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1850 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1851 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1852 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1854 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1855 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1856 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1857 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1858 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1859 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1861 u8 txpwr_safetyflag; /* Band edge enable flag */
1862 u16 eeprom_txpowerdiff;
1863 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1864 u8 antenna_txpwdiff[3];
1866 u8 eeprom_regulatory;
1867 u8 eeprom_thermalmeter;
1868 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1870 u8 crystalcap; /* CrystalCap. */
1874 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1875 bool apk_thermalmeterignore;
1877 bool b1x1_recvcombine;
1884 struct rtl_tx_report {
1887 unsigned long last_sent_time;
1892 bool pwrdomain_protect;
1893 bool in_powersavemode;
1894 bool rfchange_inprogress;
1895 bool swrf_processing;
1898 * just for PCIE ASPM
1899 * If it supports ASPM, Offset[560h] = 0x40,
1900 * otherwise Offset[560h] = 0x00.
1903 bool support_backdoor;
1906 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1911 /*For Fw control LPS mode */
1913 /*Record Fw PS mode status. */
1914 bool fw_current_inpsmode;
1915 u8 reg_max_lps_awakeintvl;
1917 bool low_power_enable;/*for 32k*/
1928 /*just for PCIE ASPM */
1929 u8 const_amdpci_aspm;
1932 enum rf_pwrstate inactive_pwrstate;
1933 enum rf_pwrstate rfpwr_state; /*cur power state */
1939 bool multi_buffered;
1941 unsigned int dtim_counter;
1942 unsigned int sleep_ms;
1943 unsigned long last_sleep_jiffies;
1944 unsigned long last_awake_jiffies;
1945 unsigned long last_delaylps_stamp_jiffies;
1946 unsigned long last_dtim;
1947 unsigned long last_beacon;
1948 unsigned long last_action;
1949 unsigned long last_slept;
1952 struct rtl_p2p_ps_info p2p_ps_info;
1956 /* wake up on line */
1958 u8 arp_offload_enable;
1959 u8 gtk_offload_enable;
1960 /* Used for WOL, indicates the reason for waking event.*/
1962 /* Record the last waking time for comparison with setting key. */
1963 u64 last_wakeup_time;
1967 u8 psaddr[ETH_ALEN];
1972 u8 rate; /* hw desc rate */
1973 u8 received_channel;
1982 u8 signalquality; /*in 0-100 index. */
1984 * Real power in dBm for this packet,
1985 * no beautification and aggregation.
1987 s32 recvsignalpower;
1988 s8 rxpower; /*in dBm Translate from PWdB */
1989 u8 signalstrength; /*in 0-100 index. */
1993 u16 shortpreamble:1;
2005 bool rx_is40Mhzpacket;
2008 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2009 s8 rx_mimo_signalquality[4];
2010 u8 rx_mimo_evm_dbm[4];
2011 u16 cfo_short[4]; /* per-path's Cfo_short */
2014 s8 rx_mimo_sig_qual[4];
2015 u8 rx_pwr[4]; /* per-path's pwdb */
2016 u8 rx_snr[4]; /* per-path's SNR */
2018 u8 bt_coex_pwr_adjust;
2019 bool packet_matchbssid;
2023 bool packet_beacon; /*for rssi */
2024 s8 cck_adc_pwdb[4]; /*for rx path selection */
2030 u8 packet_report_type;
2034 u32 bt_rx_rssi_percentage;
2035 u32 macid_valid_entry[2];
2039 struct rt_link_detect {
2040 /* count for roaming */
2041 u32 bcn_rx_inperiod;
2044 u32 num_tx_in4period[4];
2045 u32 num_rx_in4period[4];
2047 u32 num_tx_inperiod;
2048 u32 num_rx_inperiod;
2051 bool tx_busy_traffic;
2052 bool rx_busy_traffic;
2053 bool higher_busytraffic;
2054 bool higher_busyrxtraffic;
2056 u32 tidtx_in4period[MAX_TID_COUNT][4];
2057 u32 tidtx_inperiod[MAX_TID_COUNT];
2058 bool higher_busytxtraffic[MAX_TID_COUNT];
2061 struct rtl_tcb_desc {
2069 u8 rts_use_shortpreamble:1;
2070 u8 rts_use_shortgi:1;
2076 u8 use_shortpreamble:1;
2077 u8 use_driver_rate:1;
2078 u8 disable_ratefallback:1;
2092 /* The max value by HW */
2094 bool tx_enable_sw_calc_duration;
2097 struct rtl_wow_pattern {
2103 struct rtl_hal_ops {
2104 int (*init_sw_vars) (struct ieee80211_hw *hw);
2105 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2106 void (*read_chip_version)(struct ieee80211_hw *hw);
2107 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2108 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2109 u32 *p_inta, u32 *p_intb);
2110 int (*hw_init) (struct ieee80211_hw *hw);
2111 void (*hw_disable) (struct ieee80211_hw *hw);
2112 void (*hw_suspend) (struct ieee80211_hw *hw);
2113 void (*hw_resume) (struct ieee80211_hw *hw);
2114 void (*enable_interrupt) (struct ieee80211_hw *hw);
2115 void (*disable_interrupt) (struct ieee80211_hw *hw);
2116 int (*set_network_type) (struct ieee80211_hw *hw,
2117 enum nl80211_iftype type);
2118 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2120 void (*set_bw_mode) (struct ieee80211_hw *hw,
2121 enum nl80211_channel_type ch_type);
2122 u8(*switch_channel) (struct ieee80211_hw *hw);
2123 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2124 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2125 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2126 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2127 u32 add_msr, u32 rm_msr);
2128 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2129 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2130 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2131 struct ieee80211_sta *sta, u8 rssi_level);
2132 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2133 u8 *desc, u8 queue_index,
2134 struct sk_buff *skb, dma_addr_t addr);
2135 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2136 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2138 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2140 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2141 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2143 struct ieee80211_tx_info *info,
2144 struct ieee80211_sta *sta,
2145 struct sk_buff *skb, u8 hw_queue,
2146 struct rtl_tcb_desc *ptcb_desc);
2147 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2148 u32 buffer_len, bool bIsPsPoll);
2149 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2150 bool firstseg, bool lastseg,
2151 struct sk_buff *skb);
2152 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2153 struct rtl_stats *stats,
2154 struct ieee80211_rx_status *rx_status,
2155 u8 *pdesc, struct sk_buff *skb);
2156 void (*set_channel_access) (struct ieee80211_hw *hw);
2157 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2158 void (*dm_watchdog) (struct ieee80211_hw *hw);
2159 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2160 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2161 enum rf_pwrstate rfpwr_state);
2162 void (*led_control) (struct ieee80211_hw *hw,
2163 enum led_ctl_mode ledaction);
2164 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2165 u8 desc_name, u8 *val);
2166 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2167 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2168 u8 hw_queue, u16 index);
2169 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2170 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2171 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2172 u8 *macaddr, bool is_group, u8 enc_algo,
2173 bool is_wepkey, bool clear_all);
2174 void (*init_sw_leds) (struct ieee80211_hw *hw);
2175 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2176 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2177 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2179 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2180 u32 regaddr, u32 bitmask);
2181 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2182 u32 regaddr, u32 bitmask, u32 data);
2183 void (*linked_set_reg) (struct ieee80211_hw *hw);
2184 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2185 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2186 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2187 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2188 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2190 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2191 u8 *ppowerlevel, u8 channel);
2192 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2194 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2196 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2197 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2198 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2199 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2200 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2202 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2203 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2204 u32 cmd_len, u8 *p_cmdbuffer);
2205 bool (*get_btc_status) (void);
2206 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2207 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2208 const struct rtl_stats *status, struct sk_buff *skb);
2209 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2210 struct rtl_wow_pattern *rtl_pattern,
2212 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2213 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
2217 struct rtl_intf_ops {
2219 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2220 int (*adapter_start) (struct ieee80211_hw *hw);
2221 void (*adapter_stop) (struct ieee80211_hw *hw);
2222 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2223 struct rtl_priv **buddy_priv);
2225 int (*adapter_tx) (struct ieee80211_hw *hw,
2226 struct ieee80211_sta *sta,
2227 struct sk_buff *skb,
2228 struct rtl_tcb_desc *ptcb_desc);
2229 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2230 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2231 bool (*waitq_insert) (struct ieee80211_hw *hw,
2232 struct ieee80211_sta *sta,
2233 struct sk_buff *skb);
2236 void (*disable_aspm) (struct ieee80211_hw *hw);
2237 void (*enable_aspm) (struct ieee80211_hw *hw);
2242 struct rtl_mod_params {
2245 /* default: 0 = using hardware encryption */
2248 /* default: 0 = DBG_EMERG (0)*/
2251 /* default: 1 = using no linked power save */
2254 /* default: 1 = using linked sw power save */
2257 /* default: 1 = using linked fw power save */
2260 /* default: 0 = not using MSI interrupts mode
2261 * submodules should set their own default value
2265 /* default 0: 1 means disable */
2266 bool disable_watchdog;
2268 /* default 0: 1 means do not disable interrupts */
2271 /* select antenna */
2275 struct rtl_hal_usbint_cfg {
2282 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2283 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2284 struct sk_buff_head *);
2287 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2288 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2290 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2291 struct sk_buff_head *);
2293 /* endpoint mapping */
2294 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2295 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2298 struct rtl_hal_cfg {
2300 bool write_readback;
2303 struct rtl_hal_ops *ops;
2304 struct rtl_mod_params *mod_params;
2305 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2307 /*this map used for some registers or vars
2308 defined int HAL but used in MAIN */
2309 u32 maps[RTL_VAR_MAP_MAX];
2315 struct mutex conf_mutex;
2316 struct mutex ps_mutex;
2319 spinlock_t ips_lock;
2320 spinlock_t irq_th_lock;
2321 spinlock_t irq_pci_lock;
2323 spinlock_t h2c_lock;
2324 spinlock_t rf_ps_lock;
2326 spinlock_t lps_lock;
2327 spinlock_t waitq_lock;
2328 spinlock_t entry_list_lock;
2329 spinlock_t usb_lock;
2330 spinlock_t c2hcmd_lock;
2331 spinlock_t scan_list_lock; /* lock for the scan list */
2333 /*FW clock change */
2334 spinlock_t fw_ps_lock;
2337 spinlock_t cck_and_rw_pagea_lock;
2340 spinlock_t check_sendpkt_lock;
2342 spinlock_t iqk_lock;
2346 struct ieee80211_hw *hw;
2349 struct timer_list watchdog_timer;
2350 struct timer_list dualmac_easyconcurrent_retrytimer;
2351 struct timer_list fw_clockoff_timer;
2352 struct timer_list fast_antenna_training_timer;
2354 struct tasklet_struct irq_tasklet;
2355 struct tasklet_struct irq_prepare_bcn_tasklet;
2358 struct workqueue_struct *rtl_wq;
2359 struct delayed_work watchdog_wq;
2360 struct delayed_work ips_nic_off_wq;
2361 struct delayed_work c2hcmd_wq;
2364 struct delayed_work ps_work;
2365 struct delayed_work ps_rfon_wq;
2366 struct delayed_work fwevt_wq;
2368 struct work_struct lps_change_work;
2369 struct work_struct fill_h2c_cmd;
2372 #define MIMO_PS_STATIC 0
2373 #define MIMO_PS_DYNAMIC 1
2374 #define MIMO_PS_NOLIMIT 3
2376 struct rtl_dualmac_easy_concurrent_ctl {
2377 enum band_type currentbandtype_backfordmdp;
2378 bool close_bbandrf_for_dmsp;
2379 bool change_to_dmdp;
2380 bool change_to_dmsp;
2381 bool switch_in_process;
2384 struct rtl_dmsp_ctl {
2385 bool activescan_for_slaveofdmsp;
2386 bool scan_for_anothermac_fordmsp;
2387 bool scan_for_itself_fordmsp;
2388 bool writedig_for_anothermacofdmsp;
2389 u32 curdigvalue_for_anothermacofdmsp;
2390 bool changecckpdstate_for_anothermacofdmsp;
2391 u8 curcckpdstate_for_anothermacofdmsp;
2392 bool changetxhighpowerlvl_for_anothermacofdmsp;
2393 u8 curtxhighlvl_for_anothermacofdmsp;
2394 long rssivalmin_for_anothermacofdmsp;
2408 u32 rssi_highthresh;
2411 long last_min_undec_pwdb_for_dm;
2412 long rssi_highpower_lowthresh;
2413 long rssi_highpower_highthresh;
2419 u8 dig_ext_port_stage;
2421 u8 dig_twoport_algorithm;
2423 u8 dig_slgorithm_switch;
2426 u8 curmultista_cstate;
2433 u8 min_undec_pwdb_for_dm;
2435 u8 pre_cck_cca_thres;
2436 u8 cur_cck_cca_thres;
2437 u8 pre_cck_pd_state;
2438 u8 cur_cck_pd_state;
2439 u8 pre_cck_fa_state;
2440 u8 cur_cck_fa_state;
2446 u8 dig_highpwrstate;
2453 u8 cur_cs_ratiostate;
2454 u8 pre_cs_ratiostate;
2455 u8 backoff_enable_flag;
2456 s8 backoffval_range_max;
2457 s8 backoffval_range_min;
2461 bool media_connect_0;
2462 bool media_connect_1;
2464 u32 antdiv_rssi_max;
2468 struct rtl_global_var {
2469 /* from this list we can get
2470 * other adapter's rtl_priv */
2471 struct list_head glb_priv_list;
2472 spinlock_t glb_list_lock;
2475 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2477 struct rtl_btc_info {
2485 unsigned long in_4way_ts;
2488 struct bt_coexist_info {
2489 struct rtl_btc_ops *btc_ops;
2490 struct rtl_btc_info btc_info;
2491 /* EEPROM BT info. */
2492 u8 eeprom_bt_coexist;
2494 u8 eeprom_bt_ant_num;
2495 u8 eeprom_bt_ant_isol;
2496 u8 eeprom_bt_radio_shared;
2502 u8 bt_cur_state; /* 0:on, 1:off */
2503 u8 bt_ant_isolation; /* 0:good, 1:bad */
2504 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2506 u8 bt_radio_shared_type;
2507 u8 bt_rfreg_origin_1e;
2508 u8 bt_rfreg_origin_1f;
2516 bool bt_busy_traffic;
2517 bool bt_traffic_mode_set;
2518 bool bt_non_traffic_mode_set;
2520 bool fw_coexist_all_off;
2521 bool sw_coexist_all_off;
2522 bool hw_coexist_all_off;
2526 u32 previous_state_h;
2528 u8 bt_pre_rssi_state;
2529 u8 bt_pre_rssi_state1;
2534 u8 bt_active_zero_cnt;
2535 bool cur_bt_disabled;
2536 bool pre_bt_disabled;
2539 u8 bt_profile_action;
2541 bool hold_for_bt_operation;
2545 struct rtl_btc_ops {
2546 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2547 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2548 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2549 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2550 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2551 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2552 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2553 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2554 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2555 enum rt_media_status mstatus);
2556 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2557 void (*btc_halt_notify) (void);
2558 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2559 u8 *tmp_buf, u8 length);
2560 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2561 u8 *tmp_buf, u8 length);
2562 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2563 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2564 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2565 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2567 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2568 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2569 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2570 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2571 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2572 u8 *ctrl_agg_size, u8 *agg_size);
2573 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2579 void *proximity_priv;
2580 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2581 struct sk_buff *skb);
2582 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2586 struct list_head list;
2592 struct rtl_bssid_entry {
2593 struct list_head list;
2598 struct rtl_scan_list {
2600 struct list_head list; /* sort by age */
2604 struct ieee80211_hw *hw;
2605 struct completion firmware_loading_complete;
2606 struct list_head list;
2607 struct rtl_priv *buddy_priv;
2608 struct rtl_global_var *glb_var;
2609 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2610 struct rtl_dmsp_ctl dmsp_ctl;
2611 struct rtl_locks locks;
2612 struct rtl_works works;
2613 struct rtl_mac mac80211;
2614 struct rtl_hal rtlhal;
2615 struct rtl_regulatory regd;
2616 struct rtl_rfkill rfkill;
2620 struct rtl_security sec;
2621 struct rtl_efuse efuse;
2622 struct rtl_led_ctl ledctl;
2623 struct rtl_tx_report tx_report;
2624 struct rtl_scan_list scan_list;
2626 struct rtl_ps_ctl psc;
2627 struct rate_adaptive ra;
2628 struct dynamic_primary_cca primarycca;
2629 struct wireless_stats stats;
2630 struct rt_link_detect link_info;
2631 struct false_alarm_statistics falsealm_cnt;
2633 struct rtl_rate_priv *rate_priv;
2635 /* sta entry list for ap adhoc or mesh */
2636 struct list_head entry_list;
2638 /* c2hcmd list for kthread level access */
2639 struct list_head c2hcmd_list;
2644 *hal_cfg : for diff cards
2645 *intf_ops : for diff interrface usb/pcie
2647 struct rtl_hal_cfg *cfg;
2648 const struct rtl_intf_ops *intf_ops;
2650 /*this var will be set by set_bit,
2651 and was used to indicate status of
2652 interface or hardware */
2653 unsigned long status;
2656 struct dig_t dm_digtable;
2657 struct ps_t dm_pstable;
2663 bool reg_init; /* true if regs saved */
2664 bool bt_operation_on;
2668 bool enter_ps; /* true when entering PS */
2671 /* intel Proximity, should be alloc mem
2672 * in intel Proximity module and can only
2673 * be used in intel Proximity mode
2675 struct proxim proximity;
2677 /*for bt coexist use*/
2678 struct bt_coexist_info btcoexist;
2680 /* separate 92ee from other ICs,
2681 * 92ee use new trx flow.
2683 bool use_new_trx_flow;
2686 struct wiphy_wowlan_support wowlan;
2688 /*This must be the last item so
2689 that it points to the data allocated
2690 beyond this structure like:
2691 rtl_pci_priv or rtl_usb_priv */
2692 u8 priv[0] __aligned(sizeof(void *));
2695 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2696 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2697 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2698 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2699 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2702 /***************************************
2703 Bluetooth Co-existence Related
2704 ****************************************/
2730 enum bt_total_ant_num {
2740 enum bt_service_type {
2747 BT_OTHER_ACTION = 6,
2753 enum bt_radio_shared {
2754 BT_RADIO_SHARED = 0,
2755 BT_RADIO_INDIVIDUAL = 1,
2759 /****************************************
2760 mem access macro define start
2761 Call endian free function when
2762 1. Read/write packet content.
2763 2. Before write integer to IO.
2764 3. After read integer from IO.
2765 ****************************************/
2766 /* Convert little data endian to host ordering */
2767 #define EF1BYTE(_val) \
2769 #define EF2BYTE(_val) \
2771 #define EF4BYTE(_val) \
2774 /* Read data from memory */
2775 #define READEF1BYTE(_ptr) \
2776 EF1BYTE(*((u8 *)(_ptr)))
2777 /* Read le16 data from memory and convert to host ordering */
2778 #define READEF2BYTE(_ptr) \
2780 #define READEF4BYTE(_ptr) \
2783 /* Create a bit mask
2785 * BIT_LEN_MASK_32(0) => 0x00000000
2786 * BIT_LEN_MASK_32(1) => 0x00000001
2787 * BIT_LEN_MASK_32(2) => 0x00000003
2788 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2790 #define BIT_LEN_MASK_32(__bitlen) \
2791 (0xFFFFFFFF >> (32 - (__bitlen)))
2792 #define BIT_LEN_MASK_16(__bitlen) \
2793 (0xFFFF >> (16 - (__bitlen)))
2794 #define BIT_LEN_MASK_8(__bitlen) \
2795 (0xFF >> (8 - (__bitlen)))
2797 /* Create an offset bit mask
2799 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2800 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2802 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2803 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2804 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2805 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2806 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2807 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2810 * Return 4-byte value in host byte ordering from
2811 * 4-byte pointer in little-endian system.
2813 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2814 (EF4BYTE(*((__le32 *)(__pstart))))
2815 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2816 (EF2BYTE(*((__le16 *)(__pstart))))
2817 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2818 (EF1BYTE(*((u8 *)(__pstart))))
2821 Translate subfield (continuous bits in little-endian) of 4-byte
2822 value to host byte ordering.*/
2823 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2825 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2826 BIT_LEN_MASK_32(__bitlen) \
2828 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2830 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2831 BIT_LEN_MASK_16(__bitlen) \
2833 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2835 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2836 BIT_LEN_MASK_8(__bitlen) \
2840 * Mask subfield (continuous bits in little-endian) of 4-byte value
2841 * and return the result in 4-byte value in host byte ordering.
2843 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2845 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2846 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2848 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2850 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2851 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2853 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2855 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2856 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2860 * Set subfield of little-endian 4-byte value to specified value.
2862 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2863 *((__le32 *)(__pstart)) = \
2865 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2866 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2868 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2869 *((__le16 *)(__pstart)) = \
2871 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2872 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2874 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2875 *((u8 *)(__pstart)) = EF1BYTE \
2877 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2878 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2881 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2882 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2884 /****************************************
2885 mem access macro define end
2886 ****************************************/
2888 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2890 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2891 #define RTL_WATCH_DOG_TIME 2000
2892 #define MSECS(t) msecs_to_jiffies(t)
2893 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2894 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2895 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2896 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2897 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2899 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2900 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2901 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2902 /*NIC halt, re-initialize hw parameters*/
2903 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2904 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2905 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2906 /*Always enable ASPM and Clock Req in initialization.*/
2907 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2908 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2909 #define RT_PS_LEVEL_ASPM BIT(7)
2910 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2911 #define RT_RF_LPS_DISALBE_2R BIT(30)
2912 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2913 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2914 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2915 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2916 (ppsc->cur_ps_level &= (~(_ps_flg)))
2917 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2918 (ppsc->cur_ps_level |= _ps_flg)
2920 #define container_of_dwork_rtl(x, y, z) \
2921 container_of(to_delayed_work(x), y, z)
2923 #define FILL_OCTET_STRING(_os, _octet, _len) \
2924 (_os).octet = (u8 *)(_octet); \
2925 (_os).length = (_len);
2927 #define CP_MACADDR(des, src) \
2928 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2929 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2930 (des)[4] = (src)[4], (des)[5] = (src)[5])
2932 #define LDPC_HT_ENABLE_RX BIT(0)
2933 #define LDPC_HT_ENABLE_TX BIT(1)
2934 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2935 #define LDPC_HT_CAP_TX BIT(3)
2937 #define STBC_HT_ENABLE_RX BIT(0)
2938 #define STBC_HT_ENABLE_TX BIT(1)
2939 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2940 #define STBC_HT_CAP_TX BIT(3)
2942 #define LDPC_VHT_ENABLE_RX BIT(0)
2943 #define LDPC_VHT_ENABLE_TX BIT(1)
2944 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2945 #define LDPC_VHT_CAP_TX BIT(3)
2947 #define STBC_VHT_ENABLE_RX BIT(0)
2948 #define STBC_VHT_ENABLE_TX BIT(1)
2949 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2950 #define STBC_VHT_CAP_TX BIT(3)
2952 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2954 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2956 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2958 return rtlpriv->io.read8_sync(rtlpriv, addr);
2961 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2963 return rtlpriv->io.read16_sync(rtlpriv, addr);
2966 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2968 return rtlpriv->io.read32_sync(rtlpriv, addr);
2971 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2973 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2975 if (rtlpriv->cfg->write_readback)
2976 rtlpriv->io.read8_sync(rtlpriv, addr);
2979 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
2982 struct rtl_priv *rtlpriv = rtl_priv(hw);
2984 rtl_write_byte(rtlpriv, addr, (u8)val8);
2987 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2989 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2991 if (rtlpriv->cfg->write_readback)
2992 rtlpriv->io.read16_sync(rtlpriv, addr);
2995 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2996 u32 addr, u32 val32)
2998 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3000 if (rtlpriv->cfg->write_readback)
3001 rtlpriv->io.read32_sync(rtlpriv, addr);
3004 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3005 u32 regaddr, u32 bitmask)
3007 struct rtl_priv *rtlpriv = hw->priv;
3009 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3012 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3013 u32 bitmask, u32 data)
3015 struct rtl_priv *rtlpriv = hw->priv;
3017 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3020 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3021 u32 regaddr, u32 data)
3023 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3026 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3027 enum radio_path rfpath, u32 regaddr,
3030 struct rtl_priv *rtlpriv = hw->priv;
3032 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3035 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3036 enum radio_path rfpath, u32 regaddr,
3037 u32 bitmask, u32 data)
3039 struct rtl_priv *rtlpriv = hw->priv;
3041 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3044 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3046 return (_HAL_STATE_STOP == rtlhal->state);
3049 static inline void set_hal_start(struct rtl_hal *rtlhal)
3051 rtlhal->state = _HAL_STATE_START;
3054 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3056 rtlhal->state = _HAL_STATE_STOP;
3059 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3061 return rtlphy->rf_type;
3064 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3066 return (struct ieee80211_hdr *)(skb->data);
3069 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3071 return rtl_get_hdr(skb)->frame_control;
3074 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3076 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3079 static inline u16 rtl_get_tid(struct sk_buff *skb)
3081 return rtl_get_tid_h(rtl_get_hdr(skb));
3084 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3085 struct ieee80211_vif *vif,
3088 return ieee80211_find_sta(vif, bssid);
3091 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3094 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3095 return ieee80211_find_sta(mac->vif, mac_addr);