drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54         while (skb_queue_len(&ring->queue)) {
  55                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57
  58                 pci_unmap_single(rtlpci->pdev,
  59                                  rtlpriv->cfg->ops->get_desc(
  60                                  hw,
  61                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  62                                  skb->len, PCI_DMA_TODEVICE);
  63                 kfree_skb(skb);
  64                 ring->idx = (ring->idx + 1) % ring->entries;
  65         }
  66         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  67 }
  68
  69 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  70                                         u8 set_bits, u8 clear_bits)
  71 {
  72         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  73         struct rtl_priv *rtlpriv = rtl_priv(hw);
  74
  75         rtlpci->reg_bcn_ctrl_val |= set_bits;
  76         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  77
  78         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  79 }
  80
  81 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  82 {
  83         struct rtl_priv *rtlpriv = rtl_priv(hw);
  84         u8 tmp1byte;
  85
  86         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  87         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  88         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  89         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  90         tmp1byte &= ~(BIT(0));
  91         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  92 }
  93
  94 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         u8 tmp1byte;
  98
  99         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 100         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 101         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 102         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 103         tmp1byte |= BIT(0);
 104         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 105 }
 106
 107 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 108 {
 109         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 110 }
 111
 112 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 113 {
 114         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 115 }
 116
 117 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 118                                        u8 rpwm_val, bool b_need_turn_off_ckk)
 119 {
 120         struct rtl_priv *rtlpriv = rtl_priv(hw);
 121         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 122         bool b_support_remote_wake_up;
 123         u32 count = 0, isr_regaddr, content;
 124         bool b_schedule_timer = b_need_turn_off_ckk;
 125
 126         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 127                                         (u8 *)(&b_support_remote_wake_up));
 128
 129         if (!rtlhal->fw_ready)
 130                 return;
 131         if (!rtlpriv->psc.fw_current_inpsmode)
 132                 return;
 133
 134         while (1) {
 135                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 136                 if (rtlhal->fw_clk_change_in_progress) {
 137                         while (rtlhal->fw_clk_change_in_progress) {
 138                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 139                                 count++;
 140                                 udelay(100);
 141                                 if (count > 1000)
 142                                         goto change_done;
 143                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 144                         }
 145                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 146                 } else {
 147                         rtlhal->fw_clk_change_in_progress = false;
 148                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 149                         goto change_done;
 150                 }
 151         }
 152 change_done:
 153         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 154                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 155                                         (u8 *)(&rpwm_val));
 156                 if (FW_PS_IS_ACK(rpwm_val)) {
 157                         isr_regaddr = REG_HISR;
 158                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 159                         while (!(content & IMR_CPWM) && (count < 500)) {
 160                                 udelay(50);
 161                                 count++;
 162                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 163                         }
 164
 165                         if (content & IMR_CPWM) {
 166                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 167                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 168                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 169                                          "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
 170                                          rtlhal->fw_ps_state);
 171                         }
 172                 }
 173
 174                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 175                 rtlhal->fw_clk_change_in_progress = false;
 176                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 177                 if (b_schedule_timer)
 178                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 179                                   jiffies + MSECS(10));
 180         } else  {
 181                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 182                 rtlhal->fw_clk_change_in_progress = false;
 183                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 184         }
 185 }
 186
 187 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 188                                         u8 rpwm_val)
 189 {
 190         struct rtl_priv *rtlpriv = rtl_priv(hw);
 191         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 192         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 193         struct rtl8192_tx_ring *ring;
 194         enum rf_pwrstate rtstate;
 195         bool b_schedule_timer = false;
 196         u8 queue;
 197
 198         if (!rtlhal->fw_ready)
 199                 return;
 200         if (!rtlpriv->psc.fw_current_inpsmode)
 201                 return;
 202         if (!rtlhal->allow_sw_to_change_hwclc)
 203                 return;
 204         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 205         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 206                 return;
 207
 208         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 209                 ring = &rtlpci->tx_ring[queue];
 210                 if (skb_queue_len(&ring->queue)) {
 211                         b_schedule_timer = true;
 212                         break;
 213                 }
 214         }
 215
 216         if (b_schedule_timer) {
 217                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 218                           jiffies + MSECS(10));
 219                 return;
 220         }
 221
 222         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 223                 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 224                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 225                 if (!rtlhal->fw_clk_change_in_progress) {
 226                         rtlhal->fw_clk_change_in_progress = true;
 227                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 228                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 229                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 230                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 231                                                       (u8 *)(&rpwm_val));
 232                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 233                         rtlhal->fw_clk_change_in_progress = false;
 234                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 235                 } else {
 236                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 237                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 238                                   jiffies + MSECS(10));
 239                 }
 240         }
 241 }
 242
 243 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 244 {
 245         u8 rpwm_val = 0;
 246
 247         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 248         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 249 }
 250
 251 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 252 {
 253         struct rtl_priv *rtlpriv = rtl_priv(hw);
 254         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 255         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 256         bool fw_current_inps = false;
 257         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 258
 259         if (ppsc->low_power_enable) {
 260                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 261                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 262                 rtlhal->allow_sw_to_change_hwclc = false;
 263                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 264                                 (u8 *)(&fw_pwrmode));
 265                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 266                                 (u8 *)(&fw_current_inps));
 267         } else {
 268                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 269                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 270                                 (u8 *)(&rpwm_val));
 271                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 272                                 (u8 *)(&fw_pwrmode));
 273                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 274                                 (u8 *)(&fw_current_inps));
 275         }
 276 }
 277
 278 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 279 {
 280         struct rtl_priv *rtlpriv = rtl_priv(hw);
 281         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 282         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 283         bool fw_current_inps = true;
 284         u8 rpwm_val;
 285
 286         if (ppsc->low_power_enable) {
 287                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 288                 rtlpriv->cfg->ops->set_hw_reg(hw,
 289                                 HW_VAR_FW_PSMODE_STATUS,
 290                                 (u8 *)(&fw_current_inps));
 291                 rtlpriv->cfg->ops->set_hw_reg(hw,
 292                                 HW_VAR_H2C_FW_PWRMODE,
 293                                 (u8 *)(&ppsc->fwctrl_psmode));
 294                 rtlhal->allow_sw_to_change_hwclc = true;
 295                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 296         } else {
 297                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 298                 rtlpriv->cfg->ops->set_hw_reg(hw,
 299                                 HW_VAR_FW_PSMODE_STATUS,
 300                                 (u8 *)(&fw_current_inps));
 301                 rtlpriv->cfg->ops->set_hw_reg(hw,
 302                                 HW_VAR_H2C_FW_PWRMODE,
 303                                 (u8 *)(&ppsc->fwctrl_psmode));
 304                 rtlpriv->cfg->ops->set_hw_reg(hw,
 305                                 HW_VAR_SET_RPWM,
 306                                 (u8 *)(&rpwm_val));
 307         }
 308 }
 309
 310 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
 311                                           bool dl_whole_packets)
 312 {
 313         struct rtl_priv *rtlpriv = rtl_priv(hw);
 314         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 315         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 316         u8 count = 0, dlbcn_count = 0;
 317         bool send_beacon = false;
 318
 319         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 320         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
 321
 322         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 323         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 324
 325         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 326         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 327                        tmp_reg422 & (~BIT(6)));
 328         if (tmp_reg422 & BIT(6))
 329                 send_beacon = true;
 330
 331         do {
 332                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 333                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 334                                (bcnvalid_reg | BIT(0)));
 335                 _rtl8821ae_return_beacon_queue_skb(hw);
 336
 337                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 338                         rtl8812ae_set_fw_rsvdpagepkt(hw, false,
 339                                                      dl_whole_packets);
 340                 else
 341                         rtl8821ae_set_fw_rsvdpagepkt(hw, false,
 342                                                      dl_whole_packets);
 343
 344                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 345                 count = 0;
 346                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 347                         count++;
 348                         udelay(10);
 349                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 350                 }
 351                 dlbcn_count++;
 352         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 353
 354         if (!(bcnvalid_reg & BIT(0)))
 355                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 356                          "Download RSVD page failed!\n");
 357         if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
 358                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
 359                 _rtl8821ae_return_beacon_queue_skb(hw);
 360                 if (send_beacon) {
 361                         dlbcn_count = 0;
 362                         do {
 363                                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 364                                                bcnvalid_reg | BIT(0));
 365
 366                                 _rtl8821ae_return_beacon_queue_skb(hw);
 367
 368                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 369                                         rtl8812ae_set_fw_rsvdpagepkt(hw, true,
 370                                                                      false);
 371                                 else
 372                                         rtl8821ae_set_fw_rsvdpagepkt(hw, true,
 373                                                                      false);
 374
 375                                 /* check rsvd page download OK. */
 376                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 377                                                              REG_TDECTRL + 2);
 378                                 count = 0;
 379                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 380                                         count++;
 381                                         udelay(10);
 382                                         bcnvalid_reg =
 383                                           rtl_read_byte(rtlpriv,
 384                                                         REG_TDECTRL + 2);
 385                                 }
 386                                 dlbcn_count++;
 387                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 388
 389                         if (!(bcnvalid_reg & BIT(0)))
 390                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 391                                          "2 Download RSVD page failed!\n");
 392                 }
 393         }
 394
 395         if (bcnvalid_reg & BIT(0))
 396                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 397
 398         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 399         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 400
 401         if (send_beacon)
 402                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 403
 404         if (!rtlhal->enter_pnp_sleep) {
 405                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 406                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 407         }
 408 }
 409
 410 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 411 {
 412         struct rtl_priv *rtlpriv = rtl_priv(hw);
 413         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 414         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 415         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 416
 417         switch (variable) {
 418         case HW_VAR_ETHER_ADDR:
 419                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 420                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 421                 break;
 422         case HW_VAR_BSSID:
 423                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 424                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 425                 break;
 426         case HW_VAR_MEDIA_STATUS:
 427                 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
 428                 break;
 429         case HW_VAR_SLOT_TIME:
 430                 *((u8 *)(val)) = mac->slot_time;
 431                 break;
 432         case HW_VAR_BEACON_INTERVAL:
 433                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 434                 break;
 435         case HW_VAR_ATIM_WINDOW:
 436                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 437                 break;
 438         case HW_VAR_RCR:
 439                 *((u32 *)(val)) = rtlpci->receive_config;
 440                 break;
 441         case HW_VAR_RF_STATE:
 442                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 443                 break;
 444         case HW_VAR_FWLPS_RF_ON:{
 445                 enum rf_pwrstate rfstate;
 446                 u32 val_rcr;
 447
 448                 rtlpriv->cfg->ops->get_hw_reg(hw,
 449                                               HW_VAR_RF_STATE,
 450                                               (u8 *)(&rfstate));
 451                 if (rfstate == ERFOFF) {
 452                         *((bool *)(val)) = true;
 453                 } else {
 454                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 455                         val_rcr &= 0x00070000;
 456                         if (val_rcr)
 457                                 *((bool *)(val)) = false;
 458                         else
 459                                 *((bool *)(val)) = true;
 460                 }
 461                 break; }
 462         case HW_VAR_FW_PSMODE_STATUS:
 463                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 464                 break;
 465         case HW_VAR_CORRECT_TSF:{
 466                 u64 tsf;
 467                 u32 *ptsf_low = (u32 *)&tsf;
 468                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 469
 470                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 471                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 472
 473                 *((u64 *)(val)) = tsf;
 474
 475                 break; }
 476         case HAL_DEF_WOWLAN:
 477                 if (ppsc->wo_wlan_mode)
 478                         *((bool *)(val)) = true;
 479                 else
 480                         *((bool *)(val)) = false;
 481                 break;
 482         default:
 483                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 484                          "switch case %#x not processed\n", variable);
 485                 break;
 486         }
 487 }
 488
 489 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 490 {
 491         struct rtl_priv *rtlpriv = rtl_priv(hw);
 492         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 493         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 494         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 495         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 496         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 497         u8 idx;
 498
 499         switch (variable) {
 500         case HW_VAR_ETHER_ADDR:{
 501                         for (idx = 0; idx < ETH_ALEN; idx++) {
 502                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 503                                                val[idx]);
 504                         }
 505                         break;
 506                 }
 507         case HW_VAR_BASIC_RATE:{
 508                         u16 b_rate_cfg = ((u16 *)val)[0];
 509                         b_rate_cfg = b_rate_cfg & 0x15f;
 510                         rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
 511                         break;
 512                 }
 513         case HW_VAR_BSSID:{
 514                         for (idx = 0; idx < ETH_ALEN; idx++) {
 515                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 516                                                val[idx]);
 517                         }
 518                         break;
 519                 }
 520         case HW_VAR_SIFS:
 521                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 522                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
 523
 524                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 525                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 526
 527                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 528                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
 529                 break;
 530         case HW_VAR_R2T_SIFS:
 531                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 532                 break;
 533         case HW_VAR_SLOT_TIME:{
 534                 u8 e_aci;
 535
 536                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 537                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 538
 539                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 540
 541                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 542                         rtlpriv->cfg->ops->set_hw_reg(hw,
 543                                                       HW_VAR_AC_PARAM,
 544                                                       (u8 *)(&e_aci));
 545                 }
 546                 break; }
 547         case HW_VAR_ACK_PREAMBLE:{
 548                 u8 reg_tmp;
 549                 u8 short_preamble = (bool)(*(u8 *)val);
 550
 551                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 552                 if (short_preamble) {
 553                         reg_tmp |= BIT(1);
 554                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
 555                                        reg_tmp);
 556                 } else {
 557                         reg_tmp &= (~BIT(1));
 558                         rtl_write_byte(rtlpriv,
 559                                 REG_TRXPTCL_CTL + 2,
 560                                 reg_tmp);
 561                 }
 562                 break; }
 563         case HW_VAR_WPA_CONFIG:
 564                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 565                 break;
 566         case HW_VAR_AMPDU_MIN_SPACE:{
 567                 u8 min_spacing_to_set;
 568                 u8 sec_min_space;
 569
 570                 min_spacing_to_set = *((u8 *)val);
 571                 if (min_spacing_to_set <= 7) {
 572                         sec_min_space = 0;
 573
 574                         if (min_spacing_to_set < sec_min_space)
 575                                 min_spacing_to_set = sec_min_space;
 576
 577                         mac->min_space_cfg = ((mac->min_space_cfg &
 578                                                0xf8) |
 579                                               min_spacing_to_set);
 580
 581                         *val = min_spacing_to_set;
 582
 583                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 584                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 585                                   mac->min_space_cfg);
 586
 587                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 588                                        mac->min_space_cfg);
 589                 }
 590                 break; }
 591         case HW_VAR_SHORTGI_DENSITY:{
 592                 u8 density_to_set;
 593
 594                 density_to_set = *((u8 *)val);
 595                 mac->min_space_cfg |= (density_to_set << 3);
 596
 597                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 598                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 599                           mac->min_space_cfg);
 600
 601                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 602                                mac->min_space_cfg);
 603
 604                 break; }
 605         case HW_VAR_AMPDU_FACTOR:{
 606                 u32     ampdu_len =  (*((u8 *)val));
 607
 608                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 609                         if (ampdu_len < VHT_AGG_SIZE_128K)
 610                                 ampdu_len =
 611                                         (0x2000 << (*((u8 *)val))) - 1;
 612                         else
 613                                 ampdu_len = 0x1ffff;
 614                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 615                         if (ampdu_len < HT_AGG_SIZE_64K)
 616                                 ampdu_len =
 617                                         (0x2000 << (*((u8 *)val))) - 1;
 618                         else
 619                                 ampdu_len = 0xffff;
 620                 }
 621                 ampdu_len |= BIT(31);
 622
 623                 rtl_write_dword(rtlpriv,
 624                         REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 625                 break; }
 626         case HW_VAR_AC_PARAM:{
 627                 u8 e_aci = *((u8 *)val);
 628
 629                 rtl8821ae_dm_init_edca_turbo(hw);
 630                 if (rtlpci->acm_method != EACMWAY2_SW)
 631                         rtlpriv->cfg->ops->set_hw_reg(hw,
 632                                                       HW_VAR_ACM_CTRL,
 633                                                       (u8 *)(&e_aci));
 634                 break; }
 635         case HW_VAR_ACM_CTRL:{
 636                 u8 e_aci = *((u8 *)val);
 637                 union aci_aifsn *p_aci_aifsn =
 638                     (union aci_aifsn *)(&mac->ac[0].aifs);
 639                 u8 acm = p_aci_aifsn->f.acm;
 640                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 641
 642                 acm_ctrl =
 643                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 644
 645                 if (acm) {
 646                         switch (e_aci) {
 647                         case AC0_BE:
 648                                 acm_ctrl |= ACMHW_BEQEN;
 649                                 break;
 650                         case AC2_VI:
 651                                 acm_ctrl |= ACMHW_VIQEN;
 652                                 break;
 653                         case AC3_VO:
 654                                 acm_ctrl |= ACMHW_VOQEN;
 655                                 break;
 656                         default:
 657                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 658                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 659                                          acm);
 660                                 break;
 661                         }
 662                 } else {
 663                         switch (e_aci) {
 664                         case AC0_BE:
 665                                 acm_ctrl &= (~ACMHW_BEQEN);
 666                                 break;
 667                         case AC2_VI:
 668                                 acm_ctrl &= (~ACMHW_VIQEN);
 669                                 break;
 670                         case AC3_VO:
 671                                 acm_ctrl &= (~ACMHW_VOQEN);
 672                                 break;
 673                         default:
 674                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 675                                          "switch case %#x not processed\n",
 676                                          e_aci);
 677                                 break;
 678                         }
 679                 }
 680
 681                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 682                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 683                          acm_ctrl);
 684                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 685                 break; }
 686         case HW_VAR_RCR:
 687                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 688                 rtlpci->receive_config = ((u32 *)(val))[0];
 689                 break;
 690         case HW_VAR_RETRY_LIMIT:{
 691                 u8 retry_limit = ((u8 *)(val))[0];
 692
 693                 rtl_write_word(rtlpriv, REG_RL,
 694                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 695                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 696                 break; }
 697         case HW_VAR_DUAL_TSF_RST:
 698                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 699                 break;
 700         case HW_VAR_EFUSE_BYTES:
 701                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 702                 break;
 703         case HW_VAR_EFUSE_USAGE:
 704                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 705                 break;
 706         case HW_VAR_IO_CMD:
 707                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 708                 break;
 709         case HW_VAR_SET_RPWM:{
 710                 u8 rpwm_val;
 711
 712                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 713                 udelay(1);
 714
 715                 if (rpwm_val & BIT(7)) {
 716                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 717                                        (*(u8 *)val));
 718                 } else {
 719                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 720                                        ((*(u8 *)val) | BIT(7)));
 721                 }
 722
 723                 break; }
 724         case HW_VAR_H2C_FW_PWRMODE:
 725                 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 726                 break;
 727         case HW_VAR_FW_PSMODE_STATUS:
 728                 ppsc->fw_current_inpsmode = *((bool *)val);
 729                 break;
 730         case HW_VAR_INIT_RTS_RATE:
 731                 break;
 732         case HW_VAR_RESUME_CLK_ON:
 733                 _rtl8821ae_set_fw_ps_rf_on(hw);
 734                 break;
 735         case HW_VAR_FW_LPS_ACTION:{
 736                 bool b_enter_fwlps = *((bool *)val);
 737
 738                 if (b_enter_fwlps)
 739                         _rtl8821ae_fwlps_enter(hw);
 740                  else
 741                         _rtl8821ae_fwlps_leave(hw);
 742                  break; }
 743         case HW_VAR_H2C_FW_JOINBSSRPT:{
 744                 u8 mstatus = (*(u8 *)val);
 745
 746                 if (mstatus == RT_MEDIA_CONNECT) {
 747                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 748                                                       NULL);
 749                         _rtl8821ae_download_rsvd_page(hw, false);
 750                 }
 751                 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
 752
 753                 break; }
 754         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 755                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 756                 break;
 757         case HW_VAR_AID:{
 758                 u16 u2btmp;
 759                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 760                 u2btmp &= 0xC000;
 761                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 762                                mac->assoc_id));
 763                 break; }
 764         case HW_VAR_CORRECT_TSF:{
 765                 u8 btype_ibss = ((u8 *)(val))[0];
 766
 767                 if (btype_ibss)
 768                         _rtl8821ae_stop_tx_beacon(hw);
 769
 770                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 771
 772                 rtl_write_dword(rtlpriv, REG_TSFTR,
 773                                 (u32)(mac->tsf & 0xffffffff));
 774                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 775                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 776
 777                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 778
 779                 if (btype_ibss)
 780                         _rtl8821ae_resume_tx_beacon(hw);
 781                 break; }
 782         case HW_VAR_NAV_UPPER: {
 783                 u32     us_nav_upper = *(u32 *)val;
 784
 785                 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
 786                         RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
 787                                  "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
 788                                  us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
 789                         break;
 790                 }
 791                 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 792                                ((u8)((us_nav_upper +
 793                                 HAL_92C_NAV_UPPER_UNIT - 1) /
 794                                 HAL_92C_NAV_UPPER_UNIT)));
 795                 break; }
 796         case HW_VAR_KEEP_ALIVE: {
 797                 u8 array[2];
 798                 array[0] = 0xff;
 799                 array[1] = *((u8 *)val);
 800                 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
 801                                        array);
 802                 break; }
 803         default:
 804                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 805                          "switch case %#x not processed\n", variable);
 806                 break;
 807         }
 808 }
 809
 810 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 811 {
 812         struct rtl_priv *rtlpriv = rtl_priv(hw);
 813         bool status = true;
 814         long count = 0;
 815         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 816                     _LLT_OP(_LLT_WRITE_ACCESS);
 817
 818         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 819
 820         do {
 821                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 822                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 823                         break;
 824
 825                 if (count > POLLING_LLT_THRESHOLD) {
 826                         pr_err("Failed to polling write LLT done at address %d!\n",
 827                                address);
 828                         status = false;
 829                         break;
 830                 }
 831         } while (++count);
 832
 833         return status;
 834 }
 835
 836 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 837 {
 838         struct rtl_priv *rtlpriv = rtl_priv(hw);
 839         unsigned short i;
 840         u8 txpktbuf_bndy;
 841         u32 rqpn;
 842         u8 maxpage;
 843         bool status;
 844
 845         maxpage = 255;
 846         txpktbuf_bndy = 0xF7;
 847         rqpn = 0x80e60808;
 848
 849         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 850         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 851
 852         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 853
 854         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 855         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 856
 857         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 858         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 859
 860         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 861                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 862                 if (!status)
 863                         return status;
 864         }
 865
 866         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 867         if (!status)
 868                 return status;
 869
 870         for (i = txpktbuf_bndy; i < maxpage; i++) {
 871                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 872                 if (!status)
 873                         return status;
 874         }
 875
 876         status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
 877         if (!status)
 878                 return status;
 879
 880         rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
 881
 882         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 883
 884         return true;
 885 }
 886
 887 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 888 {
 889         struct rtl_priv *rtlpriv = rtl_priv(hw);
 890         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 891         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 892         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 893
 894         if (rtlpriv->rtlhal.up_first_time)
 895                 return;
 896
 897         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 898                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 899                         rtl8812ae_sw_led_on(hw, pled0);
 900                 else
 901                         rtl8821ae_sw_led_on(hw, pled0);
 902         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 903                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 904                         rtl8812ae_sw_led_on(hw, pled0);
 905                 else
 906                         rtl8821ae_sw_led_on(hw, pled0);
 907         else
 908                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 909                         rtl8812ae_sw_led_off(hw, pled0);
 910                 else
 911                         rtl8821ae_sw_led_off(hw, pled0);
 912 }
 913
 914 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 915 {
 916         struct rtl_priv *rtlpriv = rtl_priv(hw);
 917         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 918         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 919
 920         u8 bytetmp = 0;
 921         u16 wordtmp = 0;
 922         bool mac_func_enable = rtlhal->mac_func_enable;
 923
 924         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 925
 926         /*Auto Power Down to CHIP-off State*/
 927         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 928         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 929
 930         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 931                 /* HW Power on sequence*/
 932                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 933                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 934                                               RTL8812_NIC_ENABLE_FLOW)) {
 935                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 936                                          "init 8812 MAC Fail as power on failure\n");
 937                                 return false;
 938                 }
 939         } else {
 940                 /* HW Power on sequence */
 941                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
 942                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 943                                               RTL8821A_NIC_ENABLE_FLOW)){
 944                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 945                                 "init 8821 MAC Fail as power on failure\n");
 946                         return false;
 947                 }
 948         }
 949
 950         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 951         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 952
 953         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 954         bytetmp = 0xff;
 955         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 956         mdelay(2);
 957
 958         bytetmp = 0xff;
 959         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 960         mdelay(2);
 961
 962         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 963                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 964                 if (bytetmp & BIT(0)) {
 965                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 966                         bytetmp |= BIT(6);
 967                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 968                 }
 969         }
 970
 971         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 972         bytetmp &= ~BIT(4);
 973         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 974
 975         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 976
 977         if (!mac_func_enable) {
 978                 if (!_rtl8821ae_llt_table_init(hw))
 979                         return false;
 980         }
 981
 982         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 983         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 984
 985         /* Enable FW Beamformer Interrupt */
 986         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 987         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 988
 989         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 990         wordtmp &= 0xf;
 991         wordtmp |= 0xF5B1;
 992         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 993
 994         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 995         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 996         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 997         /*low address*/
 998         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 999                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1000         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1001                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1002         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1003                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1004         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1005                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1006         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1007                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1008         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1009                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1010         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1011                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1012         rtl_write_dword(rtlpriv, REG_RX_DESA,
1013                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1014
1015         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1016
1017         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1018
1019         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1020
1021         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1022         _rtl8821ae_gen_refresh_led_state(hw);
1023
1024         return true;
1025 }
1026
1027 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1028 {
1029         struct rtl_priv *rtlpriv = rtl_priv(hw);
1030         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1031         u32 reg_rrsr;
1032
1033         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1034
1035         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1036         /* ARFB table 9 for 11ac 5G 2SS */
1037         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1038         /* ARFB table 10 for 11ac 5G 1SS */
1039         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1040         /* ARFB table 11 for 11ac 24G 1SS */
1041         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1042         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1043         /* ARFB table 12 for 11ac 24G 1SS */
1044         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1045         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1046         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1047         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1048         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1049
1050         /*Set retry limit*/
1051         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1052
1053         /* Set Data / Response auto rate fallack retry count*/
1054         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1055         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1056         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1057         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1058
1059         rtlpci->reg_bcn_ctrl_val = 0x1d;
1060         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1061
1062         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1063         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1064
1065         /* AGGR_BK_TIME Reg51A 0x16 */
1066         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1067
1068         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1069         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1070
1071         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1072         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1073         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1074 }
1075
1076 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1077 {
1078         u16 ret = 0;
1079         u8 tmp = 0, count = 0;
1080
1081         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1082         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1083         count = 0;
1084         while (tmp && count < 20) {
1085                 udelay(10);
1086                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1087                 count++;
1088         }
1089         if (0 == tmp)
1090                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1091
1092         return ret;
1093 }
1094
1095 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1096 {
1097         u8 tmp = 0, count = 0;
1098
1099         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1100         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1101         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1102         count = 0;
1103         while (tmp && count < 20) {
1104                 udelay(10);
1105                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1106                 count++;
1107         }
1108 }
1109
1110 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1111 {
1112         u16 read_addr = addr & 0xfffc;
1113         u8 tmp = 0, count = 0, ret = 0;
1114
1115         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1116         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1117         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1118         count = 0;
1119         while (tmp && count < 20) {
1120                 udelay(10);
1121                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1122                 count++;
1123         }
1124         if (0 == tmp) {
1125                 read_addr = REG_DBI_RDATA + addr % 4;
1126                 ret = rtl_read_byte(rtlpriv, read_addr);
1127         }
1128         return ret;
1129 }
1130
1131 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1132 {
1133         u8 tmp = 0, count = 0;
1134         u16 write_addr, remainder = addr % 4;
1135
1136         write_addr = REG_DBI_WDATA + remainder;
1137         rtl_write_byte(rtlpriv, write_addr, data);
1138
1139         write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1140         rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1141
1142         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1143
1144         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1145         count = 0;
1146         while (tmp && count < 20) {
1147                 udelay(10);
1148                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1149                 count++;
1150         }
1151 }
1152
1153 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1154 {
1155         struct rtl_priv *rtlpriv = rtl_priv(hw);
1156         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1157         u8 tmp;
1158
1159         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1160                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1161                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1162
1163                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1164                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1165         }
1166
1167         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1168         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1169                              ASPM_L1_LATENCY << 3);
1170
1171         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1172         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1173
1174         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1175                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1176                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1177         }
1178 }
1179
1180 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1181 {
1182         struct rtl_priv *rtlpriv = rtl_priv(hw);
1183         u8 sec_reg_value;
1184         u8 tmp;
1185
1186         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1187                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1188                   rtlpriv->sec.pairwise_enc_algorithm,
1189                   rtlpriv->sec.group_enc_algorithm);
1190
1191         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1192                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1193                          "not open hw encryption\n");
1194                 return;
1195         }
1196
1197         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1198
1199         if (rtlpriv->sec.use_defaultkey) {
1200                 sec_reg_value |= SCR_TXUSEDK;
1201                 sec_reg_value |= SCR_RXUSEDK;
1202         }
1203
1204         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1205
1206         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1207         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1208
1209         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1210                  "The SECR-value %x\n", sec_reg_value);
1211
1212         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1213 }
1214
1215 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1216 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1217 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1218 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1219 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1220 /* ----------------------------------------------------------- */
1221
1222 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1223 {
1224         struct rtl_priv *rtlpriv = rtl_priv(hw);
1225         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1226                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1227                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1228
1229         rtlpriv->cfg->ops->set_hw_reg(hw,
1230                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1231
1232         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1233                  "Initialize MacId media status: from %d to %d\n",
1234                  MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1235                  MAC_ID_STATIC_FOR_BT_CLIENT_END);
1236 }
1237
1238 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1239 {
1240         struct rtl_priv *rtlpriv = rtl_priv(hw);
1241         u8 tmp;
1242
1243         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1244         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1245         if (!(tmp & BIT(2))) {
1246                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1247                 mdelay(100);
1248         }
1249
1250         /* read reg 0x350 Bit[25] if 1 : RX hang */
1251         /* read reg 0x350 Bit[24] if 1 : TX hang */
1252         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1253         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1254                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1255                          "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1256                 return true;
1257         } else {
1258                 return false;
1259         }
1260 }
1261
1262 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1263                                          bool mac_power_on,
1264                                          bool in_watchdog)
1265 {
1266         struct rtl_priv *rtlpriv = rtl_priv(hw);
1267         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1268         u8 tmp;
1269         bool release_mac_rx_pause;
1270         u8 backup_pcie_dma_pause;
1271
1272         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1273
1274         /* 1. Disable register write lock. 0x1c[1] = 0 */
1275         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1276         tmp &= ~(BIT(1));
1277         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1278         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1279                 /* write 0xCC bit[2] = 1'b1 */
1280                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1281                 tmp |= BIT(2);
1282                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1283         }
1284
1285         /* 2. Check and pause TRX DMA */
1286         /* write 0x284 bit[18] = 1'b1 */
1287         /* write 0x301 = 0xFF */
1288         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1289         if (tmp & BIT(2)) {
1290                 /* Already pause before the function for another purpose. */
1291                 release_mac_rx_pause = false;
1292         } else {
1293                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1294                 release_mac_rx_pause = true;
1295         }
1296         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1297         if (backup_pcie_dma_pause != 0xFF)
1298                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1299
1300         if (mac_power_on) {
1301                 /* 3. reset TRX function */
1302                 /* write 0x100 = 0x00 */
1303                 rtl_write_byte(rtlpriv, REG_CR, 0);
1304         }
1305
1306         /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1307         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1308         tmp &= ~(BIT(0));
1309         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1310
1311         /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1312         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1313         tmp |= BIT(0);
1314         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1315
1316         if (mac_power_on) {
1317                 /* 6. enable TRX function */
1318                 /* write 0x100 = 0xFF */
1319                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1320
1321                 /* We should init LLT & RQPN and
1322                  * prepare Tx/Rx descrptor address later
1323                  * because MAC function is reset.*/
1324         }
1325
1326         /* 7. Restore PCIe autoload down bit */
1327         /* 8812AE does not has the defination. */
1328         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1329                 /* write 0xF8 bit[17] = 1'b1 */
1330                 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1331                 tmp |= BIT(1);
1332                 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1333         }
1334
1335         /* In MAC power on state, BB and RF maybe in ON state,
1336          * if we release TRx DMA here.
1337          * it will cause packets to be started to Tx/Rx,
1338          * so we release Tx/Rx DMA later.*/
1339         if (!mac_power_on/* || in_watchdog*/) {
1340                 /* 8. release TRX DMA */
1341                 /* write 0x284 bit[18] = 1'b0 */
1342                 /* write 0x301 = 0x00 */
1343                 if (release_mac_rx_pause) {
1344                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1345                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1346                                        tmp & (~BIT(2)));
1347                 }
1348                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1349                                backup_pcie_dma_pause);
1350         }
1351
1352         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1353                 /* 9. lock system register */
1354                 /* write 0xCC bit[2] = 1'b0 */
1355                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1356                 tmp &= ~(BIT(2));
1357                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1358         }
1359         return true;
1360 }
1361
1362 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1363 {
1364         struct rtl_priv *rtlpriv = rtl_priv(hw);
1365         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1366         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1367         u8 fw_reason = 0;
1368
1369         fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1370
1371         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1372                  fw_reason);
1373
1374         ppsc->wakeup_reason = 0;
1375
1376         rtlhal->last_suspend_sec = ktime_get_real_seconds();
1377
1378         switch (fw_reason) {
1379         case FW_WOW_V2_PTK_UPDATE_EVENT:
1380                 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1381                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1382                          "It's a WOL PTK Key update event!\n");
1383                 break;
1384         case FW_WOW_V2_GTK_UPDATE_EVENT:
1385                 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1386                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1387                          "It's a WOL GTK Key update event!\n");
1388                 break;
1389         case FW_WOW_V2_DISASSOC_EVENT:
1390                 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1391                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1392                          "It's a disassociation event!\n");
1393                 break;
1394         case FW_WOW_V2_DEAUTH_EVENT:
1395                 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1396                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1397                          "It's a deauth event!\n");
1398                 break;
1399         case FW_WOW_V2_FW_DISCONNECT_EVENT:
1400                 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1401                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1402                          "It's a Fw disconnect decision (AP lost) event!\n");
1403         break;
1404         case FW_WOW_V2_MAGIC_PKT_EVENT:
1405                 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1406                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1407                          "It's a magic packet event!\n");
1408                 break;
1409         case FW_WOW_V2_UNICAST_PKT_EVENT:
1410                 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1411                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1412                          "It's an unicast packet event!\n");
1413                 break;
1414         case FW_WOW_V2_PATTERN_PKT_EVENT:
1415                 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1416                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1417                          "It's a pattern match event!\n");
1418                 break;
1419         case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1420                 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1421                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1422                          "It's an RTD3 Ssid match event!\n");
1423                 break;
1424         case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1425                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1426                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1427                          "It's an RealWoW wake packet event!\n");
1428                 break;
1429         case FW_WOW_V2_REALWOW_V2_ACKLOST:
1430                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1431                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1432                          "It's an RealWoW ack lost event!\n");
1433                 break;
1434         default:
1435                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1436                          "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1437                           fw_reason);
1438                 break;
1439         }
1440 }
1441
1442 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1443 {
1444         struct rtl_priv *rtlpriv = rtl_priv(hw);
1445         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1446
1447         /*low address*/
1448         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1449                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1450         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1451                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1452         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1453                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1454         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1455                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1456         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1457                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1458         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1459                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1460         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1461                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1462         rtl_write_dword(rtlpriv, REG_RX_DESA,
1463                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1464 }
1465
1466 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1467 {
1468         bool status = true;
1469         u32 i;
1470         u32 txpktbuf_bndy = boundary;
1471         u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1472
1473         for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1474                 status = _rtl8821ae_llt_write(hw, i , i + 1);
1475                 if (!status)
1476                         return status;
1477         }
1478
1479         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1480         if (!status)
1481                 return status;
1482
1483         for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1484                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1485                 if (!status)
1486                         return status;
1487         }
1488
1489         status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1490                                       txpktbuf_bndy);
1491         if (!status)
1492                 return status;
1493
1494         return status;
1495 }
1496
1497 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1498                              u16 npq_rqpn_value, u32 rqpn_val)
1499 {
1500         struct rtl_priv *rtlpriv = rtl_priv(hw);
1501         u8 tmp;
1502         bool ret = true;
1503         u16 count = 0, tmp16;
1504         bool support_remote_wakeup;
1505
1506         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1507                                       (u8 *)(&support_remote_wakeup));
1508
1509         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1510                  "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1511                   boundary, npq_rqpn_value, rqpn_val);
1512
1513         /* stop PCIe DMA
1514          * 1. 0x301[7:0] = 0xFE */
1515         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1516
1517         /* wait TXFF empty
1518          * 2. polling till 0x41A[15:0]=0x07FF */
1519         tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1520         while ((tmp16 & 0x07FF) != 0x07FF) {
1521                 udelay(100);
1522                 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1523                 count++;
1524                 if ((count % 200) == 0) {
1525                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1526                                  "Tx queue is not empty for 20ms!\n");
1527                 }
1528                 if (count >= 1000) {
1529                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1530                                  "Wait for Tx FIFO empty timeout!\n");
1531                         break;
1532                 }
1533         }
1534
1535         /* TX pause
1536          * 3. reg 0x522=0xFF */
1537         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1538
1539         /* Wait TX State Machine OK
1540          * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1541         count = 0;
1542         while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1543                 udelay(100);
1544                 count++;
1545                 if (count >= 500) {
1546                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1547                                  "Wait for TX State Machine ready timeout !!\n");
1548                         break;
1549                 }
1550         }
1551
1552         /* stop RX DMA path
1553          * 5.   0x284[18] = 1
1554          * 6.   wait till 0x284[17] == 1
1555          * wait RX DMA idle */
1556         count = 0;
1557         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1558         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1559         do {
1560                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1561                 udelay(10);
1562                 count++;
1563         } while (!(tmp & BIT(1)) && count < 100);
1564
1565         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1566                  "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1567                   count, tmp);
1568
1569         /* reset BB
1570          * 7.   0x02 [0] = 0 */
1571         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1572         tmp &= ~(BIT(0));
1573         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1574
1575         /* Reset TRX MAC
1576          * 8.    0x100 = 0x00
1577          * Delay (1ms) */
1578         rtl_write_byte(rtlpriv, REG_CR, 0x00);
1579         udelay(1000);
1580
1581         /* Disable MAC Security Engine
1582          * 9.   0x100 bit[9]=0 */
1583         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1584         tmp &= ~(BIT(1));
1585         rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1586
1587         /* To avoid DD-Tim Circuit hang
1588          * 10.  0x553 bit[5]=1 */
1589         tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1590         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1591
1592         /* Enable MAC Security Engine
1593          * 11.  0x100 bit[9]=1 */
1594         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1595         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1596
1597         /* Enable TRX MAC
1598          * 12.   0x100 = 0xFF
1599          *      Delay (1ms) */
1600         rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1601         udelay(1000);
1602
1603         /* Enable BB
1604          * 13.  0x02 [0] = 1 */
1605         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1606         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1607
1608         /* beacon setting
1609          * 14,15. set beacon head page (reg 0x209 and 0x424) */
1610         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1611         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1612         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1613
1614         /* 16.  WMAC_LBK_BF_HD 0x45D[7:0]
1615          * WMAC_LBK_BF_HD */
1616         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1617                        (u8)boundary);
1618
1619         rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1620
1621         /* init LLT
1622          * 17. init LLT */
1623         if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1624                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1625                          "Failed to init LLT table!\n");
1626                 return false;
1627         }
1628
1629         /* reallocate RQPN
1630          * 18. reallocate RQPN and init LLT */
1631         rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1632         rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1633
1634         /* release Tx pause
1635          * 19. 0x522=0x00 */
1636         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1637
1638         /* enable PCIE DMA
1639          * 20. 0x301[7:0] = 0x00
1640          * 21. 0x284[18] = 0 */
1641         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1642         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1643         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1644
1645         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1646         return ret;
1647 }
1648
1649 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1650 {
1651         struct rtl_priv *rtlpriv = rtl_priv(hw);
1652         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1653         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1654
1655 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1656         /* Re-download normal Fw. */
1657         rtl8821ae_set_fw_related_for_wowlan(hw, false);
1658 #endif
1659
1660         /* Re-Initialize LLT table. */
1661         if (rtlhal->re_init_llt_table) {
1662                 u32 rqpn = 0x80e70808;
1663                 u8 rqpn_npq = 0, boundary = 0xF8;
1664                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1665                         rqpn = 0x80e90808;
1666                         boundary = 0xFA;
1667                 }
1668                 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1669                         rtlhal->re_init_llt_table = false;
1670         }
1671
1672         ppsc->rfpwr_state = ERFON;
1673 }
1674
1675 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1676 {
1677         u8 tmp  = 0;
1678         struct rtl_priv *rtlpriv = rtl_priv(hw);
1679
1680         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1681
1682         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1683         if (!(tmp & (BIT(2) | BIT(3)))) {
1684                 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1685                          "0x160(%#x)return!!\n", tmp);
1686                 return;
1687         }
1688
1689         tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1690         _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1691
1692         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1693         _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1694
1695         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1696 }
1697
1698 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1699 {
1700         u8 tmp  = 0;
1701         struct rtl_priv *rtlpriv = rtl_priv(hw);
1702
1703         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1704
1705         /* Check 0x98[10] */
1706         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1707         if (!(tmp & BIT(2))) {
1708                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1709                          "<---0x99(%#x) return!!\n", tmp);
1710                 return;
1711         }
1712
1713         /* LTR idle latency, 0x90 for 144us */
1714         rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1715
1716         /* LTR active latency, 0x3c for 60us */
1717         rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1718
1719         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1720         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1721
1722         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1723         rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1724         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1725
1726         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1727 }
1728
1729 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1730 {
1731         struct rtl_priv *rtlpriv = rtl_priv(hw);
1732         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1733         bool init_finished = true;
1734         u8 tmp = 0;
1735
1736         /* Get Fw wake up reason. */
1737         _rtl8821ae_get_wakeup_reason(hw);
1738
1739         /* Patch Pcie Rx DMA hang after S3/S4 several times.
1740          * The root cause has not be found. */
1741         if (_rtl8821ae_check_pcie_dma_hang(hw))
1742                 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1743
1744         /* Prepare Tx/Rx Desc Hw address. */
1745         _rtl8821ae_init_trx_desc_hw_address(hw);
1746
1747         /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1748         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1749         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1750
1751         /* Check wake up event.
1752          * We should check wake packet bit before disable wowlan by H2C or
1753          * Fw will clear the bit. */
1754         tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1755         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1756                  "Read REG_FTISR 0x13f = %#X\n", tmp);
1757
1758         /* Set the WoWLAN related function control disable. */
1759         rtl8821ae_set_fw_wowlan_mode(hw, false);
1760         rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1761
1762         if (rtlhal->hw_rof_enable) {
1763                 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1764                 if (tmp & BIT(1)) {
1765                         /* Clear GPIO9 ISR */
1766                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1767                         init_finished = false;
1768                 } else {
1769                         init_finished = true;
1770                 }
1771         }
1772
1773         if (init_finished) {
1774                 _rtl8821ae_simple_initialize_adapter(hw);
1775
1776                 /* Release Pcie Interface Tx DMA. */
1777                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1778                 /* Release Pcie RX DMA */
1779                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1780
1781                 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1782                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1783
1784                 _rtl8821ae_enable_l1off(hw);
1785                 _rtl8821ae_enable_ltr(hw);
1786         }
1787
1788         return init_finished;
1789 }
1790
1791 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1792 {
1793         /* BB OFDM RX Path_A */
1794         rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1795         /* BB OFDM TX Path_A */
1796         rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1797         /* BB CCK R/Rx Path_A */
1798         rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1799         /* MCS support */
1800         rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1801         /* RF Path_B HSSI OFF */
1802         rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1803         /* RF Path_B Power Down */
1804         rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1805         /* ADDA Path_B OFF */
1806         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1807         rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1808 }
1809
1810 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1811 {
1812         struct rtl_priv *rtlpriv = rtl_priv(hw);
1813         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1814         u8 u1b_tmp;
1815
1816         rtlhal->mac_func_enable = false;
1817
1818         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1819                 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1820                 /* 1. Run LPS WL RFOFF flow */
1821                 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1822                 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1823                 */
1824                 rtl_hal_pwrseqcmdparsing(rtlpriv,
1825                         PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1826                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1827         }
1828         /* 2. 0x1F[7:0] = 0 */
1829         /* turn off RF */
1830         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1831         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1832                 rtlhal->fw_ready) {
1833                 rtl8821ae_firmware_selfreset(hw);
1834         }
1835
1836         /* Reset MCU. Suggested by Filen. */
1837         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1838         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1839
1840         /* g.   MCUFWDL 0x80[1:0]=0      */
1841         /* reset MCU ready status */
1842         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1843
1844         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1845                 /* HW card disable configuration. */
1846                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1847                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1848         } else {
1849                 /* HW card disable configuration. */
1850                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1851                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1852         }
1853
1854         /* Reset MCU IO Wrapper */
1855         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1856         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1857         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1858         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1859
1860         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1861         /* lock ISO/CLK/Power control register */
1862         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1863 }
1864
1865 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1866 {
1867         struct rtl_priv *rtlpriv = rtl_priv(hw);
1868         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1869         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1870         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1871         bool rtstatus = true;
1872         int err;
1873         u8 tmp_u1b;
1874         bool support_remote_wakeup;
1875         u32 nav_upper = WIFI_NAV_UPPER_US;
1876
1877         rtlhal->being_init_adapter = true;
1878         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1879                                       (u8 *)(&support_remote_wakeup));
1880         rtlpriv->intf_ops->disable_aspm(hw);
1881
1882         /*YP wowlan not considered*/
1883
1884         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1885         if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1886                 rtlhal->mac_func_enable = true;
1887                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1888                          "MAC has already power on.\n");
1889         } else {
1890                 rtlhal->mac_func_enable = false;
1891                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1892         }
1893
1894         if (support_remote_wakeup &&
1895                 rtlhal->wake_from_pnp_sleep &&
1896                 rtlhal->mac_func_enable) {
1897                 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1898                         rtlhal->being_init_adapter = false;
1899                         return 0;
1900                 }
1901         }
1902
1903         if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1904                 _rtl8821ae_reset_pcie_interface_dma(hw,
1905                                                     rtlhal->mac_func_enable,
1906                                                     false);
1907                 rtlhal->mac_func_enable = false;
1908         }
1909
1910         /* Reset MAC/BB/RF status if it is not powered off
1911          * before calling initialize Hw flow to prevent
1912          * from interface and MAC status mismatch.
1913          * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1914         if (rtlhal->mac_func_enable) {
1915                 _rtl8821ae_poweroff_adapter(hw);
1916                 rtlhal->mac_func_enable = false;
1917         }
1918
1919         rtstatus = _rtl8821ae_init_mac(hw);
1920         if (rtstatus != true) {
1921                 pr_err("Init MAC failed\n");
1922                 err = 1;
1923                 return err;
1924         }
1925
1926         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1927         tmp_u1b &= 0x7F;
1928         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1929
1930         err = rtl8821ae_download_fw(hw, false);
1931         if (err) {
1932                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1933                          "Failed to download FW. Init HW without FW now\n");
1934                 err = 1;
1935                 rtlhal->fw_ready = false;
1936                 return err;
1937         } else {
1938                 rtlhal->fw_ready = true;
1939         }
1940         ppsc->fw_current_inpsmode = false;
1941         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1942         rtlhal->fw_clk_change_in_progress = false;
1943         rtlhal->allow_sw_to_change_hwclc = false;
1944         rtlhal->last_hmeboxnum = 0;
1945
1946         /*SIC_Init(Adapter);
1947         if(rtlhal->AMPDUBurstMode)
1948                 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1949
1950         rtl8821ae_phy_mac_config(hw);
1951         /* because last function modify RCR, so we update
1952          * rcr var here, or TP will unstable for receive_config
1953          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1954          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1955         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1956         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1957         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1958         rtl8821ae_phy_bb_config(hw);
1959
1960         rtl8821ae_phy_rf_config(hw);
1961
1962         if (rtlpriv->phy.rf_type == RF_1T1R &&
1963                 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1964                 _rtl8812ae_bb8812_config_1t(hw);
1965
1966         _rtl8821ae_hw_configure(hw);
1967
1968         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1969
1970         /*set wireless mode*/
1971
1972         rtlhal->mac_func_enable = true;
1973
1974         rtl_cam_reset_all_entry(hw);
1975
1976         rtl8821ae_enable_hw_security_config(hw);
1977
1978         ppsc->rfpwr_state = ERFON;
1979
1980         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1981         _rtl8821ae_enable_aspm_back_door(hw);
1982         rtlpriv->intf_ops->enable_aspm(hw);
1983
1984         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1985             (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1986                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1987
1988         rtl8821ae_bt_hw_init(hw);
1989         rtlpriv->rtlhal.being_init_adapter = false;
1990
1991         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1992
1993         /* rtl8821ae_dm_check_txpower_tracking(hw); */
1994         /* rtl8821ae_phy_lc_calibrate(hw); */
1995         if (support_remote_wakeup)
1996                 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
1997
1998         /* Release Rx DMA*/
1999         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2000         if (tmp_u1b & BIT(2)) {
2001                 /* Release Rx DMA if needed*/
2002                 tmp_u1b &= ~BIT(2);
2003                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2004         }
2005
2006         /* Release Tx/Rx PCIE DMA if*/
2007         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2008
2009         rtl8821ae_dm_init(hw);
2010         rtl8821ae_macid_initialize_mediastatus(hw);
2011
2012         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2013         return err;
2014 }
2015
2016 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2017 {
2018         struct rtl_priv *rtlpriv = rtl_priv(hw);
2019         struct rtl_phy *rtlphy = &rtlpriv->phy;
2020         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2021         enum version_8821ae version = VERSION_UNKNOWN;
2022         u32 value32;
2023
2024         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2025         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2026                  "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2027
2028         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2029                 rtlphy->rf_type = RF_2T2R;
2030         else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2031                 rtlphy->rf_type = RF_1T1R;
2032
2033         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2034                  "RF_Type is %x!!\n", rtlphy->rf_type);
2035
2036         if (value32 & TRP_VAUX_EN) {
2037                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2038                         if (rtlphy->rf_type == RF_2T2R)
2039                                 version = VERSION_TEST_CHIP_2T2R_8812;
2040                         else
2041                                 version = VERSION_TEST_CHIP_1T1R_8812;
2042                 } else
2043                         version = VERSION_TEST_CHIP_8821;
2044         } else {
2045                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2046                         u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2047
2048                         if (rtlphy->rf_type == RF_2T2R)
2049                                 version =
2050                                         (enum version_8821ae)(CHIP_8812
2051                                         | NORMAL_CHIP |
2052                                         RF_TYPE_2T2R);
2053                         else
2054                                 version = (enum version_8821ae)(CHIP_8812
2055                                         | NORMAL_CHIP);
2056
2057                         version = (enum version_8821ae)(version | (rtl_id << 12));
2058                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2059                         u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2060
2061                         version = (enum version_8821ae)(CHIP_8821
2062                                 | NORMAL_CHIP | rtl_id);
2063                 }
2064         }
2065
2066         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2067                 /*WL_HWROF_EN.*/
2068                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2069                 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2070         }
2071
2072         switch (version) {
2073         case VERSION_TEST_CHIP_1T1R_8812:
2074                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2075                          "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2076                 break;
2077         case VERSION_TEST_CHIP_2T2R_8812:
2078                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2079                          "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2080                 break;
2081         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2082                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2083                          "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2084                 break;
2085         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2086                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2088                 break;
2089         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2090                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2092                 break;
2093         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2094                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2096                 break;
2097         case VERSION_TEST_CHIP_8821:
2098                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099                          "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2100                 break;
2101         case VERSION_NORMAL_TSMC_CHIP_8821:
2102                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2104                 break;
2105         case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2106                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2108                 break;
2109         default:
2110                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111                          "Chip Version ID: Unknown (0x%X)\n", version);
2112                 break;
2113         }
2114
2115         return version;
2116 }
2117
2118 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2119                                      enum nl80211_iftype type)
2120 {
2121         struct rtl_priv *rtlpriv = rtl_priv(hw);
2122         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2123         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2124         bt_msr &= 0xfc;
2125
2126         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2127         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2128                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2129
2130         if (type == NL80211_IFTYPE_UNSPECIFIED ||
2131             type == NL80211_IFTYPE_STATION) {
2132                 _rtl8821ae_stop_tx_beacon(hw);
2133                 _rtl8821ae_enable_bcn_sub_func(hw);
2134         } else if (type == NL80211_IFTYPE_ADHOC ||
2135                 type == NL80211_IFTYPE_AP) {
2136                 _rtl8821ae_resume_tx_beacon(hw);
2137                 _rtl8821ae_disable_bcn_sub_func(hw);
2138         } else {
2139                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2140                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2141                          type);
2142         }
2143
2144         switch (type) {
2145         case NL80211_IFTYPE_UNSPECIFIED:
2146                 bt_msr |= MSR_NOLINK;
2147                 ledaction = LED_CTL_LINK;
2148                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2149                          "Set Network type to NO LINK!\n");
2150                 break;
2151         case NL80211_IFTYPE_ADHOC:
2152                 bt_msr |= MSR_ADHOC;
2153                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2154                          "Set Network type to Ad Hoc!\n");
2155                 break;
2156         case NL80211_IFTYPE_STATION:
2157                 bt_msr |= MSR_INFRA;
2158                 ledaction = LED_CTL_LINK;
2159                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2160                          "Set Network type to STA!\n");
2161                 break;
2162         case NL80211_IFTYPE_AP:
2163                 bt_msr |= MSR_AP;
2164                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2165                          "Set Network type to AP!\n");
2166                 break;
2167         default:
2168                 pr_err("Network type %d not support!\n", type);
2169                 return 1;
2170         }
2171
2172         rtl_write_byte(rtlpriv, MSR, bt_msr);
2173         rtlpriv->cfg->ops->led_control(hw, ledaction);
2174         if ((bt_msr & MSR_MASK) == MSR_AP)
2175                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2176         else
2177                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2178
2179         return 0;
2180 }
2181
2182 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2183 {
2184         struct rtl_priv *rtlpriv = rtl_priv(hw);
2185         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2186         u32 reg_rcr = rtlpci->receive_config;
2187
2188         if (rtlpriv->psc.rfpwr_state != ERFON)
2189                 return;
2190
2191         if (check_bssid) {
2192                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2193                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2194                                               (u8 *)(&reg_rcr));
2195                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2196         } else if (!check_bssid) {
2197                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2198                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2199                 rtlpriv->cfg->ops->set_hw_reg(hw,
2200                         HW_VAR_RCR, (u8 *)(&reg_rcr));
2201         }
2202 }
2203
2204 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2205 {
2206         struct rtl_priv *rtlpriv = rtl_priv(hw);
2207
2208         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2209
2210         if (_rtl8821ae_set_media_status(hw, type))
2211                 return -EOPNOTSUPP;
2212
2213         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2214                 if (type != NL80211_IFTYPE_AP)
2215                         rtl8821ae_set_check_bssid(hw, true);
2216         } else {
2217                 rtl8821ae_set_check_bssid(hw, false);
2218         }
2219
2220         return 0;
2221 }
2222
2223 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2224 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2225 {
2226         struct rtl_priv *rtlpriv = rtl_priv(hw);
2227         rtl8821ae_dm_init_edca_turbo(hw);
2228         switch (aci) {
2229         case AC1_BK:
2230                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2231                 break;
2232         case AC0_BE:
2233                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2234                 break;
2235         case AC2_VI:
2236                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2237                 break;
2238         case AC3_VO:
2239                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2240                 break;
2241         default:
2242                 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci);
2243                 break;
2244         }
2245 }
2246
2247 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2248 {
2249         struct rtl_priv *rtlpriv = rtl_priv(hw);
2250         u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2251
2252         rtl_write_dword(rtlpriv, REG_HISR, tmp);
2253
2254         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2255         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2256
2257         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2258         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2259 }
2260
2261 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2262 {
2263         struct rtl_priv *rtlpriv = rtl_priv(hw);
2264         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2265
2266         if (rtlpci->int_clear)
2267                 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2268
2269         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2270         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2271         rtlpci->irq_enabled = true;
2272         /* there are some C2H CMDs have been sent before
2273         system interrupt is enabled, e.g., C2H, CPWM.
2274         *So we need to clear all C2H events that FW has
2275         notified, otherwise FW won't schedule any commands anymore.
2276         */
2277         /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2278         /*enable system interrupt*/
2279         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2280 }
2281
2282 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2283 {
2284         struct rtl_priv *rtlpriv = rtl_priv(hw);
2285         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2286
2287         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2288         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2289         rtlpci->irq_enabled = false;
2290         /*synchronize_irq(rtlpci->pdev->irq);*/
2291 }
2292
2293 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2294 {
2295         struct rtl_priv *rtlpriv = rtl_priv(hw);
2296         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2297         u16 cap_hdr;
2298         u8 cap_pointer;
2299         u8 cap_id = 0xff;
2300         u8 pmcs_reg;
2301         u8 cnt = 0;
2302
2303         /* Get the Capability pointer first,
2304          * the Capability Pointer is located at
2305          * offset 0x34 from the Function Header */
2306
2307         pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2308         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2309                  "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2310
2311         do {
2312                 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2313                 cap_id = cap_hdr & 0xFF;
2314
2315                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2316                          "in pci configuration, cap_pointer%x = %x\n",
2317                           cap_pointer, cap_id);
2318
2319                 if (cap_id == 0x01) {
2320                         break;
2321                 } else {
2322                         /* point to next Capability */
2323                         cap_pointer = (cap_hdr >> 8) & 0xFF;
2324                         /* 0: end of pci capability, 0xff: invalid value */
2325                         if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2326                                 cap_id = 0xff;
2327                                 break;
2328                         }
2329                 }
2330         } while (cnt++ < 200);
2331
2332         if (cap_id == 0x01) {
2333                 /* Get the PM CSR (Control/Status Register),
2334                  * The PME_Status is located at PM Capatibility offset 5, bit 7
2335                  */
2336                 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2337
2338                 if (pmcs_reg & BIT(7)) {
2339                         /* PME event occured, clear the PM_Status by write 1 */
2340                         pmcs_reg = pmcs_reg | BIT(7);
2341
2342                         pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2343                                               pmcs_reg);
2344                         /* Read it back to check */
2345                         pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2346                                              &pmcs_reg);
2347                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2348                                  "Clear PME status 0x%2x to 0x%2x\n",
2349                                   cap_pointer + 5, pmcs_reg);
2350                 } else {
2351                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2352                                  "PME status(0x%2x) = 0x%2x\n",
2353                                   cap_pointer + 5, pmcs_reg);
2354                 }
2355         } else {
2356                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2357                          "Cannot find PME Capability\n");
2358         }
2359 }
2360
2361 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2362 {
2363         struct rtl_priv *rtlpriv = rtl_priv(hw);
2364         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2365         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2366         struct rtl_mac *mac = rtl_mac(rtlpriv);
2367         enum nl80211_iftype opmode;
2368         bool support_remote_wakeup;
2369         u8 tmp;
2370         u32 count = 0;
2371
2372         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2373                                       (u8 *)(&support_remote_wakeup));
2374
2375         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2376
2377         if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2378             || !rtlhal->enter_pnp_sleep) {
2379                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2380                 mac->link_state = MAC80211_NOLINK;
2381                 opmode = NL80211_IFTYPE_UNSPECIFIED;
2382                 _rtl8821ae_set_media_status(hw, opmode);
2383                 _rtl8821ae_poweroff_adapter(hw);
2384         } else {
2385                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2386                 /* 3 <1> Prepare for configuring wowlan related infomations */
2387                 /* Clear Fw WoWLAN event. */
2388                 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2389
2390 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2391                 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2392 #endif
2393                 /* Dynamically adjust Tx packet boundary
2394                  * for download reserved page packet.
2395                  * reserve 30 pages for rsvd page */
2396                 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2397                         rtlhal->re_init_llt_table = true;
2398
2399                 /* 3 <2> Set Fw releted H2C cmd. */
2400
2401                 /* Set WoWLAN related security information. */
2402                 rtl8821ae_set_fw_global_info_cmd(hw);
2403
2404                 _rtl8821ae_download_rsvd_page(hw, true);
2405
2406                 /* Just enable AOAC related functions when we connect to AP. */
2407                 printk("mac->link_state = %d\n", mac->link_state);
2408                 if (mac->link_state >= MAC80211_LINKED &&
2409                     mac->opmode == NL80211_IFTYPE_STATION) {
2410                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2411                         rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2412                                                               RT_MEDIA_CONNECT);
2413
2414                         rtl8821ae_set_fw_wowlan_mode(hw, true);
2415                         /* Enable Fw Keep alive mechanism. */
2416                         rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2417
2418                         /* Enable disconnect decision control. */
2419                         rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2420                 }
2421
2422                 /* 3 <3> Hw Configutations */
2423
2424                 /* Wait untill Rx DMA Finished before host sleep.
2425                  * FW Pause Rx DMA may happens when received packet doing dma.
2426                  */
2427                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2428
2429                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2430                 count = 0;
2431                 while (!(tmp & BIT(1)) && (count++ < 100)) {
2432                         udelay(10);
2433                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2434                 }
2435                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2436                          "Wait Rx DMA Finished before host sleep. count=%d\n",
2437                           count);
2438
2439                 /* reset trx ring */
2440                 rtlpriv->intf_ops->reset_trx_ring(hw);
2441
2442                 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2443
2444                 _rtl8821ae_clear_pci_pme_status(hw);
2445                 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2446                 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2447                 /* prevent 8051 to be reset by PERST */
2448                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2449                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2450         }
2451
2452         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2453             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2454                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2455         /* For wowlan+LPS+32k. */
2456         if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2457                 /* Set the WoWLAN related function control enable.
2458                  * It should be the last H2C cmd in the WoWLAN flow. */
2459                 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2460
2461                 /* Stop Pcie Interface Tx DMA. */
2462                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2463                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2464
2465                 /* Wait for TxDMA idle. */
2466                 count = 0;
2467                 do {
2468                         tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2469                         udelay(10);
2470                         count++;
2471                 } while ((tmp != 0) && (count < 100));
2472                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2473                          "Wait Tx DMA Finished before host sleep. count=%d\n",
2474                           count);
2475
2476                 if (rtlhal->hw_rof_enable) {
2477                         printk("hw_rof_enable\n");
2478                         tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2479                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2480                 }
2481         }
2482         /* after power off we should do iqk again */
2483         rtlpriv->phy.iqk_initialized = false;
2484 }
2485
2486 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2487                                     struct rtl_int *intvec)
2488 {
2489         struct rtl_priv *rtlpriv = rtl_priv(hw);
2490         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2491
2492         intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2493         rtl_write_dword(rtlpriv, ISR, intvec->inta);
2494
2495         intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2496         rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
2497 }
2498
2499 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2500 {
2501         struct rtl_priv *rtlpriv = rtl_priv(hw);
2502         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2503         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2504         u16 bcn_interval, atim_window;
2505
2506         bcn_interval = mac->beacon_interval;
2507         atim_window = 2;        /*FIX MERGE */
2508         rtl8821ae_disable_interrupt(hw);
2509         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2510         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2511         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2512         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2513         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2514         rtl_write_byte(rtlpriv, 0x606, 0x30);
2515         rtlpci->reg_bcn_ctrl_val |= BIT(3);
2516         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2517         rtl8821ae_enable_interrupt(hw);
2518 }
2519
2520 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2521 {
2522         struct rtl_priv *rtlpriv = rtl_priv(hw);
2523         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2524         u16 bcn_interval = mac->beacon_interval;
2525
2526         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2527                  "beacon_interval:%d\n", bcn_interval);
2528         rtl8821ae_disable_interrupt(hw);
2529         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2530         rtl8821ae_enable_interrupt(hw);
2531 }
2532
2533 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2534                                    u32 add_msr, u32 rm_msr)
2535 {
2536         struct rtl_priv *rtlpriv = rtl_priv(hw);
2537         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2538
2539         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2540                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2541
2542         if (add_msr)
2543                 rtlpci->irq_mask[0] |= add_msr;
2544         if (rm_msr)
2545                 rtlpci->irq_mask[0] &= (~rm_msr);
2546         rtl8821ae_disable_interrupt(hw);
2547         rtl8821ae_enable_interrupt(hw);
2548 }
2549
2550 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2551 {
2552         u8 group = 0;
2553
2554         if (chnl <= 14) {
2555                 if (1 <= chnl && chnl <= 2)
2556                         group = 0;
2557         else if (3 <= chnl && chnl <= 5)
2558                         group = 1;
2559         else if (6 <= chnl && chnl <= 8)
2560                         group = 2;
2561         else if (9 <= chnl && chnl <= 11)
2562                         group = 3;
2563         else /*if (12 <= chnl && chnl <= 14)*/
2564                         group = 4;
2565         } else {
2566                 if (36 <= chnl && chnl <= 42)
2567                         group = 0;
2568         else if (44 <= chnl && chnl <= 48)
2569                         group = 1;
2570         else if (50 <= chnl && chnl <= 58)
2571                         group = 2;
2572         else if (60 <= chnl && chnl <= 64)
2573                         group = 3;
2574         else if (100 <= chnl && chnl <= 106)
2575                         group = 4;
2576         else if (108 <= chnl && chnl <= 114)
2577                         group = 5;
2578         else if (116 <= chnl && chnl <= 122)
2579                         group = 6;
2580         else if (124 <= chnl && chnl <= 130)
2581                         group = 7;
2582         else if (132 <= chnl && chnl <= 138)
2583                         group = 8;
2584         else if (140 <= chnl && chnl <= 144)
2585                         group = 9;
2586         else if (149 <= chnl && chnl <= 155)
2587                         group = 10;
2588         else if (157 <= chnl && chnl <= 161)
2589                         group = 11;
2590         else if (165 <= chnl && chnl <= 171)
2591                         group = 12;
2592         else if (173 <= chnl && chnl <= 177)
2593                         group = 13;
2594         else
2595                 WARN_ONCE(true,
2596                           "rtl8821ae: 5G, Channel %d in Group not found\n",
2597                           chnl);
2598         }
2599         return group;
2600 }
2601
2602 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2603         struct txpower_info_2g *pwrinfo24g,
2604         struct txpower_info_5g *pwrinfo5g,
2605         bool autoload_fail,
2606         u8 *hwinfo)
2607 {
2608         struct rtl_priv *rtlpriv = rtl_priv(hw);
2609         u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2610
2611         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2612                  "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2613                  (eeAddr+1), hwinfo[eeAddr+1]);
2614         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2615                 autoload_fail = true;
2616
2617         if (autoload_fail) {
2618                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2619                          "auto load fail : Use Default value!\n");
2620                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2621                         /*2.4G default value*/
2622                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2623                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
2624                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2625                         }
2626                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2627                                 if (TxCount == 0) {
2628                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2629                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2630                                 } else {
2631                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2632                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2633                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2634                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2635                                 }
2636                         }
2637                         /*5G default value*/
2638                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2639                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2640
2641                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2642                                 if (TxCount == 0) {
2643                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2644                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2645                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2646                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2647                                 } else {
2648                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2649                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2650                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2651                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2652                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2653                                 }
2654                         }
2655                 }
2656                 return;
2657         }
2658
2659         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2660
2661         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2662                 /*2.4G default value*/
2663                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2664                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2665                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2666                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2667                 }
2668                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2669                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2670                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2671                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2672                 }
2673                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2674                         if (TxCount == 0) {
2675                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2676                                 /*bit sign number to 8 bit sign number*/
2677                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2678                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2679                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2680                                 /*bit sign number to 8 bit sign number*/
2681                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2682                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2683                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2684
2685                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2686                                 eeAddr++;
2687                         } else {
2688                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2689                                 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2690                                         pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2691
2692                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2693                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2694                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2695
2696                                 eeAddr++;
2697
2698                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2699                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2700                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2701
2702                                 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2703                                 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2704                                         pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2705
2706                                 eeAddr++;
2707                         }
2708                 }
2709
2710                 /*5G default value*/
2711                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2712                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2713                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2714                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2715                 }
2716
2717                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2718                         if (TxCount == 0) {
2719                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2720
2721                                 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2722                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2723                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2724
2725                                 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2726                                 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2727                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2728
2729                                 eeAddr++;
2730                         } else {
2731                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2732                                 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2733                                         pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2734
2735                                 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2736                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2737                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2738
2739                                 eeAddr++;
2740                         }
2741                 }
2742
2743                 pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2744                 pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2745
2746                 eeAddr++;
2747
2748                 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2749
2750                 eeAddr++;
2751
2752                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2753                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2754                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2755                 }
2756                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2757                         pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2758                         /* 4bit sign number to 8 bit sign number */
2759                         if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2760                                 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2761                         /* 4bit sign number to 8 bit sign number */
2762                         pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2763                         if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2764                                 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2765
2766                         eeAddr++;
2767                 }
2768         }
2769 }
2770 #if 0
2771 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2772                                                  bool autoload_fail,
2773                                                  u8 *hwinfo)
2774 {
2775         struct rtl_priv *rtlpriv = rtl_priv(hw);
2776         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2777         struct txpower_info_2g pwrinfo24g;
2778         struct txpower_info_5g pwrinfo5g;
2779         u8 rf_path, index;
2780         u8 i;
2781
2782         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2783                                         &pwrinfo5g, autoload_fail, hwinfo);
2784
2785         for (rf_path = 0; rf_path < 2; rf_path++) {
2786                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2787                         index = _rtl8821ae_get_chnl_group(i + 1);
2788
2789                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2790                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2791                                         pwrinfo24g.index_cck_base[rf_path][5];
2792                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2793                                         pwrinfo24g.index_bw40_base[rf_path][index];
2794                         } else {
2795                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2796                                         pwrinfo24g.index_cck_base[rf_path][index];
2797                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2798                                         pwrinfo24g.index_bw40_base[rf_path][index];
2799                         }
2800                 }
2801
2802                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2803                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2804                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2805                                         pwrinfo5g.index_bw40_base[rf_path][index];
2806                 }
2807                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2808                         u8 upper, lower;
2809                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2810                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2811                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2812
2813                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2814                 }
2815                 for (i = 0; i < MAX_TX_COUNT; i++) {
2816                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2817                                 pwrinfo24g.cck_diff[rf_path][i];
2818                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2819                                 pwrinfo24g.ofdm_diff[rf_path][i];
2820                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2821                                 pwrinfo24g.bw20_diff[rf_path][i];
2822                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2823                                 pwrinfo24g.bw40_diff[rf_path][i];
2824
2825                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2826                                 pwrinfo5g.ofdm_diff[rf_path][i];
2827                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2828                                 pwrinfo5g.bw20_diff[rf_path][i];
2829                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2830                                 pwrinfo5g.bw40_diff[rf_path][i];
2831                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2832                                 pwrinfo5g.bw80_diff[rf_path][i];
2833                 }
2834         }
2835
2836         if (!autoload_fail) {
2837                 rtlefuse->eeprom_regulatory =
2838                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2839                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2840                         rtlefuse->eeprom_regulatory = 0;
2841         } else {
2842                 rtlefuse->eeprom_regulatory = 0;
2843         }
2844
2845         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2846         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2847 }
2848 #endif
2849 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2850                                                  bool autoload_fail,
2851                                                  u8 *hwinfo)
2852 {
2853         struct rtl_priv *rtlpriv = rtl_priv(hw);
2854         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2855         struct txpower_info_2g pwrinfo24g;
2856         struct txpower_info_5g pwrinfo5g;
2857         u8 rf_path, index;
2858         u8 i;
2859
2860         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2861                 &pwrinfo5g, autoload_fail, hwinfo);
2862
2863         for (rf_path = 0; rf_path < 2; rf_path++) {
2864                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2865                         index = _rtl8821ae_get_chnl_group(i + 1);
2866
2867                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2868                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2869                                         pwrinfo24g.index_cck_base[rf_path][5];
2870                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2871                                         pwrinfo24g.index_bw40_base[rf_path][index];
2872                         } else {
2873                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2874                                         pwrinfo24g.index_cck_base[rf_path][index];
2875                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2876                                         pwrinfo24g.index_bw40_base[rf_path][index];
2877                         }
2878                 }
2879
2880                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2881                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2882                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2883                                 pwrinfo5g.index_bw40_base[rf_path][index];
2884                 }
2885                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2886                         u8 upper, lower;
2887                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2888                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2889                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2890
2891                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2892                 }
2893                 for (i = 0; i < MAX_TX_COUNT; i++) {
2894                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2895                                 pwrinfo24g.cck_diff[rf_path][i];
2896                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2897                                 pwrinfo24g.ofdm_diff[rf_path][i];
2898                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2899                                 pwrinfo24g.bw20_diff[rf_path][i];
2900                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2901                                 pwrinfo24g.bw40_diff[rf_path][i];
2902
2903                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2904                                 pwrinfo5g.ofdm_diff[rf_path][i];
2905                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2906                                 pwrinfo5g.bw20_diff[rf_path][i];
2907                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2908                                 pwrinfo5g.bw40_diff[rf_path][i];
2909                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2910                                 pwrinfo5g.bw80_diff[rf_path][i];
2911                 }
2912         }
2913         /*bit0~2*/
2914         if (!autoload_fail) {
2915                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2916                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2917                         rtlefuse->eeprom_regulatory = 0;
2918         } else {
2919                 rtlefuse->eeprom_regulatory = 0;
2920         }
2921
2922         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2923         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2924 }
2925
2926 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2927                                     bool autoload_fail)
2928 {
2929         struct rtl_priv *rtlpriv = rtl_priv(hw);
2930         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2931
2932         if (!autoload_fail) {
2933                 rtlhal->pa_type_2g = hwinfo[0xBC];
2934                 rtlhal->lna_type_2g = hwinfo[0xBD];
2935                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2936                         rtlhal->pa_type_2g = 0;
2937                         rtlhal->lna_type_2g = 0;
2938                 }
2939                 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2940                                           (rtlhal->pa_type_2g & BIT(4))) ?
2941                                          1 : 0;
2942                 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2943                                            (rtlhal->lna_type_2g & BIT(3))) ?
2944                                           1 : 0;
2945
2946                 rtlhal->pa_type_5g = hwinfo[0xBC];
2947                 rtlhal->lna_type_5g = hwinfo[0xBF];
2948                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2949                         rtlhal->pa_type_5g = 0;
2950                         rtlhal->lna_type_5g = 0;
2951                 }
2952                 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2953                                           (rtlhal->pa_type_5g & BIT(0))) ?
2954                                          1 : 0;
2955                 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2956                                            (rtlhal->lna_type_5g & BIT(3))) ?
2957                                           1 : 0;
2958         } else {
2959                 rtlhal->external_pa_2g  = 0;
2960                 rtlhal->external_lna_2g = 0;
2961                 rtlhal->external_pa_5g  = 0;
2962                 rtlhal->external_lna_5g = 0;
2963         }
2964 }
2965
2966 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
2967                                            bool autoload_fail)
2968 {
2969         struct rtl_priv *rtlpriv = rtl_priv(hw);
2970         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2971
2972         u8 ext_type_pa_2g_a  = (hwinfo[0xBD] & BIT(2))      >> 2; /* 0xBD[2] */
2973         u8 ext_type_pa_2g_b  = (hwinfo[0xBD] & BIT(6))      >> 6; /* 0xBD[6] */
2974         u8 ext_type_pa_5g_a  = (hwinfo[0xBF] & BIT(2))      >> 2; /* 0xBF[2] */
2975         u8 ext_type_pa_5g_b  = (hwinfo[0xBF] & BIT(6))      >> 6; /* 0xBF[6] */
2976         /* 0xBD[1:0] */
2977         u8 ext_type_lna_2g_a = (hwinfo[0xBD] & (BIT(1) | BIT(0))) >> 0;
2978         /* 0xBD[5:4] */
2979         u8 ext_type_lna_2g_b = (hwinfo[0xBD] & (BIT(5) | BIT(4))) >> 4;
2980         /* 0xBF[1:0] */
2981         u8 ext_type_lna_5g_a = (hwinfo[0xBF] & (BIT(1) | BIT(0))) >> 0;
2982         /* 0xBF[5:4] */
2983         u8 ext_type_lna_5g_b = (hwinfo[0xBF] & (BIT(5) | BIT(4))) >> 4;
2984
2985         _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
2986
2987         /* [2.4G] Path A and B are both extPA */
2988         if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
2989                 rtlhal->type_gpa  = ext_type_pa_2g_b  << 2 | ext_type_pa_2g_a;
2990
2991         /* [5G] Path A and B are both extPA */
2992         if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
2993                 rtlhal->type_apa  = ext_type_pa_5g_b  << 2 | ext_type_pa_5g_a;
2994
2995         /* [2.4G] Path A and B are both extLNA */
2996         if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2997                 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
2998
2999         /* [5G] Path A and B are both extLNA */
3000         if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
3001                 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
3002 }
3003
3004 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
3005                                     bool autoload_fail)
3006 {
3007         struct rtl_priv *rtlpriv = rtl_priv(hw);
3008         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3009
3010         if (!autoload_fail) {
3011                 rtlhal->pa_type_2g = hwinfo[0xBC];
3012                 rtlhal->lna_type_2g = hwinfo[0xBD];
3013                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
3014                         rtlhal->pa_type_2g = 0;
3015                         rtlhal->lna_type_2g = 0;
3016                 }
3017                 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
3018                 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3019
3020                 rtlhal->pa_type_5g = hwinfo[0xBC];
3021                 rtlhal->lna_type_5g = hwinfo[0xBF];
3022                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3023                         rtlhal->pa_type_5g = 0;
3024                         rtlhal->lna_type_5g = 0;
3025                 }
3026                 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3027                 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3028         } else {
3029                 rtlhal->external_pa_2g  = 0;
3030                 rtlhal->external_lna_2g = 0;
3031                 rtlhal->external_pa_5g  = 0;
3032                 rtlhal->external_lna_5g = 0;
3033         }
3034 }
3035
3036 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3037                               bool autoload_fail)
3038 {
3039         struct rtl_priv *rtlpriv = rtl_priv(hw);
3040         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3041
3042         if (!autoload_fail) {
3043                 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3044                         if (rtlhal->external_lna_5g) {
3045                                 if (rtlhal->external_pa_5g) {
3046                                         if (rtlhal->external_lna_2g &&
3047                                             rtlhal->external_pa_2g)
3048                                                 rtlhal->rfe_type = 3;
3049                                         else
3050                                                 rtlhal->rfe_type = 0;
3051                                 } else {
3052                                         rtlhal->rfe_type = 2;
3053                                 }
3054                         } else {
3055                                 rtlhal->rfe_type = 4;
3056                         }
3057                 } else {
3058                         rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3059
3060                         if (rtlhal->rfe_type == 4 &&
3061                             (rtlhal->external_pa_5g ||
3062                              rtlhal->external_pa_2g ||
3063                              rtlhal->external_lna_5g ||
3064                              rtlhal->external_lna_2g)) {
3065                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3066                                         rtlhal->rfe_type = 2;
3067                         }
3068                 }
3069         } else {
3070                 rtlhal->rfe_type = 0x04;
3071         }
3072
3073         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3074                  "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3075 }
3076
3077 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3078                                               bool auto_load_fail, u8 *hwinfo)
3079 {
3080         struct rtl_priv *rtlpriv = rtl_priv(hw);
3081         u8 value;
3082
3083         if (!auto_load_fail) {
3084                 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3085                 if (((value & 0xe0) >> 5) == 0x1)
3086                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3087                 else
3088                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3089                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3090
3091                 value = hwinfo[EEPROM_RF_BT_SETTING];
3092                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3093         } else {
3094                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3095                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3096                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3097         }
3098         /*move BT_InitHalVars() to init_sw_vars*/
3099 }
3100
3101 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3102                                               bool auto_load_fail, u8 *hwinfo)
3103 {
3104         struct rtl_priv *rtlpriv = rtl_priv(hw);
3105         u8 value;
3106         u32 tmpu_32;
3107
3108         if (!auto_load_fail) {
3109                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3110                 if (tmpu_32 & BIT(18))
3111                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3112                 else
3113                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3114                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3115
3116                 value = hwinfo[EEPROM_RF_BT_SETTING];
3117                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3118         } else {
3119                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3120                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3121                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3122         }
3123         /*move BT_InitHalVars() to init_sw_vars*/
3124 }
3125
3126 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3127 {
3128         struct rtl_priv *rtlpriv = rtl_priv(hw);
3129         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3130         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3131         int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3132                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3133                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3134                         COUNTRY_CODE_WORLD_WIDE_13};
3135         u8 *hwinfo;
3136
3137         if (b_pseudo_test) {
3138                 ;/* need add */
3139         }
3140
3141         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3142         if (!hwinfo)
3143                 return;
3144
3145         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3146                 goto exit;
3147
3148         _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3149                                                hwinfo);
3150
3151         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3152                 _rtl8812ae_read_amplifier_type(hw, hwinfo,
3153                                                rtlefuse->autoload_failflag);
3154                 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3155                                 rtlefuse->autoload_failflag, hwinfo);
3156         } else {
3157                 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3158                 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3159                                 rtlefuse->autoload_failflag, hwinfo);
3160         }
3161
3162         _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3163         /*board type*/
3164         rtlefuse->board_type = ODM_BOARD_DEFAULT;
3165         if (rtlhal->external_lna_2g != 0)
3166                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3167         if (rtlhal->external_lna_5g != 0)
3168                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3169         if (rtlhal->external_pa_2g != 0)
3170                 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3171         if (rtlhal->external_pa_5g != 0)
3172                 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3173
3174         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3175                 rtlefuse->board_type |= ODM_BOARD_BT;
3176
3177         rtlhal->board_type = rtlefuse->board_type;
3178         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3179                  "board_type = 0x%x\n", rtlefuse->board_type);
3180
3181         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3182         if (rtlefuse->eeprom_channelplan == 0xff)
3183                 rtlefuse->eeprom_channelplan = 0x7F;
3184
3185         /* set channel plan from efuse */
3186         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3187
3188         /*parse xtal*/
3189         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3190         if (rtlefuse->crystalcap == 0xFF)
3191                 rtlefuse->crystalcap = 0x20;
3192
3193         rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3194         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3195             rtlefuse->autoload_failflag) {
3196                 rtlefuse->apk_thermalmeterignore = true;
3197                 rtlefuse->eeprom_thermalmeter = 0xff;
3198         }
3199
3200         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3201         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3202                  "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3203
3204         if (!rtlefuse->autoload_failflag) {
3205                 rtlefuse->antenna_div_cfg =
3206                   (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3207                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3208                         rtlefuse->antenna_div_cfg = 0;
3209
3210                 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3211                     rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3212                         rtlefuse->antenna_div_cfg = 0;
3213
3214                 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3215                 if (rtlefuse->antenna_div_type == 0xff)
3216                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3217         } else {
3218                 rtlefuse->antenna_div_cfg = 0;
3219                 rtlefuse->antenna_div_type = 0;
3220         }
3221
3222         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3223                 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3224                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3225
3226         rtlpriv->ledctl.led_opendrain = true;
3227
3228         if (rtlhal->oem_id == RT_CID_DEFAULT) {
3229                 switch (rtlefuse->eeprom_oemid) {
3230                 case RT_CID_DEFAULT:
3231                         break;
3232                 case EEPROM_CID_TOSHIBA:
3233                         rtlhal->oem_id = RT_CID_TOSHIBA;
3234                         break;
3235                 case EEPROM_CID_CCX:
3236                         rtlhal->oem_id = RT_CID_CCX;
3237                         break;
3238                 case EEPROM_CID_QMI:
3239                         rtlhal->oem_id = RT_CID_819X_QMI;
3240                         break;
3241                 case EEPROM_CID_WHQL:
3242                         break;
3243                 default:
3244                         break;
3245                 }
3246         }
3247 exit:
3248         kfree(hwinfo);
3249 }
3250
3251 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3252 {
3253         struct rtl_priv *rtlpriv = rtl_priv(hw);
3254         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3255         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3256
3257         rtlpriv->ledctl.led_opendrain = true;
3258         switch (rtlhal->oem_id) {
3259         case RT_CID_819X_HP:
3260                 rtlpriv->ledctl.led_opendrain = true;
3261                 break;
3262         case RT_CID_819X_LENOVO:
3263         case RT_CID_DEFAULT:
3264         case RT_CID_TOSHIBA:
3265         case RT_CID_CCX:
3266         case RT_CID_819X_ACER:
3267         case RT_CID_WHQL:
3268         default:
3269                 break;
3270         }
3271         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3272                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3273 }*/
3274
3275 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3276 {
3277         struct rtl_priv *rtlpriv = rtl_priv(hw);
3278         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3279         struct rtl_phy *rtlphy = &rtlpriv->phy;
3280         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3281         u8 tmp_u1b;
3282
3283         rtlhal->version = _rtl8821ae_read_chip_version(hw);
3284         if (get_rf_type(rtlphy) == RF_1T1R)
3285                 rtlpriv->dm.rfpath_rxenable[0] = true;
3286         else
3287                 rtlpriv->dm.rfpath_rxenable[0] =
3288                     rtlpriv->dm.rfpath_rxenable[1] = true;
3289         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3290                                                 rtlhal->version);
3291
3292         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3293         if (tmp_u1b & BIT(4)) {
3294                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3295                 rtlefuse->epromtype = EEPROM_93C46;
3296         } else {
3297                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3298                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3299         }
3300
3301         if (tmp_u1b & BIT(5)) {
3302                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3303                 rtlefuse->autoload_failflag = false;
3304                 _rtl8821ae_read_adapter_info(hw, false);
3305         } else {
3306                 pr_err("Autoload ERR!!\n");
3307         }
3308         /*hal_ReadRFType_8812A()*/
3309         /* _rtl8821ae_hal_customized_behavior(hw); */
3310 }
3311
3312 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3313                 struct ieee80211_sta *sta)
3314 {
3315         struct rtl_priv *rtlpriv = rtl_priv(hw);
3316         struct rtl_phy *rtlphy = &rtlpriv->phy;
3317         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3318         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3319         u32 ratr_value;
3320         u8 ratr_index = 0;
3321         u8 b_nmode = mac->ht_enable;
3322         u8 mimo_ps = IEEE80211_SMPS_OFF;
3323         u16 shortgi_rate;
3324         u32 tmp_ratr_value;
3325         u8 curtxbw_40mhz = mac->bw_40;
3326         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3327                                 1 : 0;
3328         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3329                                 1 : 0;
3330         enum wireless_mode wirelessmode = mac->mode;
3331
3332         if (rtlhal->current_bandtype == BAND_ON_5G)
3333                 ratr_value = sta->supp_rates[1] << 4;
3334         else
3335                 ratr_value = sta->supp_rates[0];
3336         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3337                 ratr_value = 0xfff;
3338         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3339                         sta->ht_cap.mcs.rx_mask[0] << 12);
3340         switch (wirelessmode) {
3341         case WIRELESS_MODE_B:
3342                 if (ratr_value & 0x0000000c)
3343                         ratr_value &= 0x0000000d;
3344                 else
3345                         ratr_value &= 0x0000000f;
3346                 break;
3347         case WIRELESS_MODE_G:
3348                 ratr_value &= 0x00000FF5;
3349                 break;
3350         case WIRELESS_MODE_N_24G:
3351         case WIRELESS_MODE_N_5G:
3352                 b_nmode = 1;
3353                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3354                         ratr_value &= 0x0007F005;
3355                 } else {
3356                         u32 ratr_mask;
3357
3358                         if (get_rf_type(rtlphy) == RF_1T2R ||
3359                             get_rf_type(rtlphy) == RF_1T1R)
3360                                 ratr_mask = 0x000ff005;
3361                         else
3362                                 ratr_mask = 0x0f0ff005;
3363
3364                         ratr_value &= ratr_mask;
3365                 }
3366                 break;
3367         default:
3368                 if (rtlphy->rf_type == RF_1T2R)
3369                         ratr_value &= 0x000ff0ff;
3370                 else
3371                         ratr_value &= 0x0f0ff0ff;
3372
3373                 break;
3374         }
3375
3376         if ((rtlpriv->btcoexist.bt_coexistence) &&
3377              (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3378              (rtlpriv->btcoexist.bt_cur_state) &&
3379              (rtlpriv->btcoexist.bt_ant_isolation) &&
3380              ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3381              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3382                 ratr_value &= 0x0fffcfc0;
3383         else
3384                 ratr_value &= 0x0FFFFFFF;
3385
3386         if (b_nmode && ((curtxbw_40mhz &&
3387                          b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3388                                                  b_curshortgi_20mhz))) {
3389                 ratr_value |= 0x10000000;
3390                 tmp_ratr_value = (ratr_value >> 12);
3391
3392                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3393                         if ((1 << shortgi_rate) & tmp_ratr_value)
3394                                 break;
3395                 }
3396
3397                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3398                     (shortgi_rate << 4) | (shortgi_rate);
3399         }
3400
3401         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3402
3403         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3404                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3405 }
3406
3407 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3408 {
3409         u8 i, j, tmp_rate;
3410         u32 rate_bitmap = 0;
3411
3412         for (i = j = 0; i < 4; i += 2, j += 10) {
3413                 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3414
3415                 switch (tmp_rate) {
3416                 case 2:
3417                         rate_bitmap = rate_bitmap | (0x03ff << j);
3418                         break;
3419                 case 1:
3420                         rate_bitmap = rate_bitmap | (0x01ff << j);
3421                         break;
3422                 case 0:
3423                         rate_bitmap = rate_bitmap | (0x00ff << j);
3424                         break;
3425                 default:
3426                         break;
3427                 }
3428         }
3429
3430         return rate_bitmap;
3431 }
3432
3433 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3434                                              enum wireless_mode wirelessmode,
3435                                              u32 ratr_bitmap)
3436 {
3437         struct rtl_priv *rtlpriv = rtl_priv(hw);
3438         struct rtl_phy *rtlphy = &rtlpriv->phy;
3439         u32 ret_bitmap = ratr_bitmap;
3440
3441         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3442                 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3443                 ret_bitmap = ratr_bitmap;
3444         else if (wirelessmode == WIRELESS_MODE_AC_5G
3445                 || wirelessmode == WIRELESS_MODE_AC_24G) {
3446                 if (rtlphy->rf_type == RF_1T1R)
3447                         ret_bitmap = ratr_bitmap & (~BIT21);
3448                 else
3449                         ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3450         }
3451
3452         return ret_bitmap;
3453 }
3454
3455 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3456                         u32 ratr_bitmap)
3457 {
3458         u8 ret = 0;
3459         if (wirelessmode < WIRELESS_MODE_N_24G)
3460                 ret =  0;
3461         else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3462                 if (ratr_bitmap & 0xfff00000)   /* Mix , 2SS */
3463                         ret = 3;
3464                 else                                    /* Mix, 1SS */
3465                         ret = 2;
3466         } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3467                         ret = 1;
3468         } /* VHT */
3469
3470         return ret << 4;
3471 }
3472
3473 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3474                              u8 mac_id, struct rtl_sta_info *sta_entry,
3475                              enum wireless_mode wirelessmode)
3476 {
3477         u8 b_ldpc = 0;
3478         /*not support ldpc, do not open*/
3479         return b_ldpc << 2;
3480 }
3481
3482 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3483                           enum wireless_mode wirelessmode,
3484                           u32 ratr_bitmap)
3485 {
3486         struct rtl_priv *rtlpriv = rtl_priv(hw);
3487         struct rtl_phy *rtlphy = &rtlpriv->phy;
3488         u8 rf_type = RF_1T1R;
3489
3490         if (rtlphy->rf_type == RF_1T1R)
3491                 rf_type = RF_1T1R;
3492         else if (wirelessmode == WIRELESS_MODE_AC_5G
3493                 || wirelessmode == WIRELESS_MODE_AC_24G
3494                 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3495                 if (ratr_bitmap & 0xffc00000)
3496                         rf_type = RF_2T2R;
3497         } else if (wirelessmode == WIRELESS_MODE_N_5G
3498                 || wirelessmode == WIRELESS_MODE_N_24G) {
3499                 if (ratr_bitmap & 0xfff00000)
3500                         rf_type = RF_2T2R;
3501         }
3502
3503         return rf_type;
3504 }
3505
3506 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3507                               u8 mac_id)
3508 {
3509         bool b_short_gi = false;
3510         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3511                                 1 : 0;
3512         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3513                                 1 : 0;
3514         u8 b_curshortgi_80mhz = 0;
3515         b_curshortgi_80mhz = (sta->vht_cap.cap &
3516                               IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3517
3518         if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3519                         b_short_gi = false;
3520
3521         if (b_curshortgi_40mhz || b_curshortgi_80mhz
3522                 || b_curshortgi_20mhz)
3523                 b_short_gi = true;
3524
3525         return b_short_gi;
3526 }
3527
3528 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3529                 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3530 {
3531         struct rtl_priv *rtlpriv = rtl_priv(hw);
3532         struct rtl_phy *rtlphy = &rtlpriv->phy;
3533         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3534         struct rtl_sta_info *sta_entry = NULL;
3535         u32 ratr_bitmap;
3536         u8 ratr_index;
3537         enum wireless_mode wirelessmode = 0;
3538         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3539                                 ? 1 : 0;
3540         bool b_shortgi = false;
3541         u8 rate_mask[7];
3542         u8 macid = 0;
3543         u8 mimo_ps = IEEE80211_SMPS_OFF;
3544         u8 rf_type;
3545
3546         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3547         wirelessmode = sta_entry->wireless_mode;
3548
3549         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3550                  "wireless mode = 0x%x\n", wirelessmode);
3551         if (mac->opmode == NL80211_IFTYPE_STATION ||
3552                 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3553                 curtxbw_40mhz = mac->bw_40;
3554         } else if (mac->opmode == NL80211_IFTYPE_AP ||
3555                 mac->opmode == NL80211_IFTYPE_ADHOC)
3556                 macid = sta->aid + 1;
3557         if (wirelessmode == WIRELESS_MODE_N_5G ||
3558             wirelessmode == WIRELESS_MODE_AC_5G ||
3559             wirelessmode == WIRELESS_MODE_A)
3560                 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3561         else
3562                 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3563
3564         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3565                 ratr_bitmap = 0xfff;
3566
3567         if (wirelessmode == WIRELESS_MODE_N_24G
3568                 || wirelessmode == WIRELESS_MODE_N_5G)
3569                 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3570                                 sta->ht_cap.mcs.rx_mask[0] << 12);
3571         else if (wirelessmode == WIRELESS_MODE_AC_24G
3572                 || wirelessmode == WIRELESS_MODE_AC_5G
3573                 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3574                 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3575                                 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3576
3577         b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3578         rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3579
3580 /*mac id owner*/
3581         switch (wirelessmode) {
3582         case WIRELESS_MODE_B:
3583                 ratr_index = RATR_INX_WIRELESS_B;
3584                 if (ratr_bitmap & 0x0000000c)
3585                         ratr_bitmap &= 0x0000000d;
3586                 else
3587                         ratr_bitmap &= 0x0000000f;
3588                 break;
3589         case WIRELESS_MODE_G:
3590                 ratr_index = RATR_INX_WIRELESS_GB;
3591
3592                 if (rssi_level == 1)
3593                         ratr_bitmap &= 0x00000f00;
3594                 else if (rssi_level == 2)
3595                         ratr_bitmap &= 0x00000ff0;
3596                 else
3597                         ratr_bitmap &= 0x00000ff5;
3598                 break;
3599         case WIRELESS_MODE_A:
3600                 ratr_index = RATR_INX_WIRELESS_G;
3601                 ratr_bitmap &= 0x00000ff0;
3602                 break;
3603         case WIRELESS_MODE_N_24G:
3604         case WIRELESS_MODE_N_5G:
3605                 if (wirelessmode == WIRELESS_MODE_N_24G)
3606                         ratr_index = RATR_INX_WIRELESS_NGB;
3607                 else
3608                         ratr_index = RATR_INX_WIRELESS_NG;
3609
3610                 if (mimo_ps == IEEE80211_SMPS_STATIC
3611                         || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3612                         if (rssi_level == 1)
3613                                 ratr_bitmap &= 0x000f0000;
3614                         else if (rssi_level == 2)
3615                                 ratr_bitmap &= 0x000ff000;
3616                         else
3617                                 ratr_bitmap &= 0x000ff005;
3618                 } else {
3619                         if (rf_type == RF_1T1R) {
3620                                 if (curtxbw_40mhz) {
3621                                         if (rssi_level == 1)
3622                                                 ratr_bitmap &= 0x000f0000;
3623                                         else if (rssi_level == 2)
3624                                                 ratr_bitmap &= 0x000ff000;
3625                                         else
3626                                                 ratr_bitmap &= 0x000ff015;
3627                                 } else {
3628                                         if (rssi_level == 1)
3629                                                 ratr_bitmap &= 0x000f0000;
3630                                         else if (rssi_level == 2)
3631                                                 ratr_bitmap &= 0x000ff000;
3632                                         else
3633                                                 ratr_bitmap &= 0x000ff005;
3634                                 }
3635                         } else {
3636                                 if (curtxbw_40mhz) {
3637                                         if (rssi_level == 1)
3638                                                 ratr_bitmap &= 0x0fff0000;
3639                                         else if (rssi_level == 2)
3640                                                 ratr_bitmap &= 0x0ffff000;
3641                                         else
3642                                                 ratr_bitmap &= 0x0ffff015;
3643                                 } else {
3644                                         if (rssi_level == 1)
3645                                                 ratr_bitmap &= 0x0fff0000;
3646                                         else if (rssi_level == 2)
3647                                                 ratr_bitmap &= 0x0ffff000;
3648                                         else
3649                                                 ratr_bitmap &= 0x0ffff005;
3650                                 }
3651                         }
3652                 }
3653                 break;
3654
3655         case WIRELESS_MODE_AC_24G:
3656                 ratr_index = RATR_INX_WIRELESS_AC_24N;
3657                 if (rssi_level == 1)
3658                         ratr_bitmap &= 0xfc3f0000;
3659                 else if (rssi_level == 2)
3660                         ratr_bitmap &= 0xfffff000;
3661                 else
3662                         ratr_bitmap &= 0xffffffff;
3663                 break;
3664
3665         case WIRELESS_MODE_AC_5G:
3666                 ratr_index = RATR_INX_WIRELESS_AC_5N;
3667
3668                 if (rf_type == RF_1T1R) {
3669                         if (rssi_level == 1)    /*add by Gary for ac-series*/
3670                                 ratr_bitmap &= 0x003f8000;
3671                         else if (rssi_level == 2)
3672                                 ratr_bitmap &= 0x003ff000;
3673                         else
3674                                 ratr_bitmap &= 0x003ff010;
3675                 } else {
3676                         if (rssi_level == 1)
3677                                 ratr_bitmap &= 0xfe3f8000;
3678                         else if (rssi_level == 2)
3679                                 ratr_bitmap &= 0xfffff000;
3680                         else
3681                                 ratr_bitmap &= 0xfffff010;
3682                 }
3683                 break;
3684
3685         default:
3686                 ratr_index = RATR_INX_WIRELESS_NGB;
3687
3688                 if (rf_type == RF_1T2R)
3689                         ratr_bitmap &= 0x000ff0ff;
3690                 else
3691                         ratr_bitmap &= 0x0f8ff0ff;
3692                 break;
3693         }
3694
3695         ratr_index = rtl_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3696         sta_entry->ratr_index = ratr_index;
3697         ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3698                                                         ratr_bitmap);
3699
3700         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3701                  "ratr_bitmap :%x\n", ratr_bitmap);
3702
3703         /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3704                                        (ratr_index << 28)); */
3705
3706         rate_mask[0] = macid;
3707         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3708         rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3)
3709                            | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3710                            | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3711
3712         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3713         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3714         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3715         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3716
3717         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3718                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3719                  ratr_index, ratr_bitmap,
3720                  rate_mask[0], rate_mask[1],
3721                  rate_mask[2], rate_mask[3],
3722                  rate_mask[4], rate_mask[5],
3723                  rate_mask[6]);
3724         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3725         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3726 }
3727
3728 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3729                 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3730 {
3731         struct rtl_priv *rtlpriv = rtl_priv(hw);
3732         if (rtlpriv->dm.useramask)
3733                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
3734         else
3735                 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3736                            "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3737                 rtl8821ae_update_hal_rate_table(hw, sta);
3738 }
3739
3740 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3741 {
3742         struct rtl_priv *rtlpriv = rtl_priv(hw);
3743         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3744         u16 wireless_mode = mac->mode;
3745         u8 sifs_timer, r2t_sifs;
3746
3747         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3748                                       (u8 *)&mac->slot_time);
3749         if (wireless_mode == WIRELESS_MODE_G)
3750                 sifs_timer = 0x0a;
3751         else
3752                 sifs_timer = 0x0e;
3753         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3754
3755         r2t_sifs = 0xa;
3756
3757         if (wireless_mode == WIRELESS_MODE_AC_5G &&
3758             (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3759             (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3760                 if (mac->vendor == PEER_ATH)
3761                         r2t_sifs = 0x8;
3762                 else
3763                         r2t_sifs = 0xa;
3764         } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3765                 r2t_sifs = 0xa;
3766         }
3767
3768         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3769 }
3770
3771 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3772 {
3773         struct rtl_priv *rtlpriv = rtl_priv(hw);
3774         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3775         struct rtl_phy *rtlphy = &rtlpriv->phy;
3776         enum rf_pwrstate e_rfpowerstate_toset;
3777         u8 u1tmp = 0;
3778         bool b_actuallyset = false;
3779
3780         if (rtlpriv->rtlhal.being_init_adapter)
3781                 return false;
3782
3783         if (ppsc->swrf_processing)
3784                 return false;
3785
3786         spin_lock(&rtlpriv->locks.rf_ps_lock);
3787         if (ppsc->rfchange_inprogress) {
3788                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3789                 return false;
3790         } else {
3791                 ppsc->rfchange_inprogress = true;
3792                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3793         }
3794
3795         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3796                         rtl_read_byte(rtlpriv,
3797                                         REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3798
3799         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3800
3801         if (rtlphy->polarity_ctl)
3802                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3803         else
3804                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3805
3806         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3807                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3808                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
3809
3810                 e_rfpowerstate_toset = ERFON;
3811                 ppsc->hwradiooff = false;
3812                 b_actuallyset = true;
3813         } else if ((!ppsc->hwradiooff)
3814                    && (e_rfpowerstate_toset == ERFOFF)) {
3815                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3816                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3817
3818                 e_rfpowerstate_toset = ERFOFF;
3819                 ppsc->hwradiooff = true;
3820                 b_actuallyset = true;
3821         }
3822
3823         if (b_actuallyset) {
3824                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3825                 ppsc->rfchange_inprogress = false;
3826                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3827         } else {
3828                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3829                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3830
3831                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3832                 ppsc->rfchange_inprogress = false;
3833                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3834         }
3835
3836         *valid = 1;
3837         return !ppsc->hwradiooff;
3838 }
3839
3840 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3841                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3842                      bool is_wepkey, bool clear_all)
3843 {
3844         struct rtl_priv *rtlpriv = rtl_priv(hw);
3845         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3846         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3847         u8 *macaddr = p_macaddr;
3848         u32 entry_id = 0;
3849         bool is_pairwise = false;
3850
3851         static u8 cam_const_addr[4][6] = {
3852                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3853                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3854                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3855                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3856         };
3857         static u8 cam_const_broad[] = {
3858                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3859         };
3860
3861         if (clear_all) {
3862                 u8 idx = 0;
3863                 u8 cam_offset = 0;
3864                 u8 clear_number = 5;
3865
3866                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3867
3868                 for (idx = 0; idx < clear_number; idx++) {
3869                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3870                         rtl_cam_empty_entry(hw, cam_offset + idx);
3871
3872                         if (idx < 5) {
3873                                 memset(rtlpriv->sec.key_buf[idx], 0,
3874                                        MAX_KEY_LEN);
3875                                 rtlpriv->sec.key_len[idx] = 0;
3876                         }
3877                 }
3878         } else {
3879                 switch (enc_algo) {
3880                 case WEP40_ENCRYPTION:
3881                         enc_algo = CAM_WEP40;
3882                         break;
3883                 case WEP104_ENCRYPTION:
3884                         enc_algo = CAM_WEP104;
3885                         break;
3886                 case TKIP_ENCRYPTION:
3887                         enc_algo = CAM_TKIP;
3888                         break;
3889                 case AESCCMP_ENCRYPTION:
3890                         enc_algo = CAM_AES;
3891                         break;
3892                 default:
3893                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3894                                  "switch case %#x not processed\n", enc_algo);
3895                         enc_algo = CAM_TKIP;
3896                         break;
3897                 }
3898
3899                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3900                         macaddr = cam_const_addr[key_index];
3901                         entry_id = key_index;
3902                 } else {
3903                         if (is_group) {
3904                                 macaddr = cam_const_broad;
3905                                 entry_id = key_index;
3906                         } else {
3907                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3908                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3909                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3910                                                 pr_err("an not find free hwsecurity cam entry\n");
3911                                                 return;
3912                                         }
3913                                 } else {
3914                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3915                                 }
3916
3917                                 key_index = PAIRWISE_KEYIDX;
3918                                 is_pairwise = true;
3919                         }
3920                 }
3921
3922                 if (rtlpriv->sec.key_len[key_index] == 0) {
3923                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3924                                  "delete one entry, entry_id is %d\n",
3925                                  entry_id);
3926                         if (mac->opmode == NL80211_IFTYPE_AP)
3927                                 rtl_cam_del_entry(hw, p_macaddr);
3928                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3929                 } else {
3930                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3931                                  "add one entry\n");
3932                         if (is_pairwise) {
3933                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3934                                          "set Pairwise key\n");
3935
3936                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3937                                                       entry_id, enc_algo,
3938                                                       CAM_CONFIG_NO_USEDK,
3939                                                       rtlpriv->sec.key_buf[key_index]);
3940                         } else {
3941                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3942                                          "set group key\n");
3943
3944                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3945                                         rtl_cam_add_one_entry(hw,
3946                                                         rtlefuse->dev_addr,
3947                                                         PAIRWISE_KEYIDX,
3948                                                         CAM_PAIRWISE_KEY_POSITION,
3949                                                         enc_algo,
3950                                                         CAM_CONFIG_NO_USEDK,
3951                                                         rtlpriv->sec.key_buf
3952                                                         [entry_id]);
3953                                 }
3954
3955                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3956                                                 entry_id, enc_algo,
3957                                                 CAM_CONFIG_NO_USEDK,
3958                                                 rtlpriv->sec.key_buf[entry_id]);
3959                         }
3960                 }
3961         }
3962 }
3963
3964 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
3965 {
3966         struct rtl_priv *rtlpriv = rtl_priv(hw);
3967
3968         /* 0:Low, 1:High, 2:From Efuse. */
3969         rtlpriv->btcoexist.reg_bt_iso = 2;
3970         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3971         rtlpriv->btcoexist.reg_bt_sco = 3;
3972         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3973         rtlpriv->btcoexist.reg_bt_sco = 0;
3974 }
3975
3976 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
3977 {
3978         struct rtl_priv *rtlpriv = rtl_priv(hw);
3979
3980         if (rtlpriv->cfg->ops->get_btc_status())
3981                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3982 }
3983
3984 void rtl8821ae_suspend(struct ieee80211_hw *hw)
3985 {
3986 }
3987
3988 void rtl8821ae_resume(struct ieee80211_hw *hw)
3989 {
3990 }
3991
3992 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
3993 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3994         bool allow_all_da, bool write_into_reg)
3995 {
3996         struct rtl_priv *rtlpriv = rtl_priv(hw);
3997         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3998
3999         if (allow_all_da) /* Set BIT0 */
4000                 rtlpci->receive_config |= RCR_AAP;
4001         else /* Clear BIT0 */
4002                 rtlpci->receive_config &= ~RCR_AAP;
4003
4004         if (write_into_reg)
4005                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4006
4007         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4008                 "receive_config=0x%08X, write_into_reg=%d\n",
4009                 rtlpci->receive_config, write_into_reg);
4010 }
4011
4012 /* WKFMCAMAddAllEntry8812 */
4013 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4014                                   struct rtl_wow_pattern *rtl_pattern,
4015                                   u8 index)
4016 {
4017         struct rtl_priv *rtlpriv = rtl_priv(hw);
4018         u32 cam = 0;
4019         u8 addr = 0;
4020         u16 rxbuf_addr;
4021         u8 tmp, count = 0;
4022         u16 cam_start;
4023         u16 offset;
4024
4025         /* Count the WFCAM entry start offset. */
4026
4027         /* RX page size = 128 byte */
4028         offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4029         /* We should start from the boundry */
4030         cam_start = offset * 128;
4031
4032         /* Enable Rx packet buffer access. */
4033         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4034         for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4035                 /* Set Rx packet buffer offset.
4036                  * RxBufer pointer increases 1,
4037                  * we can access 8 bytes in Rx packet buffer.
4038                  * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4039                  * RxBufer addr = (CAM start offset +
4040                  *                 per entry offset of a WKFM CAM)/8
4041                  *      * index: The index of the wake up frame mask
4042                  *      * WKFMCAM_SIZE: the total size of one WKFM CAM
4043                  *      * per entry offset of a WKFM CAM: Addr*4 bytes
4044                  */
4045                 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4046                 /* Set R/W start offset */
4047                 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4048
4049                 if (addr == 0) {
4050                         cam = BIT(31) | rtl_pattern->crc;
4051
4052                         if (rtl_pattern->type == UNICAST_PATTERN)
4053                                 cam |= BIT(24);
4054                         else if (rtl_pattern->type == MULTICAST_PATTERN)
4055                                 cam |= BIT(25);
4056                         else if (rtl_pattern->type == BROADCAST_PATTERN)
4057                                 cam |= BIT(26);
4058
4059                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4060                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4061                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4062                                   REG_PKTBUF_DBG_DATA_L, cam);
4063
4064                         /* Write to Rx packet buffer. */
4065                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4066                 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4067                         cam = rtl_pattern->mask[addr - 2];
4068
4069                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4070                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4071                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4072                                   REG_PKTBUF_DBG_DATA_L, cam);
4073
4074                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4075                 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4076                         cam = rtl_pattern->mask[addr - 2];
4077
4078                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4079                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4080                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4081                                   REG_PKTBUF_DBG_DATA_H, cam);
4082
4083                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4084                 }
4085
4086                 count = 0;
4087                 do {
4088                         tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4089                         udelay(2);
4090                         count++;
4091                 } while (tmp && count < 100);
4092
4093                 WARN_ONCE((count >= 100),
4094                           "rtl8821ae: Write wake up frame mask FAIL %d value!\n",
4095                           tmp);
4096         }
4097         /* Disable Rx packet buffer access. */
4098         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4099                        DISABLE_TRXPKT_BUF_ACCESS);
4100 }