1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
40 #include "../pwrseqcmd.h"
42 #include "../btcoexist/rtl_btc.h"
46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
54 while (skb_queue_len(&ring->queue)) {
55 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
56 struct sk_buff *skb = __skb_dequeue(&ring->queue);
58 pci_unmap_single(rtlpci->pdev,
59 rtlpriv->cfg->ops->get_desc(
60 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
61 skb->len, PCI_DMA_TODEVICE);
63 ring->idx = (ring->idx + 1) % ring->entries;
65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
77 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
86 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
101 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
108 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
113 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
117 u8 rpwm_val, bool b_need_turn_off_ckk)
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
121 bool b_support_remote_wake_up;
122 u32 count = 0, isr_regaddr, content;
123 bool b_schedule_timer = b_need_turn_off_ckk;
125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
126 (u8 *)(&b_support_remote_wake_up));
128 if (!rtlhal->fw_ready)
130 if (!rtlpriv->psc.fw_current_inpsmode)
134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
135 if (rtlhal->fw_clk_change_in_progress) {
136 while (rtlhal->fw_clk_change_in_progress) {
137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
146 rtlhal->fw_clk_change_in_progress = false;
147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
152 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
155 if (FW_PS_IS_ACK(rpwm_val)) {
156 isr_regaddr = REG_HISR;
157 content = rtl_read_dword(rtlpriv, isr_regaddr);
158 while (!(content & IMR_CPWM) && (count < 500)) {
161 content = rtl_read_dword(rtlpriv, isr_regaddr);
164 if (content & IMR_CPWM) {
165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
168 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
169 rtlhal->fw_ps_state);
173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
174 rtlhal->fw_clk_change_in_progress = false;
175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
176 if (b_schedule_timer)
177 mod_timer(&rtlpriv->works.fw_clockoff_timer,
178 jiffies + MSECS(10));
180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
181 rtlhal->fw_clk_change_in_progress = false;
182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
192 struct rtl8192_tx_ring *ring;
193 enum rf_pwrstate rtstate;
194 bool b_schedule_timer = false;
197 if (!rtlhal->fw_ready)
199 if (!rtlpriv->psc.fw_current_inpsmode)
201 if (!rtlhal->allow_sw_to_change_hwclc)
203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
208 ring = &rtlpci->tx_ring[queue];
209 if (skb_queue_len(&ring->queue)) {
210 b_schedule_timer = true;
215 if (b_schedule_timer) {
216 mod_timer(&rtlpriv->works.fw_clockoff_timer,
217 jiffies + MSECS(10));
221 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
222 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
246 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
247 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255 bool fw_current_inps = false;
256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
258 if (ppsc->low_power_enable) {
259 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
260 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
261 rtlhal->allow_sw_to_change_hwclc = false;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
267 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&fw_pwrmode));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
273 (u8 *)(&fw_current_inps));
277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
279 struct rtl_priv *rtlpriv = rtl_priv(hw);
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
282 bool fw_current_inps = true;
285 if (ppsc->low_power_enable) {
286 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
287 rtlpriv->cfg->ops->set_hw_reg(hw,
288 HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw,
291 HW_VAR_H2C_FW_PWRMODE,
292 (u8 *)(&ppsc->fwctrl_psmode));
293 rtlhal->allow_sw_to_change_hwclc = true;
294 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
296 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
297 rtlpriv->cfg->ops->set_hw_reg(hw,
298 HW_VAR_FW_PSMODE_STATUS,
299 (u8 *)(&fw_current_inps));
300 rtlpriv->cfg->ops->set_hw_reg(hw,
301 HW_VAR_H2C_FW_PWRMODE,
302 (u8 *)(&ppsc->fwctrl_psmode));
303 rtlpriv->cfg->ops->set_hw_reg(hw,
309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
310 bool dl_whole_packets)
312 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
314 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
315 u8 count = 0, dlbcn_count = 0;
316 bool send_beacon = false;
318 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
319 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
321 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
322 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
324 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
325 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
326 tmp_reg422 & (~BIT(6)));
327 if (tmp_reg422 & BIT(6))
331 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
332 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
333 (bcnvalid_reg | BIT(0)));
334 _rtl8821ae_return_beacon_queue_skb(hw);
336 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
337 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
340 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
343 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
345 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
348 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
351 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
353 if (!(bcnvalid_reg & BIT(0)))
354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
355 "Download RSVD page failed!\n");
356 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
357 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
358 _rtl8821ae_return_beacon_queue_skb(hw);
362 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
363 bcnvalid_reg | BIT(0));
365 _rtl8821ae_return_beacon_queue_skb(hw);
367 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
368 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
371 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
374 /* check rsvd page download OK. */
375 bcnvalid_reg = rtl_read_byte(rtlpriv,
378 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
382 rtl_read_byte(rtlpriv,
386 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
388 if (!(bcnvalid_reg & BIT(0)))
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
390 "2 Download RSVD page failed!\n");
394 if (bcnvalid_reg & BIT(0))
395 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
397 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
398 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
403 if (!rtlhal->enter_pnp_sleep) {
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
414 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
417 case HW_VAR_ETHER_ADDR:
418 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
419 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
425 case HW_VAR_MEDIA_STATUS:
426 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
428 case HW_VAR_SLOT_TIME:
429 *((u8 *)(val)) = mac->slot_time;
431 case HW_VAR_BEACON_INTERVAL:
432 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
434 case HW_VAR_ATIM_WINDOW:
435 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
438 *((u32 *)(val)) = rtlpci->receive_config;
440 case HW_VAR_RF_STATE:
441 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
443 case HW_VAR_FWLPS_RF_ON:{
444 enum rf_pwrstate rfstate;
447 rtlpriv->cfg->ops->get_hw_reg(hw,
450 if (rfstate == ERFOFF) {
451 *((bool *)(val)) = true;
453 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
454 val_rcr &= 0x00070000;
456 *((bool *)(val)) = false;
458 *((bool *)(val)) = true;
461 case HW_VAR_FW_PSMODE_STATUS:
462 *((bool *)(val)) = ppsc->fw_current_inpsmode;
464 case HW_VAR_CORRECT_TSF:{
466 u32 *ptsf_low = (u32 *)&tsf;
467 u32 *ptsf_high = ((u32 *)&tsf) + 1;
469 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
470 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
472 *((u64 *)(val)) = tsf;
476 if (ppsc->wo_wlan_mode)
477 *((bool *)(val)) = true;
479 *((bool *)(val)) = false;
482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
483 "switch case %#x not processed\n", variable);
488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
490 struct rtl_priv *rtlpriv = rtl_priv(hw);
491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
494 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
499 case HW_VAR_ETHER_ADDR:{
500 for (idx = 0; idx < ETH_ALEN; idx++) {
501 rtl_write_byte(rtlpriv, (REG_MACID + idx),
506 case HW_VAR_BASIC_RATE:{
507 u16 b_rate_cfg = ((u16 *)val)[0];
508 b_rate_cfg = b_rate_cfg & 0x15f;
509 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
513 for (idx = 0; idx < ETH_ALEN; idx++) {
514 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
520 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
521 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
523 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
524 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
526 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
529 case HW_VAR_R2T_SIFS:
530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
532 case HW_VAR_SLOT_TIME:{
535 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
536 "HW_VAR_SLOT_TIME %x\n", val[0]);
538 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
540 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
541 rtlpriv->cfg->ops->set_hw_reg(hw,
546 case HW_VAR_ACK_PREAMBLE:{
548 u8 short_preamble = (bool)(*(u8 *)val);
550 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
551 if (short_preamble) {
553 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
556 reg_tmp &= (~BIT(1));
557 rtl_write_byte(rtlpriv,
562 case HW_VAR_WPA_CONFIG:
563 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
565 case HW_VAR_AMPDU_MIN_SPACE:{
566 u8 min_spacing_to_set;
569 min_spacing_to_set = *((u8 *)val);
570 if (min_spacing_to_set <= 7) {
573 if (min_spacing_to_set < sec_min_space)
574 min_spacing_to_set = sec_min_space;
576 mac->min_space_cfg = ((mac->min_space_cfg &
580 *val = min_spacing_to_set;
582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
590 case HW_VAR_SHORTGI_DENSITY:{
593 density_to_set = *((u8 *)val);
594 mac->min_space_cfg |= (density_to_set << 3);
596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
604 case HW_VAR_AMPDU_FACTOR:{
605 u32 ampdu_len = (*((u8 *)val));
607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
608 if (ampdu_len < VHT_AGG_SIZE_128K)
610 (0x2000 << (*((u8 *)val))) - 1;
613 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
614 if (ampdu_len < HT_AGG_SIZE_64K)
616 (0x2000 << (*((u8 *)val))) - 1;
620 ampdu_len |= BIT(31);
622 rtl_write_dword(rtlpriv,
623 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
625 case HW_VAR_AC_PARAM:{
626 u8 e_aci = *((u8 *)val);
628 rtl8821ae_dm_init_edca_turbo(hw);
629 if (rtlpci->acm_method != EACMWAY2_SW)
630 rtlpriv->cfg->ops->set_hw_reg(hw,
634 case HW_VAR_ACM_CTRL:{
635 u8 e_aci = *((u8 *)val);
636 union aci_aifsn *p_aci_aifsn =
637 (union aci_aifsn *)(&mac->ac[0].aifs);
638 u8 acm = p_aci_aifsn->f.acm;
639 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
642 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
647 acm_ctrl |= ACMHW_BEQEN;
650 acm_ctrl |= ACMHW_VIQEN;
653 acm_ctrl |= ACMHW_VOQEN;
656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
657 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
664 acm_ctrl &= (~ACMHW_BEQEN);
667 acm_ctrl &= (~ACMHW_VIQEN);
670 acm_ctrl &= (~ACMHW_VOQEN);
673 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
674 "switch case %#x not processed\n",
680 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
681 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
683 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
686 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
687 rtlpci->receive_config = ((u32 *)(val))[0];
689 case HW_VAR_RETRY_LIMIT:{
690 u8 retry_limit = ((u8 *)(val))[0];
692 rtl_write_word(rtlpriv, REG_RL,
693 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
694 retry_limit << RETRY_LIMIT_LONG_SHIFT);
696 case HW_VAR_DUAL_TSF_RST:
697 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
699 case HW_VAR_EFUSE_BYTES:
700 rtlefuse->efuse_usedbytes = *((u16 *)val);
702 case HW_VAR_EFUSE_USAGE:
703 rtlefuse->efuse_usedpercentage = *((u8 *)val);
706 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
708 case HW_VAR_SET_RPWM:{
711 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
714 if (rpwm_val & BIT(7)) {
715 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
718 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
719 ((*(u8 *)val) | BIT(7)));
723 case HW_VAR_H2C_FW_PWRMODE:
724 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
726 case HW_VAR_FW_PSMODE_STATUS:
727 ppsc->fw_current_inpsmode = *((bool *)val);
729 case HW_VAR_INIT_RTS_RATE:
731 case HW_VAR_RESUME_CLK_ON:
732 _rtl8821ae_set_fw_ps_rf_on(hw);
734 case HW_VAR_FW_LPS_ACTION:{
735 bool b_enter_fwlps = *((bool *)val);
738 _rtl8821ae_fwlps_enter(hw);
740 _rtl8821ae_fwlps_leave(hw);
742 case HW_VAR_H2C_FW_JOINBSSRPT:{
743 u8 mstatus = (*(u8 *)val);
745 if (mstatus == RT_MEDIA_CONNECT) {
746 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
748 _rtl8821ae_download_rsvd_page(hw, false);
750 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
753 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
754 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
758 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
760 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
763 case HW_VAR_CORRECT_TSF:{
764 u8 btype_ibss = ((u8 *)(val))[0];
767 _rtl8821ae_stop_tx_beacon(hw);
769 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
771 rtl_write_dword(rtlpriv, REG_TSFTR,
772 (u32)(mac->tsf & 0xffffffff));
773 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
774 (u32)((mac->tsf >> 32) & 0xffffffff));
776 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
779 _rtl8821ae_resume_tx_beacon(hw);
781 case HW_VAR_NAV_UPPER: {
782 u32 us_nav_upper = ((u32)*val);
784 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
785 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
786 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
787 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
790 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
791 ((u8)((us_nav_upper +
792 HAL_92C_NAV_UPPER_UNIT - 1) /
793 HAL_92C_NAV_UPPER_UNIT)));
795 case HW_VAR_KEEP_ALIVE: {
798 array[1] = *((u8 *)val);
799 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
803 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
804 "switch case %#x not processed\n", variable);
809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
811 struct rtl_priv *rtlpriv = rtl_priv(hw);
814 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
815 _LLT_OP(_LLT_WRITE_ACCESS);
817 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
820 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
821 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
824 if (count > POLLING_LLT_THRESHOLD) {
825 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
826 "Failed to polling write LLT done at address %d!\n",
836 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
838 struct rtl_priv *rtlpriv = rtl_priv(hw);
846 txpktbuf_bndy = 0xF8;
848 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
849 txpktbuf_bndy = 0xFA;
853 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
854 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
856 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
858 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
859 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
861 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
862 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
864 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
865 status = _rtl8821ae_llt_write(hw, i, i + 1);
870 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
874 for (i = txpktbuf_bndy; i < maxpage; i++) {
875 status = _rtl8821ae_llt_write(hw, i, (i + 1));
880 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
884 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
886 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
891 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
893 struct rtl_priv *rtlpriv = rtl_priv(hw);
894 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
895 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
896 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
897 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
899 if (rtlpriv->rtlhal.up_first_time)
902 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
903 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
904 rtl8812ae_sw_led_on(hw, pled0);
906 rtl8821ae_sw_led_on(hw, pled0);
907 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
908 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
909 rtl8812ae_sw_led_on(hw, pled0);
911 rtl8821ae_sw_led_on(hw, pled0);
913 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
914 rtl8812ae_sw_led_off(hw, pled0);
916 rtl8821ae_sw_led_off(hw, pled0);
919 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
921 struct rtl_priv *rtlpriv = rtl_priv(hw);
922 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
923 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
927 bool mac_func_enable = rtlhal->mac_func_enable;
929 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
931 /*Auto Power Down to CHIP-off State*/
932 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
933 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
935 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
936 /* HW Power on sequence*/
937 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
938 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
939 RTL8812_NIC_ENABLE_FLOW)) {
940 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
941 "init 8812 MAC Fail as power on failure\n");
945 /* HW Power on sequence */
946 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
947 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
948 RTL8821A_NIC_ENABLE_FLOW)){
949 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
950 "init 8821 MAC Fail as power on failure\n");
955 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
956 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
958 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
960 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
964 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
967 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
968 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
969 if (bytetmp & BIT(0)) {
970 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
972 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
976 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
978 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
980 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
982 if (!mac_func_enable) {
983 if (!_rtl8821ae_llt_table_init(hw))
987 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
988 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
990 /* Enable FW Beamformer Interrupt */
991 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
992 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
994 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
997 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
999 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
1000 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1001 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1003 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1004 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1005 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1006 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1007 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1008 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1009 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1010 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1011 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1012 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1013 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1014 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1015 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1016 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1017 rtl_write_dword(rtlpriv, REG_RX_DESA,
1018 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1020 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1022 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1024 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1026 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1027 _rtl8821ae_gen_refresh_led_state(hw);
1032 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1034 struct rtl_priv *rtlpriv = rtl_priv(hw);
1035 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1038 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1040 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1041 /* ARFB table 9 for 11ac 5G 2SS */
1042 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1043 /* ARFB table 10 for 11ac 5G 1SS */
1044 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1045 /* ARFB table 11 for 11ac 24G 1SS */
1046 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1047 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1048 /* ARFB table 12 for 11ac 24G 1SS */
1049 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1050 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1051 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1052 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1053 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1056 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1058 /* Set Data / Response auto rate fallack retry count*/
1059 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1060 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1061 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1062 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1064 rtlpci->reg_bcn_ctrl_val = 0x1d;
1065 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1067 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1068 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1070 /* AGGR_BK_TIME Reg51A 0x16 */
1071 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1073 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1074 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1076 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1077 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1078 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1081 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1084 u8 tmp = 0, count = 0;
1086 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1087 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1089 while (tmp && count < 20) {
1091 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1095 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1100 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1102 u8 tmp = 0, count = 0;
1104 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1105 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1106 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1108 while (tmp && count < 20) {
1110 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1115 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1117 u16 read_addr = addr & 0xfffc;
1118 u8 tmp = 0, count = 0, ret = 0;
1120 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1121 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1122 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1124 while (tmp && count < 20) {
1126 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1130 read_addr = REG_DBI_RDATA + addr % 4;
1131 ret = rtl_read_byte(rtlpriv, read_addr);
1136 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1138 u8 tmp = 0, count = 0;
1139 u16 wrtie_addr, remainder = addr % 4;
1141 wrtie_addr = REG_DBI_WDATA + remainder;
1142 rtl_write_byte(rtlpriv, wrtie_addr, data);
1144 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1145 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1147 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1149 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1151 while (tmp && count < 20) {
1153 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1158 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1160 struct rtl_priv *rtlpriv = rtl_priv(hw);
1161 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1164 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1165 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1166 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1168 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1169 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1172 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1173 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1174 ASPM_L1_LATENCY << 3);
1176 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1177 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1179 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1180 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1181 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1185 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1187 struct rtl_priv *rtlpriv = rtl_priv(hw);
1191 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1192 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1193 rtlpriv->sec.pairwise_enc_algorithm,
1194 rtlpriv->sec.group_enc_algorithm);
1196 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1197 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1198 "not open hw encryption\n");
1202 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1204 if (rtlpriv->sec.use_defaultkey) {
1205 sec_reg_value |= SCR_TXUSEDK;
1206 sec_reg_value |= SCR_RXUSEDK;
1209 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1211 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1212 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1214 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1215 "The SECR-value %x\n", sec_reg_value);
1217 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1220 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1221 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1222 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1223 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1224 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1225 /* ----------------------------------------------------------- */
1227 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1229 struct rtl_priv *rtlpriv = rtl_priv(hw);
1230 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1231 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1232 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1234 rtlpriv->cfg->ops->set_hw_reg(hw,
1235 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1237 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1238 "Initialize MacId media status: from %d to %d\n",
1239 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1240 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1243 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1245 struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1249 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1250 if (!(tmp & BIT(2))) {
1251 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1255 /* read reg 0x350 Bit[25] if 1 : RX hang */
1256 /* read reg 0x350 Bit[24] if 1 : TX hang */
1257 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1258 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1259 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1260 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1267 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1271 struct rtl_priv *rtlpriv = rtl_priv(hw);
1272 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1274 bool release_mac_rx_pause;
1275 u8 backup_pcie_dma_pause;
1277 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1279 /* 1. Disable register write lock. 0x1c[1] = 0 */
1280 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1282 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1283 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1284 /* write 0xCC bit[2] = 1'b1 */
1285 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1287 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1290 /* 2. Check and pause TRX DMA */
1291 /* write 0x284 bit[18] = 1'b1 */
1292 /* write 0x301 = 0xFF */
1293 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1295 /* Already pause before the function for another purpose. */
1296 release_mac_rx_pause = false;
1298 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1299 release_mac_rx_pause = true;
1301 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1302 if (backup_pcie_dma_pause != 0xFF)
1303 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1306 /* 3. reset TRX function */
1307 /* write 0x100 = 0x00 */
1308 rtl_write_byte(rtlpriv, REG_CR, 0);
1311 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1312 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1314 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1316 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1317 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1319 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1322 /* 6. enable TRX function */
1323 /* write 0x100 = 0xFF */
1324 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1326 /* We should init LLT & RQPN and
1327 * prepare Tx/Rx descrptor address later
1328 * because MAC function is reset.*/
1331 /* 7. Restore PCIe autoload down bit */
1332 /* 8812AE does not has the defination. */
1333 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1334 /* write 0xF8 bit[17] = 1'b1 */
1335 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1337 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1340 /* In MAC power on state, BB and RF maybe in ON state,
1341 * if we release TRx DMA here.
1342 * it will cause packets to be started to Tx/Rx,
1343 * so we release Tx/Rx DMA later.*/
1344 if (!mac_power_on/* || in_watchdog*/) {
1345 /* 8. release TRX DMA */
1346 /* write 0x284 bit[18] = 1'b0 */
1347 /* write 0x301 = 0x00 */
1348 if (release_mac_rx_pause) {
1349 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1350 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1353 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1354 backup_pcie_dma_pause);
1357 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1358 /* 9. lock system register */
1359 /* write 0xCC bit[2] = 1'b0 */
1360 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1362 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1367 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1369 struct rtl_priv *rtlpriv = rtl_priv(hw);
1370 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1371 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1375 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1377 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1380 ppsc->wakeup_reason = 0;
1382 do_gettimeofday(&ts);
1383 rtlhal->last_suspend_sec = ts.tv_sec;
1385 switch (fw_reason) {
1386 case FW_WOW_V2_PTK_UPDATE_EVENT:
1387 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1388 do_gettimeofday(&ts);
1389 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1390 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1391 "It's a WOL PTK Key update event!\n");
1393 case FW_WOW_V2_GTK_UPDATE_EVENT:
1394 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1395 do_gettimeofday(&ts);
1396 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1397 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1398 "It's a WOL GTK Key update event!\n");
1400 case FW_WOW_V2_DISASSOC_EVENT:
1401 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1402 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1403 "It's a disassociation event!\n");
1405 case FW_WOW_V2_DEAUTH_EVENT:
1406 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1407 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1408 "It's a deauth event!\n");
1410 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1411 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1412 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1413 "It's a Fw disconnect decision (AP lost) event!\n");
1415 case FW_WOW_V2_MAGIC_PKT_EVENT:
1416 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1417 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1418 "It's a magic packet event!\n");
1420 case FW_WOW_V2_UNICAST_PKT_EVENT:
1421 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1422 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1423 "It's an unicast packet event!\n");
1425 case FW_WOW_V2_PATTERN_PKT_EVENT:
1426 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1427 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1428 "It's a pattern match event!\n");
1430 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1431 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1432 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1433 "It's an RTD3 Ssid match event!\n");
1435 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1436 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1437 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1438 "It's an RealWoW wake packet event!\n");
1440 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1441 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1442 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1443 "It's an RealWoW ack lost event!\n");
1446 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1447 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1453 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1459 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1460 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1461 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1462 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1463 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1464 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1465 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1466 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1467 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1468 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1469 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1470 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1471 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1472 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1473 rtl_write_dword(rtlpriv, REG_RX_DESA,
1474 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1477 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1481 u32 txpktbuf_bndy = boundary;
1482 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1484 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1485 status = _rtl8821ae_llt_write(hw, i , i + 1);
1490 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1494 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1495 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1500 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1508 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1509 u16 npq_rqpn_value, u32 rqpn_val)
1511 struct rtl_priv *rtlpriv = rtl_priv(hw);
1514 u16 count = 0, tmp16;
1515 bool support_remote_wakeup;
1517 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1518 (u8 *)(&support_remote_wakeup));
1520 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1521 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1522 boundary, npq_rqpn_value, rqpn_val);
1525 * 1. 0x301[7:0] = 0xFE */
1526 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1529 * 2. polling till 0x41A[15:0]=0x07FF */
1530 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1531 while ((tmp16 & 0x07FF) != 0x07FF) {
1533 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1535 if ((count % 200) == 0) {
1536 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1537 "Tx queue is not empty for 20ms!\n");
1539 if (count >= 1000) {
1540 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1541 "Wait for Tx FIFO empty timeout!\n");
1547 * 3. reg 0x522=0xFF */
1548 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1550 /* Wait TX State Machine OK
1551 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1553 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1557 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1558 "Wait for TX State Machine ready timeout !!\n");
1565 * 6. wait till 0x284[17] == 1
1566 * wait RX DMA idle */
1568 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1569 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1571 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1574 } while (!(tmp & BIT(1)) && count < 100);
1576 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1577 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1581 * 7. 0x02 [0] = 0 */
1582 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1584 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1589 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1592 /* Disable MAC Security Engine
1593 * 9. 0x100 bit[9]=0 */
1594 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1596 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1598 /* To avoid DD-Tim Circuit hang
1599 * 10. 0x553 bit[5]=1 */
1600 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1601 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1603 /* Enable MAC Security Engine
1604 * 11. 0x100 bit[9]=1 */
1605 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1606 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1611 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1615 * 13. 0x02 [0] = 1 */
1616 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1617 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1620 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1621 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1622 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1623 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1625 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1627 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1630 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1634 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1635 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1636 "Failed to init LLT table!\n");
1641 * 18. reallocate RQPN and init LLT */
1642 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1643 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1647 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1650 * 20. 0x301[7:0] = 0x00
1651 * 21. 0x284[18] = 0 */
1652 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1653 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1654 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1656 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1660 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1662 struct rtl_priv *rtlpriv = rtl_priv(hw);
1663 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1664 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1666 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1667 /* Re-download normal Fw. */
1668 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1671 /* Re-Initialize LLT table. */
1672 if (rtlhal->re_init_llt_table) {
1673 u32 rqpn = 0x80e70808;
1674 u8 rqpn_npq = 0, boundary = 0xF8;
1675 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1679 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1680 rtlhal->re_init_llt_table = false;
1683 ppsc->rfpwr_state = ERFON;
1686 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1689 struct rtl_priv *rtlpriv = rtl_priv(hw);
1691 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1693 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1694 if (!(tmp & (BIT(2) | BIT(3)))) {
1695 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1696 "0x160(%#x)return!!\n", tmp);
1700 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1701 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1703 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1704 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1706 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1709 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1712 struct rtl_priv *rtlpriv = rtl_priv(hw);
1714 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1716 /* Check 0x98[10] */
1717 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1718 if (!(tmp & BIT(2))) {
1719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1720 "<---0x99(%#x) return!!\n", tmp);
1724 /* LTR idle latency, 0x90 for 144us */
1725 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1727 /* LTR active latency, 0x3c for 60us */
1728 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1730 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1731 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1733 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1734 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1735 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1737 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1740 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1742 struct rtl_priv *rtlpriv = rtl_priv(hw);
1743 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1744 bool init_finished = true;
1747 /* Get Fw wake up reason. */
1748 _rtl8821ae_get_wakeup_reason(hw);
1750 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1751 * The root cause has not be found. */
1752 if (_rtl8821ae_check_pcie_dma_hang(hw))
1753 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1755 /* Prepare Tx/Rx Desc Hw address. */
1756 _rtl8821ae_init_trx_desc_hw_address(hw);
1758 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1759 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1760 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1762 /* Check wake up event.
1763 * We should check wake packet bit before disable wowlan by H2C or
1764 * Fw will clear the bit. */
1765 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1766 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1767 "Read REG_FTISR 0x13f = %#X\n", tmp);
1769 /* Set the WoWLAN related function control disable. */
1770 rtl8821ae_set_fw_wowlan_mode(hw, false);
1771 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1773 if (rtlhal->hw_rof_enable) {
1774 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1776 /* Clear GPIO9 ISR */
1777 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1778 init_finished = false;
1780 init_finished = true;
1784 if (init_finished) {
1785 _rtl8821ae_simple_initialize_adapter(hw);
1787 /* Release Pcie Interface Tx DMA. */
1788 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1789 /* Release Pcie RX DMA */
1790 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1792 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1793 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1795 _rtl8821ae_enable_l1off(hw);
1796 _rtl8821ae_enable_ltr(hw);
1799 return init_finished;
1802 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1804 /* BB OFDM RX Path_A */
1805 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1806 /* BB OFDM TX Path_A */
1807 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1808 /* BB CCK R/Rx Path_A */
1809 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1811 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1812 /* RF Path_B HSSI OFF */
1813 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1814 /* RF Path_B Power Down */
1815 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1816 /* ADDA Path_B OFF */
1817 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1818 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1821 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1823 struct rtl_priv *rtlpriv = rtl_priv(hw);
1824 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1827 rtlhal->mac_func_enable = false;
1829 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1830 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1831 /* 1. Run LPS WL RFOFF flow */
1832 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1833 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1835 rtl_hal_pwrseqcmdparsing(rtlpriv,
1836 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1837 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1839 /* 2. 0x1F[7:0] = 0 */
1841 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1842 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1844 rtl8821ae_firmware_selfreset(hw);
1847 /* Reset MCU. Suggested by Filen. */
1848 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1849 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1851 /* g. MCUFWDL 0x80[1:0]=0 */
1852 /* reset MCU ready status */
1853 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1855 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1856 /* HW card disable configuration. */
1857 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1858 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1860 /* HW card disable configuration. */
1861 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1862 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1865 /* Reset MCU IO Wrapper */
1866 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1867 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1868 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1869 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1871 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1872 /* lock ISO/CLK/Power control register */
1873 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1876 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1878 struct rtl_priv *rtlpriv = rtl_priv(hw);
1879 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1880 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1881 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1882 bool rtstatus = true;
1885 bool support_remote_wakeup;
1886 u32 nav_upper = WIFI_NAV_UPPER_US;
1888 rtlhal->being_init_adapter = true;
1889 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1890 (u8 *)(&support_remote_wakeup));
1891 rtlpriv->intf_ops->disable_aspm(hw);
1893 /*YP wowlan not considered*/
1895 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1896 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1897 rtlhal->mac_func_enable = true;
1898 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1899 "MAC has already power on.\n");
1901 rtlhal->mac_func_enable = false;
1902 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1905 if (support_remote_wakeup &&
1906 rtlhal->wake_from_pnp_sleep &&
1907 rtlhal->mac_func_enable) {
1908 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1909 rtlhal->being_init_adapter = false;
1914 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1915 _rtl8821ae_reset_pcie_interface_dma(hw,
1916 rtlhal->mac_func_enable,
1918 rtlhal->mac_func_enable = false;
1921 /* Reset MAC/BB/RF status if it is not powered off
1922 * before calling initialize Hw flow to prevent
1923 * from interface and MAC status mismatch.
1924 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1925 if (rtlhal->mac_func_enable) {
1926 _rtl8821ae_poweroff_adapter(hw);
1927 rtlhal->mac_func_enable = false;
1930 rtstatus = _rtl8821ae_init_mac(hw);
1931 if (rtstatus != true) {
1932 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1937 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1939 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1941 err = rtl8821ae_download_fw(hw, false);
1943 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1944 "Failed to download FW. Init HW without FW now\n");
1946 rtlhal->fw_ready = false;
1949 rtlhal->fw_ready = true;
1951 ppsc->fw_current_inpsmode = false;
1952 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1953 rtlhal->fw_clk_change_in_progress = false;
1954 rtlhal->allow_sw_to_change_hwclc = false;
1955 rtlhal->last_hmeboxnum = 0;
1957 /*SIC_Init(Adapter);
1958 if(rtlhal->AMPDUBurstMode)
1959 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1961 rtl8821ae_phy_mac_config(hw);
1962 /* because last function modify RCR, so we update
1963 * rcr var here, or TP will unstable for receive_config
1964 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1965 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1966 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1967 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1968 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1969 rtl8821ae_phy_bb_config(hw);
1971 rtl8821ae_phy_rf_config(hw);
1973 if (rtlpriv->phy.rf_type == RF_1T1R &&
1974 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1975 _rtl8812ae_bb8812_config_1t(hw);
1977 _rtl8821ae_hw_configure(hw);
1979 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1981 /*set wireless mode*/
1983 rtlhal->mac_func_enable = true;
1985 rtl_cam_reset_all_entry(hw);
1987 rtl8821ae_enable_hw_security_config(hw);
1989 ppsc->rfpwr_state = ERFON;
1991 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1992 _rtl8821ae_enable_aspm_back_door(hw);
1993 rtlpriv->intf_ops->enable_aspm(hw);
1995 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1996 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1997 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1999 rtl8821ae_bt_hw_init(hw);
2000 rtlpriv->rtlhal.being_init_adapter = false;
2002 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2004 /* rtl8821ae_dm_check_txpower_tracking(hw); */
2005 /* rtl8821ae_phy_lc_calibrate(hw); */
2006 if (support_remote_wakeup)
2007 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2010 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2011 if (tmp_u1b & BIT(2)) {
2012 /* Release Rx DMA if needed*/
2014 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2017 /* Release Tx/Rx PCIE DMA if*/
2018 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2020 rtl8821ae_dm_init(hw);
2021 rtl8821ae_macid_initialize_mediastatus(hw);
2023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2027 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2029 struct rtl_priv *rtlpriv = rtl_priv(hw);
2030 struct rtl_phy *rtlphy = &rtlpriv->phy;
2031 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2032 enum version_8821ae version = VERSION_UNKNOWN;
2035 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2036 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2037 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2039 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2040 rtlphy->rf_type = RF_2T2R;
2041 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2042 rtlphy->rf_type = RF_1T1R;
2044 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2045 "RF_Type is %x!!\n", rtlphy->rf_type);
2047 if (value32 & TRP_VAUX_EN) {
2048 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2049 if (rtlphy->rf_type == RF_2T2R)
2050 version = VERSION_TEST_CHIP_2T2R_8812;
2052 version = VERSION_TEST_CHIP_1T1R_8812;
2054 version = VERSION_TEST_CHIP_8821;
2056 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2057 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2059 if (rtlphy->rf_type == RF_2T2R)
2061 (enum version_8821ae)(CHIP_8812
2065 version = (enum version_8821ae)(CHIP_8812
2068 version = (enum version_8821ae)(version | (rtl_id << 12));
2069 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2070 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2072 version = (enum version_8821ae)(CHIP_8821
2073 | NORMAL_CHIP | rtl_id);
2077 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2079 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2080 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2084 case VERSION_TEST_CHIP_1T1R_8812:
2085 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2086 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2088 case VERSION_TEST_CHIP_2T2R_8812:
2089 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2090 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2092 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2093 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2094 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2096 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2097 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2098 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2100 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2101 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2102 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2104 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2105 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2106 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2108 case VERSION_TEST_CHIP_8821:
2109 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2110 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2112 case VERSION_NORMAL_TSMC_CHIP_8821:
2113 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2114 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2116 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2117 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2118 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2121 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2122 "Chip Version ID: Unknow (0x%X)\n", version);
2129 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2130 enum nl80211_iftype type)
2132 struct rtl_priv *rtlpriv = rtl_priv(hw);
2133 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2134 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2137 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2138 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2139 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2141 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2142 type == NL80211_IFTYPE_STATION) {
2143 _rtl8821ae_stop_tx_beacon(hw);
2144 _rtl8821ae_enable_bcn_sub_func(hw);
2145 } else if (type == NL80211_IFTYPE_ADHOC ||
2146 type == NL80211_IFTYPE_AP) {
2147 _rtl8821ae_resume_tx_beacon(hw);
2148 _rtl8821ae_disable_bcn_sub_func(hw);
2150 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2151 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2156 case NL80211_IFTYPE_UNSPECIFIED:
2157 bt_msr |= MSR_NOLINK;
2158 ledaction = LED_CTL_LINK;
2159 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2160 "Set Network type to NO LINK!\n");
2162 case NL80211_IFTYPE_ADHOC:
2163 bt_msr |= MSR_ADHOC;
2164 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2165 "Set Network type to Ad Hoc!\n");
2167 case NL80211_IFTYPE_STATION:
2168 bt_msr |= MSR_INFRA;
2169 ledaction = LED_CTL_LINK;
2170 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2171 "Set Network type to STA!\n");
2173 case NL80211_IFTYPE_AP:
2175 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2176 "Set Network type to AP!\n");
2179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2180 "Network type %d not support!\n", type);
2184 rtl_write_byte(rtlpriv, MSR, bt_msr);
2185 rtlpriv->cfg->ops->led_control(hw, ledaction);
2186 if ((bt_msr & MSR_MASK) == MSR_AP)
2187 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2189 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2194 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2196 struct rtl_priv *rtlpriv = rtl_priv(hw);
2197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2198 u32 reg_rcr = rtlpci->receive_config;
2200 if (rtlpriv->psc.rfpwr_state != ERFON)
2204 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2205 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2207 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2208 } else if (!check_bssid) {
2209 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2210 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2211 rtlpriv->cfg->ops->set_hw_reg(hw,
2212 HW_VAR_RCR, (u8 *)(®_rcr));
2216 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2218 struct rtl_priv *rtlpriv = rtl_priv(hw);
2220 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2222 if (_rtl8821ae_set_media_status(hw, type))
2225 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2226 if (type != NL80211_IFTYPE_AP)
2227 rtl8821ae_set_check_bssid(hw, true);
2229 rtl8821ae_set_check_bssid(hw, false);
2235 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2236 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2238 struct rtl_priv *rtlpriv = rtl_priv(hw);
2239 rtl8821ae_dm_init_edca_turbo(hw);
2242 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2245 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2248 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2251 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2254 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2259 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2261 struct rtl_priv *rtlpriv = rtl_priv(hw);
2262 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2264 rtl_write_dword(rtlpriv, REG_HISR, tmp);
2266 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2267 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2269 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2270 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2273 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2275 struct rtl_priv *rtlpriv = rtl_priv(hw);
2276 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2278 if (rtlpci->int_clear)
2279 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2281 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2282 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2283 rtlpci->irq_enabled = true;
2284 /* there are some C2H CMDs have been sent before
2285 system interrupt is enabled, e.g., C2H, CPWM.
2286 *So we need to clear all C2H events that FW has
2287 notified, otherwise FW won't schedule any commands anymore.
2289 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2290 /*enable system interrupt*/
2291 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2294 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2296 struct rtl_priv *rtlpriv = rtl_priv(hw);
2297 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2299 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2300 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2301 rtlpci->irq_enabled = false;
2302 /*synchronize_irq(rtlpci->pdev->irq);*/
2305 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2307 struct rtl_priv *rtlpriv = rtl_priv(hw);
2308 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2315 /* Get the Capability pointer first,
2316 * the Capability Pointer is located at
2317 * offset 0x34 from the Function Header */
2319 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2320 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2321 "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2324 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2325 cap_id = cap_hdr & 0xFF;
2327 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2328 "in pci configuration, cap_pointer%x = %x\n",
2329 cap_pointer, cap_id);
2331 if (cap_id == 0x01) {
2334 /* point to next Capability */
2335 cap_pointer = (cap_hdr >> 8) & 0xFF;
2336 /* 0: end of pci capability, 0xff: invalid value */
2337 if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2342 } while (cnt++ < 200);
2344 if (cap_id == 0x01) {
2345 /* Get the PM CSR (Control/Status Register),
2346 * The PME_Status is located at PM Capatibility offset 5, bit 7
2348 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2350 if (pmcs_reg & BIT(7)) {
2351 /* PME event occured, clear the PM_Status by write 1 */
2352 pmcs_reg = pmcs_reg | BIT(7);
2354 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2356 /* Read it back to check */
2357 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2359 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2360 "Clear PME status 0x%2x to 0x%2x\n",
2361 cap_pointer + 5, pmcs_reg);
2363 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2364 "PME status(0x%2x) = 0x%2x\n",
2365 cap_pointer + 5, pmcs_reg);
2368 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2369 "Cannot find PME Capability\n");
2373 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2375 struct rtl_priv *rtlpriv = rtl_priv(hw);
2376 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2377 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2378 struct rtl_mac *mac = rtl_mac(rtlpriv);
2379 enum nl80211_iftype opmode;
2380 bool support_remote_wakeup;
2384 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2385 (u8 *)(&support_remote_wakeup));
2387 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2389 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2390 || !rtlhal->enter_pnp_sleep) {
2391 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2392 mac->link_state = MAC80211_NOLINK;
2393 opmode = NL80211_IFTYPE_UNSPECIFIED;
2394 _rtl8821ae_set_media_status(hw, opmode);
2395 _rtl8821ae_poweroff_adapter(hw);
2397 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2398 /* 3 <1> Prepare for configuring wowlan related infomations */
2399 /* Clear Fw WoWLAN event. */
2400 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2402 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2403 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2405 /* Dynamically adjust Tx packet boundary
2406 * for download reserved page packet.
2407 * reserve 30 pages for rsvd page */
2408 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2409 rtlhal->re_init_llt_table = true;
2411 /* 3 <2> Set Fw releted H2C cmd. */
2413 /* Set WoWLAN related security information. */
2414 rtl8821ae_set_fw_global_info_cmd(hw);
2416 _rtl8821ae_download_rsvd_page(hw, true);
2418 /* Just enable AOAC related functions when we connect to AP. */
2419 printk("mac->link_state = %d\n", mac->link_state);
2420 if (mac->link_state >= MAC80211_LINKED &&
2421 mac->opmode == NL80211_IFTYPE_STATION) {
2422 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2423 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2426 rtl8821ae_set_fw_wowlan_mode(hw, true);
2427 /* Enable Fw Keep alive mechanism. */
2428 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2430 /* Enable disconnect decision control. */
2431 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2434 /* 3 <3> Hw Configutations */
2436 /* Wait untill Rx DMA Finished before host sleep.
2437 * FW Pause Rx DMA may happens when received packet doing dma.
2439 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2441 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2443 while (!(tmp & BIT(1)) && (count++ < 100)) {
2445 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2447 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2448 "Wait Rx DMA Finished before host sleep. count=%d\n",
2451 /* reset trx ring */
2452 rtlpriv->intf_ops->reset_trx_ring(hw);
2454 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2456 _rtl8821ae_clear_pci_pme_status(hw);
2457 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2458 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2459 /* prevent 8051 to be reset by PERST */
2460 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2461 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2464 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2465 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2466 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2467 /* For wowlan+LPS+32k. */
2468 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2469 /* Set the WoWLAN related function control enable.
2470 * It should be the last H2C cmd in the WoWLAN flow. */
2471 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2473 /* Stop Pcie Interface Tx DMA. */
2474 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2475 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2477 /* Wait for TxDMA idle. */
2480 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2483 } while ((tmp != 0) && (count < 100));
2484 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2485 "Wait Tx DMA Finished before host sleep. count=%d\n",
2488 if (rtlhal->hw_rof_enable) {
2489 printk("hw_rof_enable\n");
2490 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2491 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2494 /* after power off we should do iqk again */
2495 rtlpriv->phy.iqk_initialized = false;
2498 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2499 u32 *p_inta, u32 *p_intb)
2501 struct rtl_priv *rtlpriv = rtl_priv(hw);
2502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2504 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2505 rtl_write_dword(rtlpriv, ISR, *p_inta);
2507 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2508 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2511 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2513 struct rtl_priv *rtlpriv = rtl_priv(hw);
2514 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2516 u16 bcn_interval, atim_window;
2518 bcn_interval = mac->beacon_interval;
2519 atim_window = 2; /*FIX MERGE */
2520 rtl8821ae_disable_interrupt(hw);
2521 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2522 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2523 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2524 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2525 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2526 rtl_write_byte(rtlpriv, 0x606, 0x30);
2527 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2528 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2529 rtl8821ae_enable_interrupt(hw);
2532 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2534 struct rtl_priv *rtlpriv = rtl_priv(hw);
2535 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2536 u16 bcn_interval = mac->beacon_interval;
2538 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2539 "beacon_interval:%d\n", bcn_interval);
2540 rtl8821ae_disable_interrupt(hw);
2541 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2542 rtl8821ae_enable_interrupt(hw);
2545 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2546 u32 add_msr, u32 rm_msr)
2548 struct rtl_priv *rtlpriv = rtl_priv(hw);
2549 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2551 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2552 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2555 rtlpci->irq_mask[0] |= add_msr;
2557 rtlpci->irq_mask[0] &= (~rm_msr);
2558 rtl8821ae_disable_interrupt(hw);
2559 rtl8821ae_enable_interrupt(hw);
2562 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2567 if (1 <= chnl && chnl <= 2)
2569 else if (3 <= chnl && chnl <= 5)
2571 else if (6 <= chnl && chnl <= 8)
2573 else if (9 <= chnl && chnl <= 11)
2575 else /*if (12 <= chnl && chnl <= 14)*/
2578 if (36 <= chnl && chnl <= 42)
2580 else if (44 <= chnl && chnl <= 48)
2582 else if (50 <= chnl && chnl <= 58)
2584 else if (60 <= chnl && chnl <= 64)
2586 else if (100 <= chnl && chnl <= 106)
2588 else if (108 <= chnl && chnl <= 114)
2590 else if (116 <= chnl && chnl <= 122)
2592 else if (124 <= chnl && chnl <= 130)
2594 else if (132 <= chnl && chnl <= 138)
2596 else if (140 <= chnl && chnl <= 144)
2598 else if (149 <= chnl && chnl <= 155)
2600 else if (157 <= chnl && chnl <= 161)
2602 else if (165 <= chnl && chnl <= 171)
2604 else if (173 <= chnl && chnl <= 177)
2607 /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2608 "5G, Channel %d in Group not found\n",chnl);*/
2609 RT_ASSERT(!COMP_EFUSE,
2610 "5G, Channel %d in Group not found\n", chnl);
2615 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2616 struct txpower_info_2g *pwrinfo24g,
2617 struct txpower_info_5g *pwrinfo5g,
2621 struct rtl_priv *rtlpriv = rtl_priv(hw);
2622 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2624 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2625 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2626 (eeAddr+1), hwinfo[eeAddr+1]);
2627 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/
2628 autoload_fail = true;
2630 if (autoload_fail) {
2631 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2632 "auto load fail : Use Default value!\n");
2633 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2634 /*2.4G default value*/
2635 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2636 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2637 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2639 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2641 pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2642 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2644 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2645 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2646 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2647 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2650 /*5G default value*/
2651 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2652 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2654 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2656 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2657 pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2658 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2659 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2661 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2662 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2663 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2664 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2665 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2672 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2674 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2675 /*2.4G default value*/
2676 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2677 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2678 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2679 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2681 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2682 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2683 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2684 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2686 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2688 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2689 /*bit sign number to 8 bit sign number*/
2690 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2691 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2692 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2693 /*bit sign number to 8 bit sign number*/
2694 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2695 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2696 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2698 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2701 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2702 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2703 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2705 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2706 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2707 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2711 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2712 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2713 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2715 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2716 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2717 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2723 /*5G default value*/
2724 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2725 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2726 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2727 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2730 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2732 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2734 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2735 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2736 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2738 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2739 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2740 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2744 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2745 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2746 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2748 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2749 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2750 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2756 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4;
2757 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f);
2761 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2765 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2766 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2767 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2769 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2770 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2771 /* 4bit sign number to 8 bit sign number */
2772 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2773 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2774 /* 4bit sign number to 8 bit sign number */
2775 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2776 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2777 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2784 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2788 struct rtl_priv *rtlpriv = rtl_priv(hw);
2789 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2790 struct txpower_info_2g pwrinfo24g;
2791 struct txpower_info_5g pwrinfo5g;
2795 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2796 &pwrinfo5g, autoload_fail, hwinfo);
2798 for (rf_path = 0; rf_path < 2; rf_path++) {
2799 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2800 index = _rtl8821ae_get_chnl_group(i + 1);
2802 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2803 rtlefuse->txpwrlevel_cck[rf_path][i] =
2804 pwrinfo24g.index_cck_base[rf_path][5];
2805 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2806 pwrinfo24g.index_bw40_base[rf_path][index];
2808 rtlefuse->txpwrlevel_cck[rf_path][i] =
2809 pwrinfo24g.index_cck_base[rf_path][index];
2810 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2811 pwrinfo24g.index_bw40_base[rf_path][index];
2815 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2816 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2817 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2818 pwrinfo5g.index_bw40_base[rf_path][index];
2820 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2822 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2823 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2824 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2826 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2828 for (i = 0; i < MAX_TX_COUNT; i++) {
2829 rtlefuse->txpwr_cckdiff[rf_path][i] =
2830 pwrinfo24g.cck_diff[rf_path][i];
2831 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2832 pwrinfo24g.ofdm_diff[rf_path][i];
2833 rtlefuse->txpwr_ht20diff[rf_path][i] =
2834 pwrinfo24g.bw20_diff[rf_path][i];
2835 rtlefuse->txpwr_ht40diff[rf_path][i] =
2836 pwrinfo24g.bw40_diff[rf_path][i];
2838 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2839 pwrinfo5g.ofdm_diff[rf_path][i];
2840 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2841 pwrinfo5g.bw20_diff[rf_path][i];
2842 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2843 pwrinfo5g.bw40_diff[rf_path][i];
2844 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2845 pwrinfo5g.bw80_diff[rf_path][i];
2849 if (!autoload_fail) {
2850 rtlefuse->eeprom_regulatory =
2851 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2852 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2853 rtlefuse->eeprom_regulatory = 0;
2855 rtlefuse->eeprom_regulatory = 0;
2858 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2859 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2862 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2866 struct rtl_priv *rtlpriv = rtl_priv(hw);
2867 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2868 struct txpower_info_2g pwrinfo24g;
2869 struct txpower_info_5g pwrinfo5g;
2873 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2874 &pwrinfo5g, autoload_fail, hwinfo);
2876 for (rf_path = 0; rf_path < 2; rf_path++) {
2877 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2878 index = _rtl8821ae_get_chnl_group(i + 1);
2880 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2881 rtlefuse->txpwrlevel_cck[rf_path][i] =
2882 pwrinfo24g.index_cck_base[rf_path][5];
2883 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2884 pwrinfo24g.index_bw40_base[rf_path][index];
2886 rtlefuse->txpwrlevel_cck[rf_path][i] =
2887 pwrinfo24g.index_cck_base[rf_path][index];
2888 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2889 pwrinfo24g.index_bw40_base[rf_path][index];
2893 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2894 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2895 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2896 pwrinfo5g.index_bw40_base[rf_path][index];
2898 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2900 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2901 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2902 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2904 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2906 for (i = 0; i < MAX_TX_COUNT; i++) {
2907 rtlefuse->txpwr_cckdiff[rf_path][i] =
2908 pwrinfo24g.cck_diff[rf_path][i];
2909 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2910 pwrinfo24g.ofdm_diff[rf_path][i];
2911 rtlefuse->txpwr_ht20diff[rf_path][i] =
2912 pwrinfo24g.bw20_diff[rf_path][i];
2913 rtlefuse->txpwr_ht40diff[rf_path][i] =
2914 pwrinfo24g.bw40_diff[rf_path][i];
2916 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2917 pwrinfo5g.ofdm_diff[rf_path][i];
2918 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2919 pwrinfo5g.bw20_diff[rf_path][i];
2920 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2921 pwrinfo5g.bw40_diff[rf_path][i];
2922 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2923 pwrinfo5g.bw80_diff[rf_path][i];
2927 if (!autoload_fail) {
2928 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2929 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2930 rtlefuse->eeprom_regulatory = 0;
2932 rtlefuse->eeprom_regulatory = 0;
2935 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2936 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2939 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2942 struct rtl_priv *rtlpriv = rtl_priv(hw);
2943 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2945 if (!autoload_fail) {
2946 rtlhal->pa_type_2g = hwinfo[0xBC];
2947 rtlhal->lna_type_2g = hwinfo[0xBD];
2948 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2949 rtlhal->pa_type_2g = 0;
2950 rtlhal->lna_type_2g = 0;
2952 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2953 (rtlhal->pa_type_2g & BIT(4))) ?
2955 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2956 (rtlhal->lna_type_2g & BIT(3))) ?
2959 rtlhal->pa_type_5g = hwinfo[0xBC];
2960 rtlhal->lna_type_5g = hwinfo[0xBF];
2961 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2962 rtlhal->pa_type_5g = 0;
2963 rtlhal->lna_type_5g = 0;
2965 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2966 (rtlhal->pa_type_5g & BIT(0))) ?
2968 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2969 (rtlhal->lna_type_5g & BIT(3))) ?
2972 rtlhal->external_pa_2g = 0;
2973 rtlhal->external_lna_2g = 0;
2974 rtlhal->external_pa_5g = 0;
2975 rtlhal->external_lna_5g = 0;
2979 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2982 struct rtl_priv *rtlpriv = rtl_priv(hw);
2983 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2985 if (!autoload_fail) {
2986 rtlhal->pa_type_2g = hwinfo[0xBC];
2987 rtlhal->lna_type_2g = hwinfo[0xBD];
2988 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2989 rtlhal->pa_type_2g = 0;
2990 rtlhal->lna_type_2g = 0;
2992 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2993 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2995 rtlhal->pa_type_5g = hwinfo[0xBC];
2996 rtlhal->lna_type_5g = hwinfo[0xBF];
2997 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2998 rtlhal->pa_type_5g = 0;
2999 rtlhal->lna_type_5g = 0;
3001 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3002 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3004 rtlhal->external_pa_2g = 0;
3005 rtlhal->external_lna_2g = 0;
3006 rtlhal->external_pa_5g = 0;
3007 rtlhal->external_lna_5g = 0;
3011 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3014 struct rtl_priv *rtlpriv = rtl_priv(hw);
3015 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3017 if (!autoload_fail) {
3018 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3019 if (rtlhal->external_lna_5g) {
3020 if (rtlhal->external_pa_5g) {
3021 if (rtlhal->external_lna_2g &&
3022 rtlhal->external_pa_2g)
3023 rtlhal->rfe_type = 3;
3025 rtlhal->rfe_type = 0;
3027 rtlhal->rfe_type = 2;
3030 rtlhal->rfe_type = 4;
3033 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3035 if (rtlhal->rfe_type == 4 &&
3036 (rtlhal->external_pa_5g ||
3037 rtlhal->external_pa_2g ||
3038 rtlhal->external_lna_5g ||
3039 rtlhal->external_lna_2g)) {
3040 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3041 rtlhal->rfe_type = 2;
3045 rtlhal->rfe_type = 0x04;
3048 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3049 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3052 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3053 bool auto_load_fail, u8 *hwinfo)
3055 struct rtl_priv *rtlpriv = rtl_priv(hw);
3058 if (!auto_load_fail) {
3059 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3060 if (((value & 0xe0) >> 5) == 0x1)
3061 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3063 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3064 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3066 value = hwinfo[EEPROM_RF_BT_SETTING];
3067 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3069 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3070 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3071 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3073 /*move BT_InitHalVars() to init_sw_vars*/
3076 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3077 bool auto_load_fail, u8 *hwinfo)
3079 struct rtl_priv *rtlpriv = rtl_priv(hw);
3083 if (!auto_load_fail) {
3084 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3085 if (tmpu_32 & BIT(18))
3086 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3088 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3089 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3091 value = hwinfo[EEPROM_RF_BT_SETTING];
3092 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3094 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3095 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3096 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3098 /*move BT_InitHalVars() to init_sw_vars*/
3101 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3103 struct rtl_priv *rtlpriv = rtl_priv(hw);
3104 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3105 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3106 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3107 int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3108 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3109 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3110 COUNTRY_CODE_WORLD_WIDE_13};
3113 if (b_pseudo_test) {
3117 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3121 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3124 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3127 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3128 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3129 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3130 rtlefuse->autoload_failflag, hwinfo);
3132 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3133 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3134 rtlefuse->autoload_failflag, hwinfo);
3137 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3139 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3140 if (rtlhal->external_lna_2g != 0)
3141 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3142 if (rtlhal->external_lna_5g != 0)
3143 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3144 if (rtlhal->external_pa_2g != 0)
3145 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3146 if (rtlhal->external_pa_5g != 0)
3147 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3149 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3150 rtlefuse->board_type |= ODM_BOARD_BT;
3152 rtlhal->board_type = rtlefuse->board_type;
3153 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3154 "board_type = 0x%x\n", rtlefuse->board_type);
3156 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3157 if (rtlefuse->eeprom_channelplan == 0xff)
3158 rtlefuse->eeprom_channelplan = 0x7F;
3160 /* set channel plan from efuse */
3161 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3164 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3165 if (rtlefuse->crystalcap == 0xFF)
3166 rtlefuse->crystalcap = 0x20;
3168 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3169 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3170 rtlefuse->autoload_failflag) {
3171 rtlefuse->apk_thermalmeterignore = true;
3172 rtlefuse->eeprom_thermalmeter = 0xff;
3175 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3176 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3177 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3179 if (!rtlefuse->autoload_failflag) {
3180 rtlefuse->antenna_div_cfg =
3181 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3182 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3183 rtlefuse->antenna_div_cfg = 0;
3185 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3186 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3187 rtlefuse->antenna_div_cfg = 0;
3189 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3190 if (rtlefuse->antenna_div_type == 0xff)
3191 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3193 rtlefuse->antenna_div_cfg = 0;
3194 rtlefuse->antenna_div_type = 0;
3197 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3198 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3199 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3201 pcipriv->ledctl.led_opendrain = true;
3203 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3204 switch (rtlefuse->eeprom_oemid) {
3205 case RT_CID_DEFAULT:
3207 case EEPROM_CID_TOSHIBA:
3208 rtlhal->oem_id = RT_CID_TOSHIBA;
3210 case EEPROM_CID_CCX:
3211 rtlhal->oem_id = RT_CID_CCX;
3213 case EEPROM_CID_QMI:
3214 rtlhal->oem_id = RT_CID_819X_QMI;
3216 case EEPROM_CID_WHQL:
3226 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3228 struct rtl_priv *rtlpriv = rtl_priv(hw);
3229 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3230 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3232 pcipriv->ledctl.led_opendrain = true;
3233 switch (rtlhal->oem_id) {
3234 case RT_CID_819X_HP:
3235 pcipriv->ledctl.led_opendrain = true;
3237 case RT_CID_819X_LENOVO:
3238 case RT_CID_DEFAULT:
3239 case RT_CID_TOSHIBA:
3241 case RT_CID_819X_ACER:
3246 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3247 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3250 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3252 struct rtl_priv *rtlpriv = rtl_priv(hw);
3253 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3254 struct rtl_phy *rtlphy = &rtlpriv->phy;
3255 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3258 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3259 if (get_rf_type(rtlphy) == RF_1T1R)
3260 rtlpriv->dm.rfpath_rxenable[0] = true;
3262 rtlpriv->dm.rfpath_rxenable[0] =
3263 rtlpriv->dm.rfpath_rxenable[1] = true;
3264 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3267 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3268 if (tmp_u1b & BIT(4)) {
3269 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3270 rtlefuse->epromtype = EEPROM_93C46;
3272 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3273 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3276 if (tmp_u1b & BIT(5)) {
3277 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3278 rtlefuse->autoload_failflag = false;
3279 _rtl8821ae_read_adapter_info(hw, false);
3281 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3283 /*hal_ReadRFType_8812A()*/
3284 /* _rtl8821ae_hal_customized_behavior(hw); */
3287 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3288 struct ieee80211_sta *sta)
3290 struct rtl_priv *rtlpriv = rtl_priv(hw);
3291 struct rtl_phy *rtlphy = &rtlpriv->phy;
3292 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3293 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3296 u8 b_nmode = mac->ht_enable;
3297 u8 mimo_ps = IEEE80211_SMPS_OFF;
3300 u8 curtxbw_40mhz = mac->bw_40;
3301 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3303 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3305 enum wireless_mode wirelessmode = mac->mode;
3307 if (rtlhal->current_bandtype == BAND_ON_5G)
3308 ratr_value = sta->supp_rates[1] << 4;
3310 ratr_value = sta->supp_rates[0];
3311 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3313 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3314 sta->ht_cap.mcs.rx_mask[0] << 12);
3315 switch (wirelessmode) {
3316 case WIRELESS_MODE_B:
3317 if (ratr_value & 0x0000000c)
3318 ratr_value &= 0x0000000d;
3320 ratr_value &= 0x0000000f;
3322 case WIRELESS_MODE_G:
3323 ratr_value &= 0x00000FF5;
3325 case WIRELESS_MODE_N_24G:
3326 case WIRELESS_MODE_N_5G:
3328 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3329 ratr_value &= 0x0007F005;
3333 if (get_rf_type(rtlphy) == RF_1T2R ||
3334 get_rf_type(rtlphy) == RF_1T1R)
3335 ratr_mask = 0x000ff005;
3337 ratr_mask = 0x0f0ff005;
3339 ratr_value &= ratr_mask;
3343 if (rtlphy->rf_type == RF_1T2R)
3344 ratr_value &= 0x000ff0ff;
3346 ratr_value &= 0x0f0ff0ff;
3351 if ((rtlpriv->btcoexist.bt_coexistence) &&
3352 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3353 (rtlpriv->btcoexist.bt_cur_state) &&
3354 (rtlpriv->btcoexist.bt_ant_isolation) &&
3355 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3356 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3357 ratr_value &= 0x0fffcfc0;
3359 ratr_value &= 0x0FFFFFFF;
3361 if (b_nmode && ((curtxbw_40mhz &&
3362 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3363 b_curshortgi_20mhz))) {
3364 ratr_value |= 0x10000000;
3365 tmp_ratr_value = (ratr_value >> 12);
3367 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3368 if ((1 << shortgi_rate) & tmp_ratr_value)
3372 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3373 (shortgi_rate << 4) | (shortgi_rate);
3376 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3378 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3379 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3382 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3383 struct ieee80211_hw *hw, u8 rate_index,
3384 enum wireless_mode wirelessmode)
3386 struct rtl_priv *rtlpriv = rtl_priv(hw);
3387 struct rtl_phy *rtlphy = &rtlpriv->phy;
3389 switch (rate_index) {
3390 case RATR_INX_WIRELESS_NGB:
3391 if (rtlphy->rf_type == RF_1T1R)
3396 case RATR_INX_WIRELESS_N:
3397 case RATR_INX_WIRELESS_NG:
3398 if (rtlphy->rf_type == RF_1T1R)
3403 case RATR_INX_WIRELESS_NB:
3404 if (rtlphy->rf_type == RF_1T1R)
3409 case RATR_INX_WIRELESS_GB:
3412 case RATR_INX_WIRELESS_G:
3415 case RATR_INX_WIRELESS_B:
3418 case RATR_INX_WIRELESS_MC:
3419 if ((wirelessmode == WIRELESS_MODE_B)
3420 || (wirelessmode == WIRELESS_MODE_G)
3421 || (wirelessmode == WIRELESS_MODE_N_24G)
3422 || (wirelessmode == WIRELESS_MODE_AC_24G))
3426 case RATR_INX_WIRELESS_AC_5N:
3427 if (rtlphy->rf_type == RF_1T1R)
3432 case RATR_INX_WIRELESS_AC_24N:
3433 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3434 if (rtlphy->rf_type == RF_1T1R)
3439 if (rtlphy->rf_type == RF_1T1R)
3451 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3454 u32 rate_bitmap = 0;
3456 for (i = j = 0; i < 4; i += 2, j += 10) {
3457 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3461 rate_bitmap = rate_bitmap | (0x03ff << j);
3464 rate_bitmap = rate_bitmap | (0x01ff << j);
3467 rate_bitmap = rate_bitmap | (0x00ff << j);
3477 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3478 enum wireless_mode wirelessmode,
3481 struct rtl_priv *rtlpriv = rtl_priv(hw);
3482 struct rtl_phy *rtlphy = &rtlpriv->phy;
3483 u32 ret_bitmap = ratr_bitmap;
3485 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3486 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3487 ret_bitmap = ratr_bitmap;
3488 else if (wirelessmode == WIRELESS_MODE_AC_5G
3489 || wirelessmode == WIRELESS_MODE_AC_24G) {
3490 if (rtlphy->rf_type == RF_1T1R)
3491 ret_bitmap = ratr_bitmap & (~BIT21);
3493 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3499 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3503 if (wirelessmode < WIRELESS_MODE_N_24G)
3505 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3506 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3510 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3517 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3518 u8 mac_id, struct rtl_sta_info *sta_entry,
3519 enum wireless_mode wirelessmode)
3522 /*not support ldpc, do not open*/
3526 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3527 enum wireless_mode wirelessmode,
3530 struct rtl_priv *rtlpriv = rtl_priv(hw);
3531 struct rtl_phy *rtlphy = &rtlpriv->phy;
3532 u8 rf_type = RF_1T1R;
3534 if (rtlphy->rf_type == RF_1T1R)
3536 else if (wirelessmode == WIRELESS_MODE_AC_5G
3537 || wirelessmode == WIRELESS_MODE_AC_24G
3538 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3539 if (ratr_bitmap & 0xffc00000)
3541 } else if (wirelessmode == WIRELESS_MODE_N_5G
3542 || wirelessmode == WIRELESS_MODE_N_24G) {
3543 if (ratr_bitmap & 0xfff00000)
3550 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3553 bool b_short_gi = false;
3554 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3556 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3558 u8 b_curshortgi_80mhz = 0;
3559 b_curshortgi_80mhz = (sta->vht_cap.cap &
3560 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3562 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3565 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3566 || b_curshortgi_20mhz)
3572 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3573 struct ieee80211_sta *sta, u8 rssi_level)
3575 struct rtl_priv *rtlpriv = rtl_priv(hw);
3576 struct rtl_phy *rtlphy = &rtlpriv->phy;
3577 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3578 struct rtl_sta_info *sta_entry = NULL;
3581 enum wireless_mode wirelessmode = 0;
3582 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3584 bool b_shortgi = false;
3587 u8 mimo_ps = IEEE80211_SMPS_OFF;
3590 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3591 wirelessmode = sta_entry->wireless_mode;
3593 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3594 "wireless mode = 0x%x\n", wirelessmode);
3595 if (mac->opmode == NL80211_IFTYPE_STATION ||
3596 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3597 curtxbw_40mhz = mac->bw_40;
3598 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3599 mac->opmode == NL80211_IFTYPE_ADHOC)
3600 macid = sta->aid + 1;
3601 if (wirelessmode == WIRELESS_MODE_N_5G ||
3602 wirelessmode == WIRELESS_MODE_AC_5G ||
3603 wirelessmode == WIRELESS_MODE_A)
3604 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3606 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3608 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3609 ratr_bitmap = 0xfff;
3611 if (wirelessmode == WIRELESS_MODE_N_24G
3612 || wirelessmode == WIRELESS_MODE_N_5G)
3613 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3614 sta->ht_cap.mcs.rx_mask[0] << 12);
3615 else if (wirelessmode == WIRELESS_MODE_AC_24G
3616 || wirelessmode == WIRELESS_MODE_AC_5G
3617 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3618 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3619 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3621 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3622 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3625 switch (wirelessmode) {
3626 case WIRELESS_MODE_B:
3627 ratr_index = RATR_INX_WIRELESS_B;
3628 if (ratr_bitmap & 0x0000000c)
3629 ratr_bitmap &= 0x0000000d;
3631 ratr_bitmap &= 0x0000000f;
3633 case WIRELESS_MODE_G:
3634 ratr_index = RATR_INX_WIRELESS_GB;
3636 if (rssi_level == 1)
3637 ratr_bitmap &= 0x00000f00;
3638 else if (rssi_level == 2)
3639 ratr_bitmap &= 0x00000ff0;
3641 ratr_bitmap &= 0x00000ff5;
3643 case WIRELESS_MODE_A:
3644 ratr_index = RATR_INX_WIRELESS_G;
3645 ratr_bitmap &= 0x00000ff0;
3647 case WIRELESS_MODE_N_24G:
3648 case WIRELESS_MODE_N_5G:
3649 if (wirelessmode == WIRELESS_MODE_N_24G)
3650 ratr_index = RATR_INX_WIRELESS_NGB;
3652 ratr_index = RATR_INX_WIRELESS_NG;
3654 if (mimo_ps == IEEE80211_SMPS_STATIC
3655 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3656 if (rssi_level == 1)
3657 ratr_bitmap &= 0x000f0000;
3658 else if (rssi_level == 2)
3659 ratr_bitmap &= 0x000ff000;
3661 ratr_bitmap &= 0x000ff005;
3663 if (rf_type == RF_1T1R) {
3664 if (curtxbw_40mhz) {
3665 if (rssi_level == 1)
3666 ratr_bitmap &= 0x000f0000;
3667 else if (rssi_level == 2)
3668 ratr_bitmap &= 0x000ff000;
3670 ratr_bitmap &= 0x000ff015;
3672 if (rssi_level == 1)
3673 ratr_bitmap &= 0x000f0000;
3674 else if (rssi_level == 2)
3675 ratr_bitmap &= 0x000ff000;
3677 ratr_bitmap &= 0x000ff005;
3680 if (curtxbw_40mhz) {
3681 if (rssi_level == 1)
3682 ratr_bitmap &= 0x0fff0000;
3683 else if (rssi_level == 2)
3684 ratr_bitmap &= 0x0ffff000;
3686 ratr_bitmap &= 0x0ffff015;
3688 if (rssi_level == 1)
3689 ratr_bitmap &= 0x0fff0000;
3690 else if (rssi_level == 2)
3691 ratr_bitmap &= 0x0ffff000;
3693 ratr_bitmap &= 0x0ffff005;
3699 case WIRELESS_MODE_AC_24G:
3700 ratr_index = RATR_INX_WIRELESS_AC_24N;
3701 if (rssi_level == 1)
3702 ratr_bitmap &= 0xfc3f0000;
3703 else if (rssi_level == 2)
3704 ratr_bitmap &= 0xfffff000;
3706 ratr_bitmap &= 0xffffffff;
3709 case WIRELESS_MODE_AC_5G:
3710 ratr_index = RATR_INX_WIRELESS_AC_5N;
3712 if (rf_type == RF_1T1R) {
3713 if (rssi_level == 1) /*add by Gary for ac-series*/
3714 ratr_bitmap &= 0x003f8000;
3715 else if (rssi_level == 2)
3716 ratr_bitmap &= 0x003ff000;
3718 ratr_bitmap &= 0x003ff010;
3720 if (rssi_level == 1)
3721 ratr_bitmap &= 0xfe3f8000;
3722 else if (rssi_level == 2)
3723 ratr_bitmap &= 0xfffff000;
3725 ratr_bitmap &= 0xfffff010;
3730 ratr_index = RATR_INX_WIRELESS_NGB;
3732 if (rf_type == RF_1T2R)
3733 ratr_bitmap &= 0x000ff0ff;
3735 ratr_bitmap &= 0x0f8ff0ff;
3739 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3740 sta_entry->ratr_index = ratr_index;
3741 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3744 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3745 "ratr_bitmap :%x\n", ratr_bitmap);
3747 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3748 (ratr_index << 28)); */
3750 rate_mask[0] = macid;
3751 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3752 rate_mask[2] = rtlphy->current_chan_bw
3753 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3754 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3756 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3757 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3758 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3759 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3761 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3762 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3763 ratr_index, ratr_bitmap,
3764 rate_mask[0], rate_mask[1],
3765 rate_mask[2], rate_mask[3],
3766 rate_mask[4], rate_mask[5],
3768 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3769 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3772 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3773 struct ieee80211_sta *sta, u8 rssi_level)
3775 struct rtl_priv *rtlpriv = rtl_priv(hw);
3776 if (rtlpriv->dm.useramask)
3777 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3779 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3780 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3781 rtl8821ae_update_hal_rate_table(hw, sta);
3784 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3786 struct rtl_priv *rtlpriv = rtl_priv(hw);
3787 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3788 u16 wireless_mode = mac->mode;
3789 u8 sifs_timer, r2t_sifs;
3791 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3792 (u8 *)&mac->slot_time);
3793 if (wireless_mode == WIRELESS_MODE_G)
3797 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3801 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3802 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3803 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3804 if (mac->vendor == PEER_ATH)
3808 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3812 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3815 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3817 struct rtl_priv *rtlpriv = rtl_priv(hw);
3818 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3819 struct rtl_phy *rtlphy = &rtlpriv->phy;
3820 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3822 bool b_actuallyset = false;
3824 if (rtlpriv->rtlhal.being_init_adapter)
3827 if (ppsc->swrf_processing)
3830 spin_lock(&rtlpriv->locks.rf_ps_lock);
3831 if (ppsc->rfchange_inprogress) {
3832 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3835 ppsc->rfchange_inprogress = true;
3836 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3839 cur_rfstate = ppsc->rfpwr_state;
3841 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3842 rtl_read_byte(rtlpriv,
3843 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3845 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3847 if (rtlphy->polarity_ctl)
3848 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3850 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3852 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3853 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3854 "GPIOChangeRF - HW Radio ON, RF ON\n");
3856 e_rfpowerstate_toset = ERFON;
3857 ppsc->hwradiooff = false;
3858 b_actuallyset = true;
3859 } else if ((!ppsc->hwradiooff)
3860 && (e_rfpowerstate_toset == ERFOFF)) {
3861 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3862 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3864 e_rfpowerstate_toset = ERFOFF;
3865 ppsc->hwradiooff = true;
3866 b_actuallyset = true;
3869 if (b_actuallyset) {
3870 spin_lock(&rtlpriv->locks.rf_ps_lock);
3871 ppsc->rfchange_inprogress = false;
3872 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3874 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3875 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3877 spin_lock(&rtlpriv->locks.rf_ps_lock);
3878 ppsc->rfchange_inprogress = false;
3879 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3883 return !ppsc->hwradiooff;
3886 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3887 u8 *p_macaddr, bool is_group, u8 enc_algo,
3888 bool is_wepkey, bool clear_all)
3890 struct rtl_priv *rtlpriv = rtl_priv(hw);
3891 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3892 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3893 u8 *macaddr = p_macaddr;
3895 bool is_pairwise = false;
3897 static u8 cam_const_addr[4][6] = {
3898 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3899 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3900 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3901 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3903 static u8 cam_const_broad[] = {
3904 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3910 u8 clear_number = 5;
3912 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3914 for (idx = 0; idx < clear_number; idx++) {
3915 rtl_cam_mark_invalid(hw, cam_offset + idx);
3916 rtl_cam_empty_entry(hw, cam_offset + idx);
3919 memset(rtlpriv->sec.key_buf[idx], 0,
3921 rtlpriv->sec.key_len[idx] = 0;
3926 case WEP40_ENCRYPTION:
3927 enc_algo = CAM_WEP40;
3929 case WEP104_ENCRYPTION:
3930 enc_algo = CAM_WEP104;
3932 case TKIP_ENCRYPTION:
3933 enc_algo = CAM_TKIP;
3935 case AESCCMP_ENCRYPTION:
3939 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3940 "switch case %#x not processed\n", enc_algo);
3941 enc_algo = CAM_TKIP;
3945 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3946 macaddr = cam_const_addr[key_index];
3947 entry_id = key_index;
3950 macaddr = cam_const_broad;
3951 entry_id = key_index;
3953 if (mac->opmode == NL80211_IFTYPE_AP) {
3954 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3955 if (entry_id >= TOTAL_CAM_ENTRY) {
3956 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
3957 "Can not find free hwsecurity cam entry\n");
3961 entry_id = CAM_PAIRWISE_KEY_POSITION;
3964 key_index = PAIRWISE_KEYIDX;
3969 if (rtlpriv->sec.key_len[key_index] == 0) {
3970 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3971 "delete one entry, entry_id is %d\n",
3973 if (mac->opmode == NL80211_IFTYPE_AP)
3974 rtl_cam_del_entry(hw, p_macaddr);
3975 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3977 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3980 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3981 "set Pairwise key\n");
3983 rtl_cam_add_one_entry(hw, macaddr, key_index,
3985 CAM_CONFIG_NO_USEDK,
3986 rtlpriv->sec.key_buf[key_index]);
3988 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3991 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3992 rtl_cam_add_one_entry(hw,
3995 CAM_PAIRWISE_KEY_POSITION,
3997 CAM_CONFIG_NO_USEDK,
3998 rtlpriv->sec.key_buf
4002 rtl_cam_add_one_entry(hw, macaddr, key_index,
4004 CAM_CONFIG_NO_USEDK,
4005 rtlpriv->sec.key_buf[entry_id]);
4011 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4013 struct rtl_priv *rtlpriv = rtl_priv(hw);
4015 /* 0:Low, 1:High, 2:From Efuse. */
4016 rtlpriv->btcoexist.reg_bt_iso = 2;
4017 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4018 rtlpriv->btcoexist.reg_bt_sco = 3;
4019 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4020 rtlpriv->btcoexist.reg_bt_sco = 0;
4023 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4025 struct rtl_priv *rtlpriv = rtl_priv(hw);
4027 if (rtlpriv->cfg->ops->get_btc_status())
4028 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4031 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4035 void rtl8821ae_resume(struct ieee80211_hw *hw)
4039 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4040 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4041 bool allow_all_da, bool write_into_reg)
4043 struct rtl_priv *rtlpriv = rtl_priv(hw);
4044 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4046 if (allow_all_da) /* Set BIT0 */
4047 rtlpci->receive_config |= RCR_AAP;
4048 else /* Clear BIT0 */
4049 rtlpci->receive_config &= ~RCR_AAP;
4052 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4054 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4055 "receive_config=0x%08X, write_into_reg=%d\n",
4056 rtlpci->receive_config, write_into_reg);
4059 /* WKFMCAMAddAllEntry8812 */
4060 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4061 struct rtl_wow_pattern *rtl_pattern,
4064 struct rtl_priv *rtlpriv = rtl_priv(hw);
4072 /* Count the WFCAM entry start offset. */
4074 /* RX page size = 128 byte */
4075 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4076 /* We should start from the boundry */
4077 cam_start = offset * 128;
4079 /* Enable Rx packet buffer access. */
4080 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4081 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4082 /* Set Rx packet buffer offset.
4083 * RxBufer pointer increases 1,
4084 * we can access 8 bytes in Rx packet buffer.
4085 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
4086 * RxBufer addr = (CAM start offset +
4087 * per entry offset of a WKFM CAM)/8
4088 * * index: The index of the wake up frame mask
4089 * * WKFMCAM_SIZE: the total size of one WKFM CAM
4090 * * per entry offset of a WKFM CAM: Addr*4 bytes
4092 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4093 /* Set R/W start offset */
4094 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4097 cam = BIT(31) | rtl_pattern->crc;
4099 if (rtl_pattern->type == UNICAST_PATTERN)
4101 else if (rtl_pattern->type == MULTICAST_PATTERN)
4103 else if (rtl_pattern->type == BROADCAST_PATTERN)
4106 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4107 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4108 "WRITE entry[%d] 0x%x: %x\n", addr,
4109 REG_PKTBUF_DBG_DATA_L, cam);
4111 /* Write to Rx packet buffer. */
4112 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4113 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4114 cam = rtl_pattern->mask[addr - 2];
4116 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4117 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4118 "WRITE entry[%d] 0x%x: %x\n", addr,
4119 REG_PKTBUF_DBG_DATA_L, cam);
4121 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4122 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4123 cam = rtl_pattern->mask[addr - 2];
4125 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4126 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4127 "WRITE entry[%d] 0x%x: %x\n", addr,
4128 REG_PKTBUF_DBG_DATA_H, cam);
4130 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4135 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4138 } while (tmp && count < 100);
4140 RT_ASSERT((count < 100),
4141 "Write wake up frame mask FAIL %d value!\n", tmp);
4143 /* Disable Rx packet buffer access. */
4144 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4145 DISABLE_TRXPKT_BUF_ACCESS);