drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42 #include "../btcoexist/rtl_btc.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  51         unsigned long flags;
  52
  53         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  54         while (skb_queue_len(&ring->queue)) {
  55                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  56                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  57
  58                 pci_unmap_single(rtlpci->pdev,
  59                                  rtlpriv->cfg->ops->get_desc(
  60                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  61                                  skb->len, PCI_DMA_TODEVICE);
  62                 kfree_skb(skb);
  63                 ring->idx = (ring->idx + 1) % ring->entries;
  64         }
  65         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  66 }
  67
  68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                         u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76
  77         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  78 }
  79
  80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
  81 {
  82         struct rtl_priv *rtlpriv = rtl_priv(hw);
  83         u8 tmp1byte;
  84
  85         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  86         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 102         tmp1byte |= BIT(0);
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 104 }
 105
 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
 107 {
 108         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
 109 }
 110
 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
 112 {
 113         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
 114 }
 115
 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
 117                                        u8 rpwm_val, bool b_need_turn_off_ckk)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 121         bool b_support_remote_wake_up;
 122         u32 count = 0, isr_regaddr, content;
 123         bool b_schedule_timer = b_need_turn_off_ckk;
 124
 125         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 126                                         (u8 *)(&b_support_remote_wake_up));
 127
 128         if (!rtlhal->fw_ready)
 129                 return;
 130         if (!rtlpriv->psc.fw_current_inpsmode)
 131                 return;
 132
 133         while (1) {
 134                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 135                 if (rtlhal->fw_clk_change_in_progress) {
 136                         while (rtlhal->fw_clk_change_in_progress) {
 137                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 138                                 count++;
 139                                 udelay(100);
 140                                 if (count > 1000)
 141                                         goto change_done;
 142                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 143                         }
 144                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 145                 } else {
 146                         rtlhal->fw_clk_change_in_progress = false;
 147                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 148                         goto change_done;
 149                 }
 150         }
 151 change_done:
 152         if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
 153                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 154                                         (u8 *)(&rpwm_val));
 155                 if (FW_PS_IS_ACK(rpwm_val)) {
 156                         isr_regaddr = REG_HISR;
 157                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         while (!(content & IMR_CPWM) && (count < 500)) {
 159                                 udelay(50);
 160                                 count++;
 161                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 162                         }
 163
 164                         if (content & IMR_CPWM) {
 165                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 166                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
 167                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 168                                          "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
 169                                          rtlhal->fw_ps_state);
 170                         }
 171                 }
 172
 173                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 174                 rtlhal->fw_clk_change_in_progress = false;
 175                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 if (b_schedule_timer)
 177                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 178                                   jiffies + MSECS(10));
 179         } else  {
 180                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 181                 rtlhal->fw_clk_change_in_progress = false;
 182                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 183         }
 184 }
 185
 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
 187                                         u8 rpwm_val)
 188 {
 189         struct rtl_priv *rtlpriv = rtl_priv(hw);
 190         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 192         struct rtl8192_tx_ring *ring;
 193         enum rf_pwrstate rtstate;
 194         bool b_schedule_timer = false;
 195         u8 queue;
 196
 197         if (!rtlhal->fw_ready)
 198                 return;
 199         if (!rtlpriv->psc.fw_current_inpsmode)
 200                 return;
 201         if (!rtlhal->allow_sw_to_change_hwclc)
 202                 return;
 203         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         b_schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (b_schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 222                 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240 }
 241
 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 243 {
 244         u8 rpwm_val = 0;
 245
 246         rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
 247         _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
 260                 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                 (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                 (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON_8821AE;   /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                 (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                 (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                 (u8 *)(&fw_current_inps));
 274         }
 275 }
 276
 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
 278 {
 279         struct rtl_priv *rtlpriv = rtl_priv(hw);
 280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 281         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 282         bool fw_current_inps = true;
 283         u8 rpwm_val;
 284
 285         if (ppsc->low_power_enable) {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;   /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw,
 288                                 HW_VAR_FW_PSMODE_STATUS,
 289                                 (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw,
 291                                 HW_VAR_H2C_FW_PWRMODE,
 292                                 (u8 *)(&ppsc->fwctrl_psmode));
 293                 rtlhal->allow_sw_to_change_hwclc = true;
 294                 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
 295         } else {
 296                 rpwm_val = FW_PS_STATE_RF_OFF_8821AE;   /* RF off */
 297                 rtlpriv->cfg->ops->set_hw_reg(hw,
 298                                 HW_VAR_FW_PSMODE_STATUS,
 299                                 (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw,
 301                                 HW_VAR_H2C_FW_PWRMODE,
 302                                 (u8 *)(&ppsc->fwctrl_psmode));
 303                 rtlpriv->cfg->ops->set_hw_reg(hw,
 304                                 HW_VAR_SET_RPWM,
 305                                 (u8 *)(&rpwm_val));
 306         }
 307 }
 308
 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
 310                                           bool dl_whole_packets)
 311 {
 312         struct rtl_priv *rtlpriv = rtl_priv(hw);
 313         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 314         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 315         u8 count = 0, dlbcn_count = 0;
 316         bool send_beacon = false;
 317
 318         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 319         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
 320
 321         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 322         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
 323
 324         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 325         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 326                        tmp_reg422 & (~BIT(6)));
 327         if (tmp_reg422 & BIT(6))
 328                 send_beacon = true;
 329
 330         do {
 331                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 332                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 333                                (bcnvalid_reg | BIT(0)));
 334                 _rtl8821ae_return_beacon_queue_skb(hw);
 335
 336                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 337                         rtl8812ae_set_fw_rsvdpagepkt(hw, false,
 338                                                      dl_whole_packets);
 339                 else
 340                         rtl8821ae_set_fw_rsvdpagepkt(hw, false,
 341                                                      dl_whole_packets);
 342
 343                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 344                 count = 0;
 345                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 346                         count++;
 347                         udelay(10);
 348                         bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 349                 }
 350                 dlbcn_count++;
 351         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 352
 353         if (!(bcnvalid_reg & BIT(0)))
 354                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 355                          "Download RSVD page failed!\n");
 356         if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
 357                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
 358                 _rtl8821ae_return_beacon_queue_skb(hw);
 359                 if (send_beacon) {
 360                         dlbcn_count = 0;
 361                         do {
 362                                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 363                                                bcnvalid_reg | BIT(0));
 364
 365                                 _rtl8821ae_return_beacon_queue_skb(hw);
 366
 367                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 368                                         rtl8812ae_set_fw_rsvdpagepkt(hw, true,
 369                                                                      false);
 370                                 else
 371                                         rtl8821ae_set_fw_rsvdpagepkt(hw, true,
 372                                                                      false);
 373
 374                                 /* check rsvd page download OK. */
 375                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 376                                                              REG_TDECTRL + 2);
 377                                 count = 0;
 378                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 379                                         count++;
 380                                         udelay(10);
 381                                         bcnvalid_reg =
 382                                           rtl_read_byte(rtlpriv,
 383                                                         REG_TDECTRL + 2);
 384                                 }
 385                                 dlbcn_count++;
 386                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 387
 388                         if (!(bcnvalid_reg & BIT(0)))
 389                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 390                                          "2 Download RSVD page failed!\n");
 391                 }
 392         }
 393
 394         if (bcnvalid_reg & BIT(0))
 395                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 396
 397         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 398         _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
 399
 400         if (send_beacon)
 401                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 402
 403         if (!rtlhal->enter_pnp_sleep) {
 404                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 405                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 406         }
 407 }
 408
 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 410 {
 411         struct rtl_priv *rtlpriv = rtl_priv(hw);
 412         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415
 416         switch (variable) {
 417         case HW_VAR_ETHER_ADDR:
 418                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
 419                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
 420                 break;
 421         case HW_VAR_BSSID:
 422                 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
 423                 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
 424                 break;
 425         case HW_VAR_MEDIA_STATUS:
 426                 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
 427                 break;
 428         case HW_VAR_SLOT_TIME:
 429                 *((u8 *)(val)) = mac->slot_time;
 430                 break;
 431         case HW_VAR_BEACON_INTERVAL:
 432                 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
 433                 break;
 434         case HW_VAR_ATIM_WINDOW:
 435                 *((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
 436                 break;
 437         case HW_VAR_RCR:
 438                 *((u32 *)(val)) = rtlpci->receive_config;
 439                 break;
 440         case HW_VAR_RF_STATE:
 441                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 442                 break;
 443         case HW_VAR_FWLPS_RF_ON:{
 444                 enum rf_pwrstate rfstate;
 445                 u32 val_rcr;
 446
 447                 rtlpriv->cfg->ops->get_hw_reg(hw,
 448                                               HW_VAR_RF_STATE,
 449                                               (u8 *)(&rfstate));
 450                 if (rfstate == ERFOFF) {
 451                         *((bool *)(val)) = true;
 452                 } else {
 453                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 454                         val_rcr &= 0x00070000;
 455                         if (val_rcr)
 456                                 *((bool *)(val)) = false;
 457                         else
 458                                 *((bool *)(val)) = true;
 459                 }
 460                 break; }
 461         case HW_VAR_FW_PSMODE_STATUS:
 462                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 463                 break;
 464         case HW_VAR_CORRECT_TSF:{
 465                 u64 tsf;
 466                 u32 *ptsf_low = (u32 *)&tsf;
 467                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 468
 469                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 470                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 471
 472                 *((u64 *)(val)) = tsf;
 473
 474                 break; }
 475         case HAL_DEF_WOWLAN:
 476                 if (ppsc->wo_wlan_mode)
 477                         *((bool *)(val)) = true;
 478                 else
 479                         *((bool *)(val)) = false;
 480                 break;
 481         default:
 482                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 483                          "switch case %#x not processed\n", variable);
 484                 break;
 485         }
 486 }
 487
 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 493         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 494         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 495         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 496         u8 idx;
 497
 498         switch (variable) {
 499         case HW_VAR_ETHER_ADDR:{
 500                         for (idx = 0; idx < ETH_ALEN; idx++) {
 501                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 502                                                val[idx]);
 503                         }
 504                         break;
 505                 }
 506         case HW_VAR_BASIC_RATE:{
 507                         u16 b_rate_cfg = ((u16 *)val)[0];
 508                         b_rate_cfg = b_rate_cfg & 0x15f;
 509                         rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
 510                         break;
 511                 }
 512         case HW_VAR_BSSID:{
 513                         for (idx = 0; idx < ETH_ALEN; idx++) {
 514                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 515                                                val[idx]);
 516                         }
 517                         break;
 518                 }
 519         case HW_VAR_SIFS:
 520                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 521                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
 522
 523                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 524                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 525
 526                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 527                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
 528                 break;
 529         case HW_VAR_R2T_SIFS:
 530                 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
 531                 break;
 532         case HW_VAR_SLOT_TIME:{
 533                 u8 e_aci;
 534
 535                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 536                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 537
 538                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 539
 540                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 541                         rtlpriv->cfg->ops->set_hw_reg(hw,
 542                                                       HW_VAR_AC_PARAM,
 543                                                       (u8 *)(&e_aci));
 544                 }
 545                 break; }
 546         case HW_VAR_ACK_PREAMBLE:{
 547                 u8 reg_tmp;
 548                 u8 short_preamble = (bool)(*(u8 *)val);
 549
 550                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 551                 if (short_preamble) {
 552                         reg_tmp |= BIT(1);
 553                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
 554                                        reg_tmp);
 555                 } else {
 556                         reg_tmp &= (~BIT(1));
 557                         rtl_write_byte(rtlpriv,
 558                                 REG_TRXPTCL_CTL + 2,
 559                                 reg_tmp);
 560                 }
 561                 break; }
 562         case HW_VAR_WPA_CONFIG:
 563                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 564                 break;
 565         case HW_VAR_AMPDU_MIN_SPACE:{
 566                 u8 min_spacing_to_set;
 567                 u8 sec_min_space;
 568
 569                 min_spacing_to_set = *((u8 *)val);
 570                 if (min_spacing_to_set <= 7) {
 571                         sec_min_space = 0;
 572
 573                         if (min_spacing_to_set < sec_min_space)
 574                                 min_spacing_to_set = sec_min_space;
 575
 576                         mac->min_space_cfg = ((mac->min_space_cfg &
 577                                                0xf8) |
 578                                               min_spacing_to_set);
 579
 580                         *val = min_spacing_to_set;
 581
 582                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 583                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 584                                   mac->min_space_cfg);
 585
 586                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 587                                        mac->min_space_cfg);
 588                 }
 589                 break; }
 590         case HW_VAR_SHORTGI_DENSITY:{
 591                 u8 density_to_set;
 592
 593                 density_to_set = *((u8 *)val);
 594                 mac->min_space_cfg |= (density_to_set << 3);
 595
 596                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 597                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 598                           mac->min_space_cfg);
 599
 600                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 601                                mac->min_space_cfg);
 602
 603                 break; }
 604         case HW_VAR_AMPDU_FACTOR:{
 605                 u32     ampdu_len =  (*((u8 *)val));
 606
 607                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 608                         if (ampdu_len < VHT_AGG_SIZE_128K)
 609                                 ampdu_len =
 610                                         (0x2000 << (*((u8 *)val))) - 1;
 611                         else
 612                                 ampdu_len = 0x1ffff;
 613                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 614                         if (ampdu_len < HT_AGG_SIZE_64K)
 615                                 ampdu_len =
 616                                         (0x2000 << (*((u8 *)val))) - 1;
 617                         else
 618                                 ampdu_len = 0xffff;
 619                 }
 620                 ampdu_len |= BIT(31);
 621
 622                 rtl_write_dword(rtlpriv,
 623                         REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
 624                 break; }
 625         case HW_VAR_AC_PARAM:{
 626                 u8 e_aci = *((u8 *)val);
 627
 628                 rtl8821ae_dm_init_edca_turbo(hw);
 629                 if (rtlpci->acm_method != EACMWAY2_SW)
 630                         rtlpriv->cfg->ops->set_hw_reg(hw,
 631                                                       HW_VAR_ACM_CTRL,
 632                                                       (u8 *)(&e_aci));
 633                 break; }
 634         case HW_VAR_ACM_CTRL:{
 635                 u8 e_aci = *((u8 *)val);
 636                 union aci_aifsn *p_aci_aifsn =
 637                     (union aci_aifsn *)(&mac->ac[0].aifs);
 638                 u8 acm = p_aci_aifsn->f.acm;
 639                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 640
 641                 acm_ctrl =
 642                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 643
 644                 if (acm) {
 645                         switch (e_aci) {
 646                         case AC0_BE:
 647                                 acm_ctrl |= ACMHW_BEQEN;
 648                                 break;
 649                         case AC2_VI:
 650                                 acm_ctrl |= ACMHW_VIQEN;
 651                                 break;
 652                         case AC3_VO:
 653                                 acm_ctrl |= ACMHW_VOQEN;
 654                                 break;
 655                         default:
 656                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 657                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 658                                          acm);
 659                                 break;
 660                         }
 661                 } else {
 662                         switch (e_aci) {
 663                         case AC0_BE:
 664                                 acm_ctrl &= (~ACMHW_BEQEN);
 665                                 break;
 666                         case AC2_VI:
 667                                 acm_ctrl &= (~ACMHW_VIQEN);
 668                                 break;
 669                         case AC3_VO:
 670                                 acm_ctrl &= (~ACMHW_VOQEN);
 671                                 break;
 672                         default:
 673                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 674                                          "switch case %#x not processed\n",
 675                                          e_aci);
 676                                 break;
 677                         }
 678                 }
 679
 680                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 681                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 682                          acm_ctrl);
 683                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 684                 break; }
 685         case HW_VAR_RCR:
 686                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 687                 rtlpci->receive_config = ((u32 *)(val))[0];
 688                 break;
 689         case HW_VAR_RETRY_LIMIT:{
 690                 u8 retry_limit = ((u8 *)(val))[0];
 691
 692                 rtl_write_word(rtlpriv, REG_RL,
 693                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 694                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 695                 break; }
 696         case HW_VAR_DUAL_TSF_RST:
 697                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 698                 break;
 699         case HW_VAR_EFUSE_BYTES:
 700                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 701                 break;
 702         case HW_VAR_EFUSE_USAGE:
 703                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 704                 break;
 705         case HW_VAR_IO_CMD:
 706                 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
 707                 break;
 708         case HW_VAR_SET_RPWM:{
 709                 u8 rpwm_val;
 710
 711                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 712                 udelay(1);
 713
 714                 if (rpwm_val & BIT(7)) {
 715                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 716                                        (*(u8 *)val));
 717                 } else {
 718                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 719                                        ((*(u8 *)val) | BIT(7)));
 720                 }
 721
 722                 break; }
 723         case HW_VAR_H2C_FW_PWRMODE:
 724                 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 725                 break;
 726         case HW_VAR_FW_PSMODE_STATUS:
 727                 ppsc->fw_current_inpsmode = *((bool *)val);
 728                 break;
 729         case HW_VAR_INIT_RTS_RATE:
 730                 break;
 731         case HW_VAR_RESUME_CLK_ON:
 732                 _rtl8821ae_set_fw_ps_rf_on(hw);
 733                 break;
 734         case HW_VAR_FW_LPS_ACTION:{
 735                 bool b_enter_fwlps = *((bool *)val);
 736
 737                 if (b_enter_fwlps)
 738                         _rtl8821ae_fwlps_enter(hw);
 739                  else
 740                         _rtl8821ae_fwlps_leave(hw);
 741                  break; }
 742         case HW_VAR_H2C_FW_JOINBSSRPT:{
 743                 u8 mstatus = (*(u8 *)val);
 744
 745                 if (mstatus == RT_MEDIA_CONNECT) {
 746                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 747                                                       NULL);
 748                         _rtl8821ae_download_rsvd_page(hw, false);
 749                 }
 750                 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
 751
 752                 break; }
 753         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 754                 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 755                 break;
 756         case HW_VAR_AID:{
 757                 u16 u2btmp;
 758                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 759                 u2btmp &= 0xC000;
 760                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 761                                mac->assoc_id));
 762                 break; }
 763         case HW_VAR_CORRECT_TSF:{
 764                 u8 btype_ibss = ((u8 *)(val))[0];
 765
 766                 if (btype_ibss)
 767                         _rtl8821ae_stop_tx_beacon(hw);
 768
 769                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
 770
 771                 rtl_write_dword(rtlpriv, REG_TSFTR,
 772                                 (u32)(mac->tsf & 0xffffffff));
 773                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 774                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 775
 776                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
 777
 778                 if (btype_ibss)
 779                         _rtl8821ae_resume_tx_beacon(hw);
 780                 break; }
 781         case HW_VAR_NAV_UPPER: {
 782                 u32     us_nav_upper = ((u32)*val);
 783
 784                 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
 785                         RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
 786                                  "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
 787                                  us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
 788                         break;
 789                 }
 790                 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
 791                                ((u8)((us_nav_upper +
 792                                 HAL_92C_NAV_UPPER_UNIT - 1) /
 793                                 HAL_92C_NAV_UPPER_UNIT)));
 794                 break; }
 795         case HW_VAR_KEEP_ALIVE: {
 796                 u8 array[2];
 797                 array[0] = 0xff;
 798                 array[1] = *((u8 *)val);
 799                 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
 800                                        array);
 801                 break; }
 802         default:
 803                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 804                          "switch case %#x not processed\n", variable);
 805                 break;
 806         }
 807 }
 808
 809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 810 {
 811         struct rtl_priv *rtlpriv = rtl_priv(hw);
 812         bool status = true;
 813         long count = 0;
 814         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 815                     _LLT_OP(_LLT_WRITE_ACCESS);
 816
 817         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 818
 819         do {
 820                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 821                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 822                         break;
 823
 824                 if (count > POLLING_LLT_THRESHOLD) {
 825                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 826                                  "Failed to polling write LLT done at address %d!\n",
 827                                  address);
 828                         status = false;
 829                         break;
 830                 }
 831         } while (++count);
 832
 833         return status;
 834 }
 835
 836 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
 837 {
 838         struct rtl_priv *rtlpriv = rtl_priv(hw);
 839         unsigned short i;
 840         u8 txpktbuf_bndy;
 841         u32 rqpn;
 842         u8 maxpage;
 843         bool status;
 844
 845         maxpage = 255;
 846         txpktbuf_bndy = 0xF8;
 847         rqpn = 0x80e70808;
 848         if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
 849                 txpktbuf_bndy = 0xFA;
 850                 rqpn = 0x80e90808;
 851         }
 852
 853         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 854         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
 855
 856         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 857
 858         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 859         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 860
 861         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 862         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 863
 864         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 865                 status = _rtl8821ae_llt_write(hw, i, i + 1);
 866                 if (!status)
 867                         return status;
 868         }
 869
 870         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 871         if (!status)
 872                 return status;
 873
 874         for (i = txpktbuf_bndy; i < maxpage; i++) {
 875                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
 876                 if (!status)
 877                         return status;
 878         }
 879
 880         status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
 881         if (!status)
 882                 return status;
 883
 884         rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
 885
 886         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 887
 888         return true;
 889 }
 890
 891 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
 892 {
 893         struct rtl_priv *rtlpriv = rtl_priv(hw);
 894         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 895         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 896         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 897         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 898
 899         if (rtlpriv->rtlhal.up_first_time)
 900                 return;
 901
 902         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 903                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 904                         rtl8812ae_sw_led_on(hw, pled0);
 905                 else
 906                         rtl8821ae_sw_led_on(hw, pled0);
 907         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 908                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 909                         rtl8812ae_sw_led_on(hw, pled0);
 910                 else
 911                         rtl8821ae_sw_led_on(hw, pled0);
 912         else
 913                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 914                         rtl8812ae_sw_led_off(hw, pled0);
 915                 else
 916                         rtl8821ae_sw_led_off(hw, pled0);
 917 }
 918
 919 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
 920 {
 921         struct rtl_priv *rtlpriv = rtl_priv(hw);
 922         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 923         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 924
 925         u8 bytetmp = 0;
 926         u16 wordtmp = 0;
 927         bool mac_func_enable = rtlhal->mac_func_enable;
 928
 929         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 930
 931         /*Auto Power Down to CHIP-off State*/
 932         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 933         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 934
 935         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 936                 /* HW Power on sequence*/
 937                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 938                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 939                                               RTL8812_NIC_ENABLE_FLOW)) {
 940                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 941                                          "init 8812 MAC Fail as power on failure\n");
 942                                 return false;
 943                 }
 944         } else {
 945                 /* HW Power on sequence */
 946                 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
 947                                               PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 948                                               RTL8821A_NIC_ENABLE_FLOW)){
 949                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 950                                 "init 8821 MAC Fail as power on failure\n");
 951                         return false;
 952                 }
 953         }
 954
 955         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 956         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 957
 958         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 959         bytetmp = 0xff;
 960         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 961         mdelay(2);
 962
 963         bytetmp = 0xff;
 964         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 965         mdelay(2);
 966
 967         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 968                 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 969                 if (bytetmp & BIT(0)) {
 970                         bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 971                         bytetmp |= BIT(6);
 972                         rtl_write_byte(rtlpriv, 0x7c, bytetmp);
 973                 }
 974         }
 975
 976         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 977         bytetmp &= ~BIT(4);
 978         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
 979
 980         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 981
 982         if (!mac_func_enable) {
 983                 if (!_rtl8821ae_llt_table_init(hw))
 984                         return false;
 985         }
 986
 987         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 988         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 989
 990         /* Enable FW Beamformer Interrupt */
 991         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 992         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 993
 994         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 995         wordtmp &= 0xf;
 996         wordtmp |= 0xF5B1;
 997         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 998
 999         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
1000         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1001         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1002         /*low address*/
1003         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1004                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1005         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1006                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1007         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1008                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1009         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1010                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1011         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1012                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1013         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1014                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1015         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1016                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1017         rtl_write_dword(rtlpriv, REG_RX_DESA,
1018                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1019
1020         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1021
1022         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1023
1024         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1025
1026         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1027         _rtl8821ae_gen_refresh_led_state(hw);
1028
1029         return true;
1030 }
1031
1032 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1033 {
1034         struct rtl_priv *rtlpriv = rtl_priv(hw);
1035         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1036         u32 reg_rrsr;
1037
1038         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1039
1040         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1041         /* ARFB table 9 for 11ac 5G 2SS */
1042         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1043         /* ARFB table 10 for 11ac 5G 1SS */
1044         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1045         /* ARFB table 11 for 11ac 24G 1SS */
1046         rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1047         rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1048         /* ARFB table 12 for 11ac 24G 1SS */
1049         rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1050         rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1051         /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1052         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1053         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1054
1055         /*Set retry limit*/
1056         rtl_write_word(rtlpriv, REG_RL, 0x0707);
1057
1058         /* Set Data / Response auto rate fallack retry count*/
1059         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1060         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1061         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1062         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1063
1064         rtlpci->reg_bcn_ctrl_val = 0x1d;
1065         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1066
1067         /* TBTT prohibit hold time. Suggested by designer TimChen. */
1068         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1069
1070         /* AGGR_BK_TIME Reg51A 0x16 */
1071         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1072
1073         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1074         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1075
1076         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1077         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1078         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1079 }
1080
1081 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1082 {
1083         u16 ret = 0;
1084         u8 tmp = 0, count = 0;
1085
1086         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1087         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1088         count = 0;
1089         while (tmp && count < 20) {
1090                 udelay(10);
1091                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1092                 count++;
1093         }
1094         if (0 == tmp)
1095                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1096
1097         return ret;
1098 }
1099
1100 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1101 {
1102         u8 tmp = 0, count = 0;
1103
1104         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1105         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1106         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1107         count = 0;
1108         while (tmp && count < 20) {
1109                 udelay(10);
1110                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1111                 count++;
1112         }
1113 }
1114
1115 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1116 {
1117         u16 read_addr = addr & 0xfffc;
1118         u8 tmp = 0, count = 0, ret = 0;
1119
1120         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1121         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1122         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1123         count = 0;
1124         while (tmp && count < 20) {
1125                 udelay(10);
1126                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1127                 count++;
1128         }
1129         if (0 == tmp) {
1130                 read_addr = REG_DBI_RDATA + addr % 4;
1131                 ret = rtl_read_byte(rtlpriv, read_addr);
1132         }
1133         return ret;
1134 }
1135
1136 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1137 {
1138         u8 tmp = 0, count = 0;
1139         u16 wrtie_addr, remainder = addr % 4;
1140
1141         wrtie_addr = REG_DBI_WDATA + remainder;
1142         rtl_write_byte(rtlpriv, wrtie_addr, data);
1143
1144         wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1145         rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1146
1147         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1148
1149         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1150         count = 0;
1151         while (tmp && count < 20) {
1152                 udelay(10);
1153                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1154                 count++;
1155         }
1156 }
1157
1158 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1159 {
1160         struct rtl_priv *rtlpriv = rtl_priv(hw);
1161         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1162         u8 tmp;
1163
1164         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1165                 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1166                         _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1167
1168                 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1169                         _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1170         }
1171
1172         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1173         _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1174                              ASPM_L1_LATENCY << 3);
1175
1176         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1177         _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1178
1179         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1180                 tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1181                 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1182         }
1183 }
1184
1185 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1186 {
1187         struct rtl_priv *rtlpriv = rtl_priv(hw);
1188         u8 sec_reg_value;
1189         u8 tmp;
1190
1191         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1192                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1193                   rtlpriv->sec.pairwise_enc_algorithm,
1194                   rtlpriv->sec.group_enc_algorithm);
1195
1196         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1197                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1198                          "not open hw encryption\n");
1199                 return;
1200         }
1201
1202         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1203
1204         if (rtlpriv->sec.use_defaultkey) {
1205                 sec_reg_value |= SCR_TXUSEDK;
1206                 sec_reg_value |= SCR_RXUSEDK;
1207         }
1208
1209         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1210
1211         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1212         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1213
1214         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1215                  "The SECR-value %x\n", sec_reg_value);
1216
1217         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1218 }
1219
1220 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1221 #define MAC_ID_STATIC_FOR_DEFAULT_PORT                          0
1222 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST           1
1223 #define MAC_ID_STATIC_FOR_BT_CLIENT_START                               2
1224 #define MAC_ID_STATIC_FOR_BT_CLIENT_END                         3
1225 /* ----------------------------------------------------------- */
1226
1227 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1228 {
1229         struct rtl_priv *rtlpriv = rtl_priv(hw);
1230         u8      media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1231                 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1232                 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1233
1234         rtlpriv->cfg->ops->set_hw_reg(hw,
1235                 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1236
1237         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1238                  "Initialize MacId media status: from %d to %d\n",
1239                  MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1240                  MAC_ID_STATIC_FOR_BT_CLIENT_END);
1241 }
1242
1243 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1244 {
1245         struct rtl_priv *rtlpriv = rtl_priv(hw);
1246         u8 tmp;
1247
1248         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1249         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1250         if (!(tmp & BIT(2))) {
1251                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1252                 mdelay(100);
1253         }
1254
1255         /* read reg 0x350 Bit[25] if 1 : RX hang */
1256         /* read reg 0x350 Bit[24] if 1 : TX hang */
1257         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1258         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1259                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1260                          "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1261                 return true;
1262         } else {
1263                 return false;
1264         }
1265 }
1266
1267 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1268                                          bool mac_power_on,
1269                                          bool in_watchdog)
1270 {
1271         struct rtl_priv *rtlpriv = rtl_priv(hw);
1272         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1273         u8 tmp;
1274         bool release_mac_rx_pause;
1275         u8 backup_pcie_dma_pause;
1276
1277         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1278
1279         /* 1. Disable register write lock. 0x1c[1] = 0 */
1280         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1281         tmp &= ~(BIT(1));
1282         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1283         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1284                 /* write 0xCC bit[2] = 1'b1 */
1285                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1286                 tmp |= BIT(2);
1287                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1288         }
1289
1290         /* 2. Check and pause TRX DMA */
1291         /* write 0x284 bit[18] = 1'b1 */
1292         /* write 0x301 = 0xFF */
1293         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1294         if (tmp & BIT(2)) {
1295                 /* Already pause before the function for another purpose. */
1296                 release_mac_rx_pause = false;
1297         } else {
1298                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1299                 release_mac_rx_pause = true;
1300         }
1301         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1302         if (backup_pcie_dma_pause != 0xFF)
1303                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1304
1305         if (mac_power_on) {
1306                 /* 3. reset TRX function */
1307                 /* write 0x100 = 0x00 */
1308                 rtl_write_byte(rtlpriv, REG_CR, 0);
1309         }
1310
1311         /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1312         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1313         tmp &= ~(BIT(0));
1314         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1315
1316         /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1317         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1318         tmp |= BIT(0);
1319         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1320
1321         if (mac_power_on) {
1322                 /* 6. enable TRX function */
1323                 /* write 0x100 = 0xFF */
1324                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1325
1326                 /* We should init LLT & RQPN and
1327                  * prepare Tx/Rx descrptor address later
1328                  * because MAC function is reset.*/
1329         }
1330
1331         /* 7. Restore PCIe autoload down bit */
1332         /* 8812AE does not has the defination. */
1333         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1334                 /* write 0xF8 bit[17] = 1'b1 */
1335                 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1336                 tmp |= BIT(1);
1337                 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1338         }
1339
1340         /* In MAC power on state, BB and RF maybe in ON state,
1341          * if we release TRx DMA here.
1342          * it will cause packets to be started to Tx/Rx,
1343          * so we release Tx/Rx DMA later.*/
1344         if (!mac_power_on/* || in_watchdog*/) {
1345                 /* 8. release TRX DMA */
1346                 /* write 0x284 bit[18] = 1'b0 */
1347                 /* write 0x301 = 0x00 */
1348                 if (release_mac_rx_pause) {
1349                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1350                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1351                                        tmp & (~BIT(2)));
1352                 }
1353                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1354                                backup_pcie_dma_pause);
1355         }
1356
1357         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1358                 /* 9. lock system register */
1359                 /* write 0xCC bit[2] = 1'b0 */
1360                 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1361                 tmp &= ~(BIT(2));
1362                 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1363         }
1364         return true;
1365 }
1366
1367 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1368 {
1369         struct rtl_priv *rtlpriv = rtl_priv(hw);
1370         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1371         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1372         u8 fw_reason = 0;
1373         struct timeval ts;
1374
1375         fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1376
1377         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1378                  fw_reason);
1379
1380         ppsc->wakeup_reason = 0;
1381
1382         do_gettimeofday(&ts);
1383         rtlhal->last_suspend_sec = ts.tv_sec;
1384
1385         switch (fw_reason) {
1386         case FW_WOW_V2_PTK_UPDATE_EVENT:
1387                 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1388                 do_gettimeofday(&ts);
1389                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1390                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1391                          "It's a WOL PTK Key update event!\n");
1392                 break;
1393         case FW_WOW_V2_GTK_UPDATE_EVENT:
1394                 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1395                 do_gettimeofday(&ts);
1396                 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1397                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1398                          "It's a WOL GTK Key update event!\n");
1399                 break;
1400         case FW_WOW_V2_DISASSOC_EVENT:
1401                 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1402                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1403                          "It's a disassociation event!\n");
1404                 break;
1405         case FW_WOW_V2_DEAUTH_EVENT:
1406                 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1407                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1408                          "It's a deauth event!\n");
1409                 break;
1410         case FW_WOW_V2_FW_DISCONNECT_EVENT:
1411                 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1412                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1413                          "It's a Fw disconnect decision (AP lost) event!\n");
1414         break;
1415         case FW_WOW_V2_MAGIC_PKT_EVENT:
1416                 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1417                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1418                          "It's a magic packet event!\n");
1419                 break;
1420         case FW_WOW_V2_UNICAST_PKT_EVENT:
1421                 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1422                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1423                          "It's an unicast packet event!\n");
1424                 break;
1425         case FW_WOW_V2_PATTERN_PKT_EVENT:
1426                 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1427                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1428                          "It's a pattern match event!\n");
1429                 break;
1430         case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1431                 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1432                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1433                          "It's an RTD3 Ssid match event!\n");
1434                 break;
1435         case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1436                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1437                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1438                          "It's an RealWoW wake packet event!\n");
1439                 break;
1440         case FW_WOW_V2_REALWOW_V2_ACKLOST:
1441                 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1442                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1443                          "It's an RealWoW ack lost event!\n");
1444                 break;
1445         default:
1446                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1447                          "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1448                           fw_reason);
1449                 break;
1450         }
1451 }
1452
1453 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1454 {
1455         struct rtl_priv *rtlpriv = rtl_priv(hw);
1456         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1457
1458         /*low address*/
1459         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1460                         rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1461         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1462                         rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1463         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1464                         rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1465         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1466                         rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1467         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1468                         rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1469         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1470                         rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1471         rtl_write_dword(rtlpriv, REG_HQ_DESA,
1472                         rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1473         rtl_write_dword(rtlpriv, REG_RX_DESA,
1474                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1475 }
1476
1477 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1478 {
1479         bool status = true;
1480         u32 i;
1481         u32 txpktbuf_bndy = boundary;
1482         u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1483
1484         for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1485                 status = _rtl8821ae_llt_write(hw, i , i + 1);
1486                 if (!status)
1487                         return status;
1488         }
1489
1490         status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1491         if (!status)
1492                 return status;
1493
1494         for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1495                 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1496                 if (!status)
1497                         return status;
1498         }
1499
1500         status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1501                                       txpktbuf_bndy);
1502         if (!status)
1503                 return status;
1504
1505         return status;
1506 }
1507
1508 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1509                              u16 npq_rqpn_value, u32 rqpn_val)
1510 {
1511         struct rtl_priv *rtlpriv = rtl_priv(hw);
1512         u8 tmp;
1513         bool ret = true;
1514         u16 count = 0, tmp16;
1515         bool support_remote_wakeup;
1516
1517         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1518                                       (u8 *)(&support_remote_wakeup));
1519
1520         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1521                  "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1522                   boundary, npq_rqpn_value, rqpn_val);
1523
1524         /* stop PCIe DMA
1525          * 1. 0x301[7:0] = 0xFE */
1526         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1527
1528         /* wait TXFF empty
1529          * 2. polling till 0x41A[15:0]=0x07FF */
1530         tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1531         while ((tmp16 & 0x07FF) != 0x07FF) {
1532                 udelay(100);
1533                 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1534                 count++;
1535                 if ((count % 200) == 0) {
1536                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1537                                  "Tx queue is not empty for 20ms!\n");
1538                 }
1539                 if (count >= 1000) {
1540                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1541                                  "Wait for Tx FIFO empty timeout!\n");
1542                         break;
1543                 }
1544         }
1545
1546         /* TX pause
1547          * 3. reg 0x522=0xFF */
1548         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1549
1550         /* Wait TX State Machine OK
1551          * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1552         count = 0;
1553         while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1554                 udelay(100);
1555                 count++;
1556                 if (count >= 500) {
1557                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1558                                  "Wait for TX State Machine ready timeout !!\n");
1559                         break;
1560                 }
1561         }
1562
1563         /* stop RX DMA path
1564          * 5.   0x284[18] = 1
1565          * 6.   wait till 0x284[17] == 1
1566          * wait RX DMA idle */
1567         count = 0;
1568         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1569         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1570         do {
1571                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1572                 udelay(10);
1573                 count++;
1574         } while (!(tmp & BIT(1)) && count < 100);
1575
1576         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1577                  "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1578                   count, tmp);
1579
1580         /* reset BB
1581          * 7.   0x02 [0] = 0 */
1582         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1583         tmp &= ~(BIT(0));
1584         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1585
1586         /* Reset TRX MAC
1587          * 8.    0x100 = 0x00
1588          * Delay (1ms) */
1589         rtl_write_byte(rtlpriv, REG_CR, 0x00);
1590         udelay(1000);
1591
1592         /* Disable MAC Security Engine
1593          * 9.   0x100 bit[9]=0 */
1594         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1595         tmp &= ~(BIT(1));
1596         rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1597
1598         /* To avoid DD-Tim Circuit hang
1599          * 10.  0x553 bit[5]=1 */
1600         tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1601         rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1602
1603         /* Enable MAC Security Engine
1604          * 11.  0x100 bit[9]=1 */
1605         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1606         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1607
1608         /* Enable TRX MAC
1609          * 12.   0x100 = 0xFF
1610          *      Delay (1ms) */
1611         rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1612         udelay(1000);
1613
1614         /* Enable BB
1615          * 13.  0x02 [0] = 1 */
1616         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1617         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1618
1619         /* beacon setting
1620          * 14,15. set beacon head page (reg 0x209 and 0x424) */
1621         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1622         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1623         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1624
1625         /* 16.  WMAC_LBK_BF_HD 0x45D[7:0]
1626          * WMAC_LBK_BF_HD */
1627         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1628                        (u8)boundary);
1629
1630         rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1631
1632         /* init LLT
1633          * 17. init LLT */
1634         if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1635                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1636                          "Failed to init LLT table!\n");
1637                 return false;
1638         }
1639
1640         /* reallocate RQPN
1641          * 18. reallocate RQPN and init LLT */
1642         rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1643         rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1644
1645         /* release Tx pause
1646          * 19. 0x522=0x00 */
1647         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1648
1649         /* enable PCIE DMA
1650          * 20. 0x301[7:0] = 0x00
1651          * 21. 0x284[18] = 0 */
1652         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1653         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1654         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1655
1656         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1657         return ret;
1658 }
1659
1660 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1661 {
1662         struct rtl_priv *rtlpriv = rtl_priv(hw);
1663         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1664         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1665
1666 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1667         /* Re-download normal Fw. */
1668         rtl8821ae_set_fw_related_for_wowlan(hw, false);
1669 #endif
1670
1671         /* Re-Initialize LLT table. */
1672         if (rtlhal->re_init_llt_table) {
1673                 u32 rqpn = 0x80e70808;
1674                 u8 rqpn_npq = 0, boundary = 0xF8;
1675                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1676                         rqpn = 0x80e90808;
1677                         boundary = 0xFA;
1678                 }
1679                 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1680                         rtlhal->re_init_llt_table = false;
1681         }
1682
1683         ppsc->rfpwr_state = ERFON;
1684 }
1685
1686 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1687 {
1688         u8 tmp  = 0;
1689         struct rtl_priv *rtlpriv = rtl_priv(hw);
1690
1691         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1692
1693         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1694         if (!(tmp & (BIT(2) | BIT(3)))) {
1695                 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1696                          "0x160(%#x)return!!\n", tmp);
1697                 return;
1698         }
1699
1700         tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1701         _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1702
1703         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1704         _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1705
1706         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1707 }
1708
1709 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1710 {
1711         u8 tmp  = 0;
1712         struct rtl_priv *rtlpriv = rtl_priv(hw);
1713
1714         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1715
1716         /* Check 0x98[10] */
1717         tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1718         if (!(tmp & BIT(2))) {
1719                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1720                          "<---0x99(%#x) return!!\n", tmp);
1721                 return;
1722         }
1723
1724         /* LTR idle latency, 0x90 for 144us */
1725         rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1726
1727         /* LTR active latency, 0x3c for 60us */
1728         rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1729
1730         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1731         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1732
1733         tmp = rtl_read_byte(rtlpriv, 0x7a4);
1734         rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1735         rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1736
1737         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1738 }
1739
1740 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1741 {
1742         struct rtl_priv *rtlpriv = rtl_priv(hw);
1743         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1744         bool init_finished = true;
1745         u8 tmp = 0;
1746
1747         /* Get Fw wake up reason. */
1748         _rtl8821ae_get_wakeup_reason(hw);
1749
1750         /* Patch Pcie Rx DMA hang after S3/S4 several times.
1751          * The root cause has not be found. */
1752         if (_rtl8821ae_check_pcie_dma_hang(hw))
1753                 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1754
1755         /* Prepare Tx/Rx Desc Hw address. */
1756         _rtl8821ae_init_trx_desc_hw_address(hw);
1757
1758         /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1759         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1760         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1761
1762         /* Check wake up event.
1763          * We should check wake packet bit before disable wowlan by H2C or
1764          * Fw will clear the bit. */
1765         tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1766         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1767                  "Read REG_FTISR 0x13f = %#X\n", tmp);
1768
1769         /* Set the WoWLAN related function control disable. */
1770         rtl8821ae_set_fw_wowlan_mode(hw, false);
1771         rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1772
1773         if (rtlhal->hw_rof_enable) {
1774                 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1775                 if (tmp & BIT(1)) {
1776                         /* Clear GPIO9 ISR */
1777                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1778                         init_finished = false;
1779                 } else {
1780                         init_finished = true;
1781                 }
1782         }
1783
1784         if (init_finished) {
1785                 _rtl8821ae_simple_initialize_adapter(hw);
1786
1787                 /* Release Pcie Interface Tx DMA. */
1788                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1789                 /* Release Pcie RX DMA */
1790                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1791
1792                 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1793                 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1794
1795                 _rtl8821ae_enable_l1off(hw);
1796                 _rtl8821ae_enable_ltr(hw);
1797         }
1798
1799         return init_finished;
1800 }
1801
1802 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1803 {
1804         /* BB OFDM RX Path_A */
1805         rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1806         /* BB OFDM TX Path_A */
1807         rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1808         /* BB CCK R/Rx Path_A */
1809         rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1810         /* MCS support */
1811         rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1812         /* RF Path_B HSSI OFF */
1813         rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1814         /* RF Path_B Power Down */
1815         rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1816         /* ADDA Path_B OFF */
1817         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1818         rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1819 }
1820
1821 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1822 {
1823         struct rtl_priv *rtlpriv = rtl_priv(hw);
1824         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1825         u8 u1b_tmp;
1826
1827         rtlhal->mac_func_enable = false;
1828
1829         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1830                 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1831                 /* 1. Run LPS WL RFOFF flow */
1832                 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1833                 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1834                 */
1835                 rtl_hal_pwrseqcmdparsing(rtlpriv,
1836                         PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1837                         PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1838         }
1839         /* 2. 0x1F[7:0] = 0 */
1840         /* turn off RF */
1841         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1842         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1843                 rtlhal->fw_ready) {
1844                 rtl8821ae_firmware_selfreset(hw);
1845         }
1846
1847         /* Reset MCU. Suggested by Filen. */
1848         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1849         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1850
1851         /* g.   MCUFWDL 0x80[1:0]=0      */
1852         /* reset MCU ready status */
1853         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1854
1855         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1856                 /* HW card disable configuration. */
1857                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1858                         PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1859         } else {
1860                 /* HW card disable configuration. */
1861                 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1862                         PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1863         }
1864
1865         /* Reset MCU IO Wrapper */
1866         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1867         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1868         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1869         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1870
1871         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1872         /* lock ISO/CLK/Power control register */
1873         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1874 }
1875
1876 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1877 {
1878         struct rtl_priv *rtlpriv = rtl_priv(hw);
1879         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1880         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1881         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1882         bool rtstatus = true;
1883         int err;
1884         u8 tmp_u1b;
1885         bool support_remote_wakeup;
1886         u32 nav_upper = WIFI_NAV_UPPER_US;
1887
1888         rtlhal->being_init_adapter = true;
1889         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1890                                       (u8 *)(&support_remote_wakeup));
1891         rtlpriv->intf_ops->disable_aspm(hw);
1892
1893         /*YP wowlan not considered*/
1894
1895         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1896         if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1897                 rtlhal->mac_func_enable = true;
1898                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1899                          "MAC has already power on.\n");
1900         } else {
1901                 rtlhal->mac_func_enable = false;
1902                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1903         }
1904
1905         if (support_remote_wakeup &&
1906                 rtlhal->wake_from_pnp_sleep &&
1907                 rtlhal->mac_func_enable) {
1908                 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1909                         rtlhal->being_init_adapter = false;
1910                         return 0;
1911                 }
1912         }
1913
1914         if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1915                 _rtl8821ae_reset_pcie_interface_dma(hw,
1916                                                     rtlhal->mac_func_enable,
1917                                                     false);
1918                 rtlhal->mac_func_enable = false;
1919         }
1920
1921         /* Reset MAC/BB/RF status if it is not powered off
1922          * before calling initialize Hw flow to prevent
1923          * from interface and MAC status mismatch.
1924          * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1925         if (rtlhal->mac_func_enable) {
1926                 _rtl8821ae_poweroff_adapter(hw);
1927                 rtlhal->mac_func_enable = false;
1928         }
1929
1930         rtstatus = _rtl8821ae_init_mac(hw);
1931         if (rtstatus != true) {
1932                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1933                 err = 1;
1934                 return err;
1935         }
1936
1937         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1938         tmp_u1b &= 0x7F;
1939         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1940
1941         err = rtl8821ae_download_fw(hw, false);
1942         if (err) {
1943                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1944                          "Failed to download FW. Init HW without FW now\n");
1945                 err = 1;
1946                 rtlhal->fw_ready = false;
1947                 return err;
1948         } else {
1949                 rtlhal->fw_ready = true;
1950         }
1951         ppsc->fw_current_inpsmode = false;
1952         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1953         rtlhal->fw_clk_change_in_progress = false;
1954         rtlhal->allow_sw_to_change_hwclc = false;
1955         rtlhal->last_hmeboxnum = 0;
1956
1957         /*SIC_Init(Adapter);
1958         if(rtlhal->AMPDUBurstMode)
1959                 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1960
1961         rtl8821ae_phy_mac_config(hw);
1962         /* because last function modify RCR, so we update
1963          * rcr var here, or TP will unstable for receive_config
1964          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1965          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1966         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1967         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1968         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1969         rtl8821ae_phy_bb_config(hw);
1970
1971         rtl8821ae_phy_rf_config(hw);
1972
1973         if (rtlpriv->phy.rf_type == RF_1T1R &&
1974                 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1975                 _rtl8812ae_bb8812_config_1t(hw);
1976
1977         _rtl8821ae_hw_configure(hw);
1978
1979         rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1980
1981         /*set wireless mode*/
1982
1983         rtlhal->mac_func_enable = true;
1984
1985         rtl_cam_reset_all_entry(hw);
1986
1987         rtl8821ae_enable_hw_security_config(hw);
1988
1989         ppsc->rfpwr_state = ERFON;
1990
1991         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1992         _rtl8821ae_enable_aspm_back_door(hw);
1993         rtlpriv->intf_ops->enable_aspm(hw);
1994
1995         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1996             (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1997                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1998
1999         rtl8821ae_bt_hw_init(hw);
2000         rtlpriv->rtlhal.being_init_adapter = false;
2001
2002         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2003
2004         /* rtl8821ae_dm_check_txpower_tracking(hw); */
2005         /* rtl8821ae_phy_lc_calibrate(hw); */
2006         if (support_remote_wakeup)
2007                 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2008
2009         /* Release Rx DMA*/
2010         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2011         if (tmp_u1b & BIT(2)) {
2012                 /* Release Rx DMA if needed*/
2013                 tmp_u1b &= ~BIT(2);
2014                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2015         }
2016
2017         /* Release Tx/Rx PCIE DMA if*/
2018         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2019
2020         rtl8821ae_dm_init(hw);
2021         rtl8821ae_macid_initialize_mediastatus(hw);
2022
2023         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2024         return err;
2025 }
2026
2027 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2028 {
2029         struct rtl_priv *rtlpriv = rtl_priv(hw);
2030         struct rtl_phy *rtlphy = &rtlpriv->phy;
2031         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2032         enum version_8821ae version = VERSION_UNKNOWN;
2033         u32 value32;
2034
2035         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2036         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2037                  "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2038
2039         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2040                 rtlphy->rf_type = RF_2T2R;
2041         else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2042                 rtlphy->rf_type = RF_1T1R;
2043
2044         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2045                  "RF_Type is %x!!\n", rtlphy->rf_type);
2046
2047         if (value32 & TRP_VAUX_EN) {
2048                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2049                         if (rtlphy->rf_type == RF_2T2R)
2050                                 version = VERSION_TEST_CHIP_2T2R_8812;
2051                         else
2052                                 version = VERSION_TEST_CHIP_1T1R_8812;
2053                 } else
2054                         version = VERSION_TEST_CHIP_8821;
2055         } else {
2056                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2057                         u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2058
2059                         if (rtlphy->rf_type == RF_2T2R)
2060                                 version =
2061                                         (enum version_8821ae)(CHIP_8812
2062                                         | NORMAL_CHIP |
2063                                         RF_TYPE_2T2R);
2064                         else
2065                                 version = (enum version_8821ae)(CHIP_8812
2066                                         | NORMAL_CHIP);
2067
2068                         version = (enum version_8821ae)(version | (rtl_id << 12));
2069                 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2070                         u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2071
2072                         version = (enum version_8821ae)(CHIP_8821
2073                                 | NORMAL_CHIP | rtl_id);
2074                 }
2075         }
2076
2077         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2078                 /*WL_HWROF_EN.*/
2079                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2080                 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2081         }
2082
2083         switch (version) {
2084         case VERSION_TEST_CHIP_1T1R_8812:
2085                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2086                          "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2087                 break;
2088         case VERSION_TEST_CHIP_2T2R_8812:
2089                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2090                          "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2091                 break;
2092         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2093                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2094                          "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2095                 break;
2096         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2097                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2098                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2099                 break;
2100         case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2101                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2102                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2103                 break;
2104         case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2105                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2106                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2107                 break;
2108         case VERSION_TEST_CHIP_8821:
2109                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2110                          "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2111                 break;
2112         case VERSION_NORMAL_TSMC_CHIP_8821:
2113                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2114                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2115                 break;
2116         case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2117                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2118                          "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2119                 break;
2120         default:
2121                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2122                          "Chip Version ID: Unknow (0x%X)\n", version);
2123                 break;
2124         }
2125
2126         return version;
2127 }
2128
2129 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2130                                      enum nl80211_iftype type)
2131 {
2132         struct rtl_priv *rtlpriv = rtl_priv(hw);
2133         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2134         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2135         bt_msr &= 0xfc;
2136
2137         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2138         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2139                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2140
2141         if (type == NL80211_IFTYPE_UNSPECIFIED ||
2142             type == NL80211_IFTYPE_STATION) {
2143                 _rtl8821ae_stop_tx_beacon(hw);
2144                 _rtl8821ae_enable_bcn_sub_func(hw);
2145         } else if (type == NL80211_IFTYPE_ADHOC ||
2146                 type == NL80211_IFTYPE_AP) {
2147                 _rtl8821ae_resume_tx_beacon(hw);
2148                 _rtl8821ae_disable_bcn_sub_func(hw);
2149         } else {
2150                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2151                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2152                          type);
2153         }
2154
2155         switch (type) {
2156         case NL80211_IFTYPE_UNSPECIFIED:
2157                 bt_msr |= MSR_NOLINK;
2158                 ledaction = LED_CTL_LINK;
2159                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2160                          "Set Network type to NO LINK!\n");
2161                 break;
2162         case NL80211_IFTYPE_ADHOC:
2163                 bt_msr |= MSR_ADHOC;
2164                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2165                          "Set Network type to Ad Hoc!\n");
2166                 break;
2167         case NL80211_IFTYPE_STATION:
2168                 bt_msr |= MSR_INFRA;
2169                 ledaction = LED_CTL_LINK;
2170                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2171                          "Set Network type to STA!\n");
2172                 break;
2173         case NL80211_IFTYPE_AP:
2174                 bt_msr |= MSR_AP;
2175                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2176                          "Set Network type to AP!\n");
2177                 break;
2178         default:
2179                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2180                          "Network type %d not support!\n", type);
2181                 return 1;
2182         }
2183
2184         rtl_write_byte(rtlpriv, MSR, bt_msr);
2185         rtlpriv->cfg->ops->led_control(hw, ledaction);
2186         if ((bt_msr & MSR_MASK) == MSR_AP)
2187                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2188         else
2189                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2190
2191         return 0;
2192 }
2193
2194 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2195 {
2196         struct rtl_priv *rtlpriv = rtl_priv(hw);
2197         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2198         u32 reg_rcr = rtlpci->receive_config;
2199
2200         if (rtlpriv->psc.rfpwr_state != ERFON)
2201                 return;
2202
2203         if (check_bssid) {
2204                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2205                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2206                                               (u8 *)(&reg_rcr));
2207                 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2208         } else if (!check_bssid) {
2209                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2210                 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2211                 rtlpriv->cfg->ops->set_hw_reg(hw,
2212                         HW_VAR_RCR, (u8 *)(&reg_rcr));
2213         }
2214 }
2215
2216 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2217 {
2218         struct rtl_priv *rtlpriv = rtl_priv(hw);
2219
2220         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2221
2222         if (_rtl8821ae_set_media_status(hw, type))
2223                 return -EOPNOTSUPP;
2224
2225         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2226                 if (type != NL80211_IFTYPE_AP)
2227                         rtl8821ae_set_check_bssid(hw, true);
2228         } else {
2229                 rtl8821ae_set_check_bssid(hw, false);
2230         }
2231
2232         return 0;
2233 }
2234
2235 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2236 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2237 {
2238         struct rtl_priv *rtlpriv = rtl_priv(hw);
2239         rtl8821ae_dm_init_edca_turbo(hw);
2240         switch (aci) {
2241         case AC1_BK:
2242                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2243                 break;
2244         case AC0_BE:
2245                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2246                 break;
2247         case AC2_VI:
2248                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2249                 break;
2250         case AC3_VO:
2251                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2252                 break;
2253         default:
2254                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2255                 break;
2256         }
2257 }
2258
2259 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2260 {
2261         struct rtl_priv *rtlpriv = rtl_priv(hw);
2262         u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2263
2264         rtl_write_dword(rtlpriv, REG_HISR, tmp);
2265
2266         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2267         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2268
2269         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2270         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2271 }
2272
2273 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2274 {
2275         struct rtl_priv *rtlpriv = rtl_priv(hw);
2276         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2277
2278         if (rtlpci->int_clear)
2279                 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2280
2281         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2282         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2283         rtlpci->irq_enabled = true;
2284         /* there are some C2H CMDs have been sent before
2285         system interrupt is enabled, e.g., C2H, CPWM.
2286         *So we need to clear all C2H events that FW has
2287         notified, otherwise FW won't schedule any commands anymore.
2288         */
2289         /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2290         /*enable system interrupt*/
2291         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2292 }
2293
2294 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2295 {
2296         struct rtl_priv *rtlpriv = rtl_priv(hw);
2297         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2298
2299         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2300         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2301         rtlpci->irq_enabled = false;
2302         /*synchronize_irq(rtlpci->pdev->irq);*/
2303 }
2304
2305 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2306 {
2307         struct rtl_priv *rtlpriv = rtl_priv(hw);
2308         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2309         u16 cap_hdr;
2310         u8 cap_pointer;
2311         u8 cap_id = 0xff;
2312         u8 pmcs_reg;
2313         u8 cnt = 0;
2314
2315         /* Get the Capability pointer first,
2316          * the Capability Pointer is located at
2317          * offset 0x34 from the Function Header */
2318
2319         pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2320         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2321                  "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2322
2323         do {
2324                 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2325                 cap_id = cap_hdr & 0xFF;
2326
2327                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2328                          "in pci configuration, cap_pointer%x = %x\n",
2329                           cap_pointer, cap_id);
2330
2331                 if (cap_id == 0x01) {
2332                         break;
2333                 } else {
2334                         /* point to next Capability */
2335                         cap_pointer = (cap_hdr >> 8) & 0xFF;
2336                         /* 0: end of pci capability, 0xff: invalid value */
2337                         if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2338                                 cap_id = 0xff;
2339                                 break;
2340                         }
2341                 }
2342         } while (cnt++ < 200);
2343
2344         if (cap_id == 0x01) {
2345                 /* Get the PM CSR (Control/Status Register),
2346                  * The PME_Status is located at PM Capatibility offset 5, bit 7
2347                  */
2348                 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2349
2350                 if (pmcs_reg & BIT(7)) {
2351                         /* PME event occured, clear the PM_Status by write 1 */
2352                         pmcs_reg = pmcs_reg | BIT(7);
2353
2354                         pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2355                                               pmcs_reg);
2356                         /* Read it back to check */
2357                         pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2358                                              &pmcs_reg);
2359                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2360                                  "Clear PME status 0x%2x to 0x%2x\n",
2361                                   cap_pointer + 5, pmcs_reg);
2362                 } else {
2363                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2364                                  "PME status(0x%2x) = 0x%2x\n",
2365                                   cap_pointer + 5, pmcs_reg);
2366                 }
2367         } else {
2368                 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2369                          "Cannot find PME Capability\n");
2370         }
2371 }
2372
2373 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2374 {
2375         struct rtl_priv *rtlpriv = rtl_priv(hw);
2376         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2377         struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2378         struct rtl_mac *mac = rtl_mac(rtlpriv);
2379         enum nl80211_iftype opmode;
2380         bool support_remote_wakeup;
2381         u8 tmp;
2382         u32 count = 0;
2383
2384         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2385                                       (u8 *)(&support_remote_wakeup));
2386
2387         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2388
2389         if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2390             || !rtlhal->enter_pnp_sleep) {
2391                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2392                 mac->link_state = MAC80211_NOLINK;
2393                 opmode = NL80211_IFTYPE_UNSPECIFIED;
2394                 _rtl8821ae_set_media_status(hw, opmode);
2395                 _rtl8821ae_poweroff_adapter(hw);
2396         } else {
2397                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2398                 /* 3 <1> Prepare for configuring wowlan related infomations */
2399                 /* Clear Fw WoWLAN event. */
2400                 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2401
2402 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2403                 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2404 #endif
2405                 /* Dynamically adjust Tx packet boundary
2406                  * for download reserved page packet.
2407                  * reserve 30 pages for rsvd page */
2408                 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2409                         rtlhal->re_init_llt_table = true;
2410
2411                 /* 3 <2> Set Fw releted H2C cmd. */
2412
2413                 /* Set WoWLAN related security information. */
2414                 rtl8821ae_set_fw_global_info_cmd(hw);
2415
2416                 _rtl8821ae_download_rsvd_page(hw, true);
2417
2418                 /* Just enable AOAC related functions when we connect to AP. */
2419                 printk("mac->link_state = %d\n", mac->link_state);
2420                 if (mac->link_state >= MAC80211_LINKED &&
2421                     mac->opmode == NL80211_IFTYPE_STATION) {
2422                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2423                         rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2424                                                               RT_MEDIA_CONNECT);
2425
2426                         rtl8821ae_set_fw_wowlan_mode(hw, true);
2427                         /* Enable Fw Keep alive mechanism. */
2428                         rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2429
2430                         /* Enable disconnect decision control. */
2431                         rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2432                 }
2433
2434                 /* 3 <3> Hw Configutations */
2435
2436                 /* Wait untill Rx DMA Finished before host sleep.
2437                  * FW Pause Rx DMA may happens when received packet doing dma.
2438                  */
2439                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2440
2441                 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2442                 count = 0;
2443                 while (!(tmp & BIT(1)) && (count++ < 100)) {
2444                         udelay(10);
2445                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2446                 }
2447                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2448                          "Wait Rx DMA Finished before host sleep. count=%d\n",
2449                           count);
2450
2451                 /* reset trx ring */
2452                 rtlpriv->intf_ops->reset_trx_ring(hw);
2453
2454                 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2455
2456                 _rtl8821ae_clear_pci_pme_status(hw);
2457                 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2458                 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2459                 /* prevent 8051 to be reset by PERST */
2460                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2461                 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2462         }
2463
2464         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2465             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2466                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2467         /* For wowlan+LPS+32k. */
2468         if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2469                 /* Set the WoWLAN related function control enable.
2470                  * It should be the last H2C cmd in the WoWLAN flow. */
2471                 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2472
2473                 /* Stop Pcie Interface Tx DMA. */
2474                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2475                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2476
2477                 /* Wait for TxDMA idle. */
2478                 count = 0;
2479                 do {
2480                         tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2481                         udelay(10);
2482                         count++;
2483                 } while ((tmp != 0) && (count < 100));
2484                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2485                          "Wait Tx DMA Finished before host sleep. count=%d\n",
2486                           count);
2487
2488                 if (rtlhal->hw_rof_enable) {
2489                         printk("hw_rof_enable\n");
2490                         tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2491                         rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2492                 }
2493         }
2494         /* after power off we should do iqk again */
2495         rtlpriv->phy.iqk_initialized = false;
2496 }
2497
2498 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2499                                   u32 *p_inta, u32 *p_intb)
2500 {
2501         struct rtl_priv *rtlpriv = rtl_priv(hw);
2502         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2503
2504         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2505         rtl_write_dword(rtlpriv, ISR, *p_inta);
2506
2507         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2508         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2509 }
2510
2511 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2512 {
2513         struct rtl_priv *rtlpriv = rtl_priv(hw);
2514         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2515         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2516         u16 bcn_interval, atim_window;
2517
2518         bcn_interval = mac->beacon_interval;
2519         atim_window = 2;        /*FIX MERGE */
2520         rtl8821ae_disable_interrupt(hw);
2521         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2522         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2523         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2524         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2525         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2526         rtl_write_byte(rtlpriv, 0x606, 0x30);
2527         rtlpci->reg_bcn_ctrl_val |= BIT(3);
2528         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2529         rtl8821ae_enable_interrupt(hw);
2530 }
2531
2532 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2533 {
2534         struct rtl_priv *rtlpriv = rtl_priv(hw);
2535         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2536         u16 bcn_interval = mac->beacon_interval;
2537
2538         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2539                  "beacon_interval:%d\n", bcn_interval);
2540         rtl8821ae_disable_interrupt(hw);
2541         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2542         rtl8821ae_enable_interrupt(hw);
2543 }
2544
2545 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2546                                    u32 add_msr, u32 rm_msr)
2547 {
2548         struct rtl_priv *rtlpriv = rtl_priv(hw);
2549         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2550
2551         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2552                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2553
2554         if (add_msr)
2555                 rtlpci->irq_mask[0] |= add_msr;
2556         if (rm_msr)
2557                 rtlpci->irq_mask[0] &= (~rm_msr);
2558         rtl8821ae_disable_interrupt(hw);
2559         rtl8821ae_enable_interrupt(hw);
2560 }
2561
2562 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2563 {
2564         u8 group = 0;
2565
2566         if (chnl <= 14) {
2567                 if (1 <= chnl && chnl <= 2)
2568                         group = 0;
2569         else if (3 <= chnl && chnl <= 5)
2570                         group = 1;
2571         else if (6 <= chnl && chnl <= 8)
2572                         group = 2;
2573         else if (9 <= chnl && chnl <= 11)
2574                         group = 3;
2575         else /*if (12 <= chnl && chnl <= 14)*/
2576                         group = 4;
2577         } else {
2578                 if (36 <= chnl && chnl <= 42)
2579                         group = 0;
2580         else if (44 <= chnl && chnl <= 48)
2581                         group = 1;
2582         else if (50 <= chnl && chnl <= 58)
2583                         group = 2;
2584         else if (60 <= chnl && chnl <= 64)
2585                         group = 3;
2586         else if (100 <= chnl && chnl <= 106)
2587                         group = 4;
2588         else if (108 <= chnl && chnl <= 114)
2589                         group = 5;
2590         else if (116 <= chnl && chnl <= 122)
2591                         group = 6;
2592         else if (124 <= chnl && chnl <= 130)
2593                         group = 7;
2594         else if (132 <= chnl && chnl <= 138)
2595                         group = 8;
2596         else if (140 <= chnl && chnl <= 144)
2597                         group = 9;
2598         else if (149 <= chnl && chnl <= 155)
2599                         group = 10;
2600         else if (157 <= chnl && chnl <= 161)
2601                         group = 11;
2602         else if (165 <= chnl && chnl <= 171)
2603                         group = 12;
2604         else if (173 <= chnl && chnl <= 177)
2605                         group = 13;
2606                 else
2607                         /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2608                                 "5G, Channel %d in Group not found\n",chnl);*/
2609                         RT_ASSERT(!COMP_EFUSE,
2610                                 "5G, Channel %d in Group not found\n", chnl);
2611         }
2612         return group;
2613 }
2614
2615 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2616         struct txpower_info_2g *pwrinfo24g,
2617         struct txpower_info_5g *pwrinfo5g,
2618         bool autoload_fail,
2619         u8 *hwinfo)
2620 {
2621         struct rtl_priv *rtlpriv = rtl_priv(hw);
2622         u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2623
2624         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2625                  "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2626                  (eeAddr+1), hwinfo[eeAddr+1]);
2627         if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2628                 autoload_fail = true;
2629
2630         if (autoload_fail) {
2631                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2632                          "auto load fail : Use Default value!\n");
2633                 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2634                         /*2.4G default value*/
2635                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2636                                 pwrinfo24g->index_cck_base[rfPath][group] =     0x2D;
2637                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2638                         }
2639                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2640                                 if (TxCount == 0) {
2641                                         pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2642                                         pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2643                                 } else {
2644                                         pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2645                                         pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2646                                         pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2647                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2648                                 }
2649                         }
2650                         /*5G default value*/
2651                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2652                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2653
2654                         for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2655                                 if (TxCount == 0) {
2656                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2657                                         pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2658                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2659                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2660                                 } else {
2661                                         pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2662                                         pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2663                                         pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2664                                         pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2665                                         pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2666                                 }
2667                         }
2668                 }
2669                 return;
2670         }
2671
2672         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2673
2674         for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2675                 /*2.4G default value*/
2676                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2677                         pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2678                         if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2679                                 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2680                 }
2681                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2682                         pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2683                         if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2684                                 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2685                 }
2686                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2687                         if (TxCount == 0) {
2688                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2689                                 /*bit sign number to 8 bit sign number*/
2690                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2691                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2692                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2693                                 /*bit sign number to 8 bit sign number*/
2694                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2695                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2696                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2697
2698                                 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2699                                 eeAddr++;
2700                         } else {
2701                                 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2702                                 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2703                                         pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2704
2705                                 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2706                                 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2707                                         pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2708
2709                                 eeAddr++;
2710
2711                                 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2712                                 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2713                                         pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2714
2715                                 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2716                                 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2717                                         pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2718
2719                                 eeAddr++;
2720                         }
2721                 }
2722
2723                 /*5G default value*/
2724                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2725                         pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2726                         if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2727                                 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2728                 }
2729
2730                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2731                         if (TxCount == 0) {
2732                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2733
2734                                 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2735                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2736                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2737
2738                                 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2739                                 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2740                                         pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2741
2742                                 eeAddr++;
2743                         } else {
2744                                 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2745                                 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2746                                         pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2747
2748                                 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2749                                 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2750                                         pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2751
2752                                 eeAddr++;
2753                         }
2754                 }
2755
2756                 pwrinfo5g->ofdm_diff[rfPath][1] =       (hwinfo[eeAddr] & 0xf0) >> 4;
2757                 pwrinfo5g->ofdm_diff[rfPath][2] =       (hwinfo[eeAddr] & 0x0f);
2758
2759                 eeAddr++;
2760
2761                 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2762
2763                 eeAddr++;
2764
2765                 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2766                         if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2767                                 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2768                 }
2769                 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2770                         pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2771                         /* 4bit sign number to 8 bit sign number */
2772                         if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2773                                 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2774                         /* 4bit sign number to 8 bit sign number */
2775                         pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2776                         if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2777                                 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2778
2779                         eeAddr++;
2780                 }
2781         }
2782 }
2783 #if 0
2784 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2785                                                  bool autoload_fail,
2786                                                  u8 *hwinfo)
2787 {
2788         struct rtl_priv *rtlpriv = rtl_priv(hw);
2789         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2790         struct txpower_info_2g pwrinfo24g;
2791         struct txpower_info_5g pwrinfo5g;
2792         u8 rf_path, index;
2793         u8 i;
2794
2795         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2796                                         &pwrinfo5g, autoload_fail, hwinfo);
2797
2798         for (rf_path = 0; rf_path < 2; rf_path++) {
2799                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2800                         index = _rtl8821ae_get_chnl_group(i + 1);
2801
2802                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2803                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2804                                         pwrinfo24g.index_cck_base[rf_path][5];
2805                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2806                                         pwrinfo24g.index_bw40_base[rf_path][index];
2807                         } else {
2808                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2809                                         pwrinfo24g.index_cck_base[rf_path][index];
2810                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2811                                         pwrinfo24g.index_bw40_base[rf_path][index];
2812                         }
2813                 }
2814
2815                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2816                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2817                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2818                                         pwrinfo5g.index_bw40_base[rf_path][index];
2819                 }
2820                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2821                         u8 upper, lower;
2822                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2823                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2824                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2825
2826                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2827                 }
2828                 for (i = 0; i < MAX_TX_COUNT; i++) {
2829                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2830                                 pwrinfo24g.cck_diff[rf_path][i];
2831                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2832                                 pwrinfo24g.ofdm_diff[rf_path][i];
2833                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2834                                 pwrinfo24g.bw20_diff[rf_path][i];
2835                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2836                                 pwrinfo24g.bw40_diff[rf_path][i];
2837
2838                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2839                                 pwrinfo5g.ofdm_diff[rf_path][i];
2840                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2841                                 pwrinfo5g.bw20_diff[rf_path][i];
2842                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2843                                 pwrinfo5g.bw40_diff[rf_path][i];
2844                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2845                                 pwrinfo5g.bw80_diff[rf_path][i];
2846                 }
2847         }
2848
2849         if (!autoload_fail) {
2850                 rtlefuse->eeprom_regulatory =
2851                         hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2852                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2853                         rtlefuse->eeprom_regulatory = 0;
2854         } else {
2855                 rtlefuse->eeprom_regulatory = 0;
2856         }
2857
2858         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2859         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2860 }
2861 #endif
2862 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2863                                                  bool autoload_fail,
2864                                                  u8 *hwinfo)
2865 {
2866         struct rtl_priv *rtlpriv = rtl_priv(hw);
2867         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2868         struct txpower_info_2g pwrinfo24g;
2869         struct txpower_info_5g pwrinfo5g;
2870         u8 rf_path, index;
2871         u8 i;
2872
2873         _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2874                 &pwrinfo5g, autoload_fail, hwinfo);
2875
2876         for (rf_path = 0; rf_path < 2; rf_path++) {
2877                 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2878                         index = _rtl8821ae_get_chnl_group(i + 1);
2879
2880                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2881                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2882                                         pwrinfo24g.index_cck_base[rf_path][5];
2883                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2884                                         pwrinfo24g.index_bw40_base[rf_path][index];
2885                         } else {
2886                                 rtlefuse->txpwrlevel_cck[rf_path][i] =
2887                                         pwrinfo24g.index_cck_base[rf_path][index];
2888                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2889                                         pwrinfo24g.index_bw40_base[rf_path][index];
2890                         }
2891                 }
2892
2893                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2894                         index = _rtl8821ae_get_chnl_group(channel5g[i]);
2895                         rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2896                                 pwrinfo5g.index_bw40_base[rf_path][index];
2897                 }
2898                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2899                         u8 upper, lower;
2900                         index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2901                         upper = pwrinfo5g.index_bw40_base[rf_path][index];
2902                         lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2903
2904                         rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2905                 }
2906                 for (i = 0; i < MAX_TX_COUNT; i++) {
2907                         rtlefuse->txpwr_cckdiff[rf_path][i] =
2908                                 pwrinfo24g.cck_diff[rf_path][i];
2909                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2910                                 pwrinfo24g.ofdm_diff[rf_path][i];
2911                         rtlefuse->txpwr_ht20diff[rf_path][i] =
2912                                 pwrinfo24g.bw20_diff[rf_path][i];
2913                         rtlefuse->txpwr_ht40diff[rf_path][i] =
2914                                 pwrinfo24g.bw40_diff[rf_path][i];
2915
2916                         rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2917                                 pwrinfo5g.ofdm_diff[rf_path][i];
2918                         rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2919                                 pwrinfo5g.bw20_diff[rf_path][i];
2920                         rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2921                                 pwrinfo5g.bw40_diff[rf_path][i];
2922                         rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2923                                 pwrinfo5g.bw80_diff[rf_path][i];
2924                 }
2925         }
2926         /*bit0~2*/
2927         if (!autoload_fail) {
2928                 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2929                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2930                         rtlefuse->eeprom_regulatory = 0;
2931         } else {
2932                 rtlefuse->eeprom_regulatory = 0;
2933         }
2934
2935         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2936         "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2937 }
2938
2939 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2940                                     bool autoload_fail)
2941 {
2942         struct rtl_priv *rtlpriv = rtl_priv(hw);
2943         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2944
2945         if (!autoload_fail) {
2946                 rtlhal->pa_type_2g = hwinfo[0xBC];
2947                 rtlhal->lna_type_2g = hwinfo[0xBD];
2948                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2949                         rtlhal->pa_type_2g = 0;
2950                         rtlhal->lna_type_2g = 0;
2951                 }
2952                 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2953                                           (rtlhal->pa_type_2g & BIT(4))) ?
2954                                          1 : 0;
2955                 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2956                                            (rtlhal->lna_type_2g & BIT(3))) ?
2957                                           1 : 0;
2958
2959                 rtlhal->pa_type_5g = hwinfo[0xBC];
2960                 rtlhal->lna_type_5g = hwinfo[0xBF];
2961                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2962                         rtlhal->pa_type_5g = 0;
2963                         rtlhal->lna_type_5g = 0;
2964                 }
2965                 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2966                                           (rtlhal->pa_type_5g & BIT(0))) ?
2967                                          1 : 0;
2968                 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2969                                            (rtlhal->lna_type_5g & BIT(3))) ?
2970                                           1 : 0;
2971         } else {
2972                 rtlhal->external_pa_2g  = 0;
2973                 rtlhal->external_lna_2g = 0;
2974                 rtlhal->external_pa_5g  = 0;
2975                 rtlhal->external_lna_5g = 0;
2976         }
2977 }
2978
2979 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2980                                     bool autoload_fail)
2981 {
2982         struct rtl_priv *rtlpriv = rtl_priv(hw);
2983         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2984
2985         if (!autoload_fail) {
2986                 rtlhal->pa_type_2g = hwinfo[0xBC];
2987                 rtlhal->lna_type_2g = hwinfo[0xBD];
2988                 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2989                         rtlhal->pa_type_2g = 0;
2990                         rtlhal->lna_type_2g = 0;
2991                 }
2992                 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2993                 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2994
2995                 rtlhal->pa_type_5g = hwinfo[0xBC];
2996                 rtlhal->lna_type_5g = hwinfo[0xBF];
2997                 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2998                         rtlhal->pa_type_5g = 0;
2999                         rtlhal->lna_type_5g = 0;
3000                 }
3001                 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3002                 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3003         } else {
3004                 rtlhal->external_pa_2g  = 0;
3005                 rtlhal->external_lna_2g = 0;
3006                 rtlhal->external_pa_5g  = 0;
3007                 rtlhal->external_lna_5g = 0;
3008         }
3009 }
3010
3011 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3012                               bool autoload_fail)
3013 {
3014         struct rtl_priv *rtlpriv = rtl_priv(hw);
3015         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3016
3017         if (!autoload_fail) {
3018                 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3019                         if (rtlhal->external_lna_5g) {
3020                                 if (rtlhal->external_pa_5g) {
3021                                         if (rtlhal->external_lna_2g &&
3022                                             rtlhal->external_pa_2g)
3023                                                 rtlhal->rfe_type = 3;
3024                                         else
3025                                                 rtlhal->rfe_type = 0;
3026                                 } else {
3027                                         rtlhal->rfe_type = 2;
3028                                 }
3029                         } else {
3030                                 rtlhal->rfe_type = 4;
3031                         }
3032                 } else {
3033                         rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3034
3035                         if (rtlhal->rfe_type == 4 &&
3036                             (rtlhal->external_pa_5g ||
3037                              rtlhal->external_pa_2g ||
3038                              rtlhal->external_lna_5g ||
3039                              rtlhal->external_lna_2g)) {
3040                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3041                                         rtlhal->rfe_type = 2;
3042                         }
3043                 }
3044         } else {
3045                 rtlhal->rfe_type = 0x04;
3046         }
3047
3048         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3049                  "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3050 }
3051
3052 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3053                                               bool auto_load_fail, u8 *hwinfo)
3054 {
3055         struct rtl_priv *rtlpriv = rtl_priv(hw);
3056         u8 value;
3057
3058         if (!auto_load_fail) {
3059                 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3060                 if (((value & 0xe0) >> 5) == 0x1)
3061                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3062                 else
3063                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3064                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3065
3066                 value = hwinfo[EEPROM_RF_BT_SETTING];
3067                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3068         } else {
3069                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3070                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3071                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3072         }
3073         /*move BT_InitHalVars() to init_sw_vars*/
3074 }
3075
3076 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3077                                               bool auto_load_fail, u8 *hwinfo)
3078 {
3079         struct rtl_priv *rtlpriv = rtl_priv(hw);
3080         u8 value;
3081         u32 tmpu_32;
3082
3083         if (!auto_load_fail) {
3084                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3085                 if (tmpu_32 & BIT(18))
3086                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
3087                 else
3088                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
3089                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3090
3091                 value = hwinfo[EEPROM_RF_BT_SETTING];
3092                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3093         } else {
3094                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3095                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3096                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3097         }
3098         /*move BT_InitHalVars() to init_sw_vars*/
3099 }
3100
3101 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3102 {
3103         struct rtl_priv *rtlpriv = rtl_priv(hw);
3104         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3105         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3106         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3107         int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3108                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3109                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3110                         COUNTRY_CODE_WORLD_WIDE_13};
3111         u8 *hwinfo;
3112
3113         if (b_pseudo_test) {
3114                 ;/* need add */
3115         }
3116
3117         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3118         if (!hwinfo)
3119                 return;
3120
3121         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3122                 goto exit;
3123
3124         _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3125                                                hwinfo);
3126
3127         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3128                 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3129                 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3130                                 rtlefuse->autoload_failflag, hwinfo);
3131         } else {
3132                 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3133                 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3134                                 rtlefuse->autoload_failflag, hwinfo);
3135         }
3136
3137         _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3138         /*board type*/
3139         rtlefuse->board_type = ODM_BOARD_DEFAULT;
3140         if (rtlhal->external_lna_2g != 0)
3141                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3142         if (rtlhal->external_lna_5g != 0)
3143                 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3144         if (rtlhal->external_pa_2g != 0)
3145                 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3146         if (rtlhal->external_pa_5g != 0)
3147                 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3148
3149         if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3150                 rtlefuse->board_type |= ODM_BOARD_BT;
3151
3152         rtlhal->board_type = rtlefuse->board_type;
3153         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3154                  "board_type = 0x%x\n", rtlefuse->board_type);
3155
3156         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3157         if (rtlefuse->eeprom_channelplan == 0xff)
3158                 rtlefuse->eeprom_channelplan = 0x7F;
3159
3160         /* set channel plan from efuse */
3161         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3162
3163         /*parse xtal*/
3164         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3165         if (rtlefuse->crystalcap == 0xFF)
3166                 rtlefuse->crystalcap = 0x20;
3167
3168         rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3169         if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3170             rtlefuse->autoload_failflag) {
3171                 rtlefuse->apk_thermalmeterignore = true;
3172                 rtlefuse->eeprom_thermalmeter = 0xff;
3173         }
3174
3175         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3176         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3177                  "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3178
3179         if (!rtlefuse->autoload_failflag) {
3180                 rtlefuse->antenna_div_cfg =
3181                   (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3182                 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3183                         rtlefuse->antenna_div_cfg = 0;
3184
3185                 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3186                     rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3187                         rtlefuse->antenna_div_cfg = 0;
3188
3189                 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3190                 if (rtlefuse->antenna_div_type == 0xff)
3191                         rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3192         } else {
3193                 rtlefuse->antenna_div_cfg = 0;
3194                 rtlefuse->antenna_div_type = 0;
3195         }
3196
3197         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3198                 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3199                 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3200
3201         pcipriv->ledctl.led_opendrain = true;
3202
3203         if (rtlhal->oem_id == RT_CID_DEFAULT) {
3204                 switch (rtlefuse->eeprom_oemid) {
3205                 case RT_CID_DEFAULT:
3206                         break;
3207                 case EEPROM_CID_TOSHIBA:
3208                         rtlhal->oem_id = RT_CID_TOSHIBA;
3209                         break;
3210                 case EEPROM_CID_CCX:
3211                         rtlhal->oem_id = RT_CID_CCX;
3212                         break;
3213                 case EEPROM_CID_QMI:
3214                         rtlhal->oem_id = RT_CID_819X_QMI;
3215                         break;
3216                 case EEPROM_CID_WHQL:
3217                         break;
3218                 default:
3219                         break;
3220                 }
3221         }
3222 exit:
3223         kfree(hwinfo);
3224 }
3225
3226 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3227 {
3228         struct rtl_priv *rtlpriv = rtl_priv(hw);
3229         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3230         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3231
3232         pcipriv->ledctl.led_opendrain = true;
3233         switch (rtlhal->oem_id) {
3234         case RT_CID_819X_HP:
3235                 pcipriv->ledctl.led_opendrain = true;
3236                 break;
3237         case RT_CID_819X_LENOVO:
3238         case RT_CID_DEFAULT:
3239         case RT_CID_TOSHIBA:
3240         case RT_CID_CCX:
3241         case RT_CID_819X_ACER:
3242         case RT_CID_WHQL:
3243         default:
3244                 break;
3245         }
3246         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3247                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3248 }*/
3249
3250 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3251 {
3252         struct rtl_priv *rtlpriv = rtl_priv(hw);
3253         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3254         struct rtl_phy *rtlphy = &rtlpriv->phy;
3255         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3256         u8 tmp_u1b;
3257
3258         rtlhal->version = _rtl8821ae_read_chip_version(hw);
3259         if (get_rf_type(rtlphy) == RF_1T1R)
3260                 rtlpriv->dm.rfpath_rxenable[0] = true;
3261         else
3262                 rtlpriv->dm.rfpath_rxenable[0] =
3263                     rtlpriv->dm.rfpath_rxenable[1] = true;
3264         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3265                                                 rtlhal->version);
3266
3267         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3268         if (tmp_u1b & BIT(4)) {
3269                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3270                 rtlefuse->epromtype = EEPROM_93C46;
3271         } else {
3272                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3273                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3274         }
3275
3276         if (tmp_u1b & BIT(5)) {
3277                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3278                 rtlefuse->autoload_failflag = false;
3279                 _rtl8821ae_read_adapter_info(hw, false);
3280         } else {
3281                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3282         }
3283         /*hal_ReadRFType_8812A()*/
3284         /* _rtl8821ae_hal_customized_behavior(hw); */
3285 }
3286
3287 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3288                 struct ieee80211_sta *sta)
3289 {
3290         struct rtl_priv *rtlpriv = rtl_priv(hw);
3291         struct rtl_phy *rtlphy = &rtlpriv->phy;
3292         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3293         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3294         u32 ratr_value;
3295         u8 ratr_index = 0;
3296         u8 b_nmode = mac->ht_enable;
3297         u8 mimo_ps = IEEE80211_SMPS_OFF;
3298         u16 shortgi_rate;
3299         u32 tmp_ratr_value;
3300         u8 curtxbw_40mhz = mac->bw_40;
3301         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3302                                 1 : 0;
3303         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3304                                 1 : 0;
3305         enum wireless_mode wirelessmode = mac->mode;
3306
3307         if (rtlhal->current_bandtype == BAND_ON_5G)
3308                 ratr_value = sta->supp_rates[1] << 4;
3309         else
3310                 ratr_value = sta->supp_rates[0];
3311         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3312                 ratr_value = 0xfff;
3313         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3314                         sta->ht_cap.mcs.rx_mask[0] << 12);
3315         switch (wirelessmode) {
3316         case WIRELESS_MODE_B:
3317                 if (ratr_value & 0x0000000c)
3318                         ratr_value &= 0x0000000d;
3319                 else
3320                         ratr_value &= 0x0000000f;
3321                 break;
3322         case WIRELESS_MODE_G:
3323                 ratr_value &= 0x00000FF5;
3324                 break;
3325         case WIRELESS_MODE_N_24G:
3326         case WIRELESS_MODE_N_5G:
3327                 b_nmode = 1;
3328                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3329                         ratr_value &= 0x0007F005;
3330                 } else {
3331                         u32 ratr_mask;
3332
3333                         if (get_rf_type(rtlphy) == RF_1T2R ||
3334                             get_rf_type(rtlphy) == RF_1T1R)
3335                                 ratr_mask = 0x000ff005;
3336                         else
3337                                 ratr_mask = 0x0f0ff005;
3338
3339                         ratr_value &= ratr_mask;
3340                 }
3341                 break;
3342         default:
3343                 if (rtlphy->rf_type == RF_1T2R)
3344                         ratr_value &= 0x000ff0ff;
3345                 else
3346                         ratr_value &= 0x0f0ff0ff;
3347
3348                 break;
3349         }
3350
3351         if ((rtlpriv->btcoexist.bt_coexistence) &&
3352              (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3353              (rtlpriv->btcoexist.bt_cur_state) &&
3354              (rtlpriv->btcoexist.bt_ant_isolation) &&
3355              ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3356              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3357                 ratr_value &= 0x0fffcfc0;
3358         else
3359                 ratr_value &= 0x0FFFFFFF;
3360
3361         if (b_nmode && ((curtxbw_40mhz &&
3362                          b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3363                                                  b_curshortgi_20mhz))) {
3364                 ratr_value |= 0x10000000;
3365                 tmp_ratr_value = (ratr_value >> 12);
3366
3367                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3368                         if ((1 << shortgi_rate) & tmp_ratr_value)
3369                                 break;
3370                 }
3371
3372                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3373                     (shortgi_rate << 4) | (shortgi_rate);
3374         }
3375
3376         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3377
3378         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3379                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3380 }
3381
3382 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3383         struct ieee80211_hw *hw, u8 rate_index,
3384         enum wireless_mode wirelessmode)
3385 {
3386         struct rtl_priv *rtlpriv = rtl_priv(hw);
3387         struct rtl_phy *rtlphy = &rtlpriv->phy;
3388         u8 ret = 0;
3389         switch (rate_index) {
3390         case RATR_INX_WIRELESS_NGB:
3391                 if (rtlphy->rf_type == RF_1T1R)
3392                         ret = 1;
3393                 else
3394                         ret = 0;
3395                 ; break;
3396         case RATR_INX_WIRELESS_N:
3397         case RATR_INX_WIRELESS_NG:
3398                 if (rtlphy->rf_type == RF_1T1R)
3399                         ret = 5;
3400                 else
3401                         ret = 4;
3402                 ; break;
3403         case RATR_INX_WIRELESS_NB:
3404                 if (rtlphy->rf_type == RF_1T1R)
3405                         ret = 3;
3406                 else
3407                         ret = 2;
3408                 ; break;
3409         case RATR_INX_WIRELESS_GB:
3410                 ret = 6;
3411                 break;
3412         case RATR_INX_WIRELESS_G:
3413                 ret = 7;
3414                 break;
3415         case RATR_INX_WIRELESS_B:
3416                 ret = 8;
3417                 break;
3418         case RATR_INX_WIRELESS_MC:
3419                 if ((wirelessmode == WIRELESS_MODE_B)
3420                         || (wirelessmode == WIRELESS_MODE_G)
3421                         || (wirelessmode == WIRELESS_MODE_N_24G)
3422                         || (wirelessmode == WIRELESS_MODE_AC_24G))
3423                         ret = 6;
3424                 else
3425                         ret = 7;
3426         case RATR_INX_WIRELESS_AC_5N:
3427                 if (rtlphy->rf_type == RF_1T1R)
3428                         ret = 10;
3429                 else
3430                         ret = 9;
3431                 break;
3432         case RATR_INX_WIRELESS_AC_24N:
3433                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3434                         if (rtlphy->rf_type == RF_1T1R)
3435                                 ret = 10;
3436                         else
3437                                 ret = 9;
3438                 } else {
3439                         if (rtlphy->rf_type == RF_1T1R)
3440                                 ret = 11;
3441                         else
3442                                 ret = 12;
3443                 }
3444                 break;
3445         default:
3446                 ret = 0; break;
3447         }
3448         return ret;
3449 }
3450
3451 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3452 {
3453         u8 i, j, tmp_rate;
3454         u32 rate_bitmap = 0;
3455
3456         for (i = j = 0; i < 4; i += 2, j += 10) {
3457                 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3458
3459                 switch (tmp_rate) {
3460                 case 2:
3461                         rate_bitmap = rate_bitmap | (0x03ff << j);
3462                         break;
3463                 case 1:
3464                         rate_bitmap = rate_bitmap | (0x01ff << j);
3465                         break;
3466                 case 0:
3467                         rate_bitmap = rate_bitmap | (0x00ff << j);
3468                         break;
3469                 default:
3470                         break;
3471                 }
3472         }
3473
3474         return rate_bitmap;
3475 }
3476
3477 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3478                                              enum wireless_mode wirelessmode,
3479                                              u32 ratr_bitmap)
3480 {
3481         struct rtl_priv *rtlpriv = rtl_priv(hw);
3482         struct rtl_phy *rtlphy = &rtlpriv->phy;
3483         u32 ret_bitmap = ratr_bitmap;
3484
3485         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3486                 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3487                 ret_bitmap = ratr_bitmap;
3488         else if (wirelessmode == WIRELESS_MODE_AC_5G
3489                 || wirelessmode == WIRELESS_MODE_AC_24G) {
3490                 if (rtlphy->rf_type == RF_1T1R)
3491                         ret_bitmap = ratr_bitmap & (~BIT21);
3492                 else
3493                         ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3494         }
3495
3496         return ret_bitmap;
3497 }
3498
3499 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3500                         u32 ratr_bitmap)
3501 {
3502         u8 ret = 0;
3503         if (wirelessmode < WIRELESS_MODE_N_24G)
3504                 ret =  0;
3505         else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3506                 if (ratr_bitmap & 0xfff00000)   /* Mix , 2SS */
3507                         ret = 3;
3508                 else                                    /* Mix, 1SS */
3509                         ret = 2;
3510         } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3511                         ret = 1;
3512         } /* VHT */
3513
3514         return ret << 4;
3515 }
3516
3517 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3518                              u8 mac_id, struct rtl_sta_info *sta_entry,
3519                              enum wireless_mode wirelessmode)
3520 {
3521         u8 b_ldpc = 0;
3522         /*not support ldpc, do not open*/
3523         return b_ldpc << 2;
3524 }
3525
3526 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3527                           enum wireless_mode wirelessmode,
3528                           u32 ratr_bitmap)
3529 {
3530         struct rtl_priv *rtlpriv = rtl_priv(hw);
3531         struct rtl_phy *rtlphy = &rtlpriv->phy;
3532         u8 rf_type = RF_1T1R;
3533
3534         if (rtlphy->rf_type == RF_1T1R)
3535                 rf_type = RF_1T1R;
3536         else if (wirelessmode == WIRELESS_MODE_AC_5G
3537                 || wirelessmode == WIRELESS_MODE_AC_24G
3538                 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3539                 if (ratr_bitmap & 0xffc00000)
3540                         rf_type = RF_2T2R;
3541         } else if (wirelessmode == WIRELESS_MODE_N_5G
3542                 || wirelessmode == WIRELESS_MODE_N_24G) {
3543                 if (ratr_bitmap & 0xfff00000)
3544                         rf_type = RF_2T2R;
3545         }
3546
3547         return rf_type;
3548 }
3549
3550 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3551                               u8 mac_id)
3552 {
3553         bool b_short_gi = false;
3554         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3555                                 1 : 0;
3556         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3557                                 1 : 0;
3558         u8 b_curshortgi_80mhz = 0;
3559         b_curshortgi_80mhz = (sta->vht_cap.cap &
3560                               IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3561
3562         if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3563                         b_short_gi = false;
3564
3565         if (b_curshortgi_40mhz || b_curshortgi_80mhz
3566                 || b_curshortgi_20mhz)
3567                 b_short_gi = true;
3568
3569         return b_short_gi;
3570 }
3571
3572 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3573                 struct ieee80211_sta *sta, u8 rssi_level)
3574 {
3575         struct rtl_priv *rtlpriv = rtl_priv(hw);
3576         struct rtl_phy *rtlphy = &rtlpriv->phy;
3577         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3578         struct rtl_sta_info *sta_entry = NULL;
3579         u32 ratr_bitmap;
3580         u8 ratr_index;
3581         enum wireless_mode wirelessmode = 0;
3582         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3583                                 ? 1 : 0;
3584         bool b_shortgi = false;
3585         u8 rate_mask[7];
3586         u8 macid = 0;
3587         u8 mimo_ps = IEEE80211_SMPS_OFF;
3588         u8 rf_type;
3589
3590         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3591         wirelessmode = sta_entry->wireless_mode;
3592
3593         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3594                  "wireless mode = 0x%x\n", wirelessmode);
3595         if (mac->opmode == NL80211_IFTYPE_STATION ||
3596                 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3597                 curtxbw_40mhz = mac->bw_40;
3598         } else if (mac->opmode == NL80211_IFTYPE_AP ||
3599                 mac->opmode == NL80211_IFTYPE_ADHOC)
3600                 macid = sta->aid + 1;
3601         if (wirelessmode == WIRELESS_MODE_N_5G ||
3602             wirelessmode == WIRELESS_MODE_AC_5G ||
3603             wirelessmode == WIRELESS_MODE_A)
3604                 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3605         else
3606                 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3607
3608         if (mac->opmode == NL80211_IFTYPE_ADHOC)
3609                 ratr_bitmap = 0xfff;
3610
3611         if (wirelessmode == WIRELESS_MODE_N_24G
3612                 || wirelessmode == WIRELESS_MODE_N_5G)
3613                 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3614                                 sta->ht_cap.mcs.rx_mask[0] << 12);
3615         else if (wirelessmode == WIRELESS_MODE_AC_24G
3616                 || wirelessmode == WIRELESS_MODE_AC_5G
3617                 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3618                 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3619                                 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3620
3621         b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3622         rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3623
3624 /*mac id owner*/
3625         switch (wirelessmode) {
3626         case WIRELESS_MODE_B:
3627                 ratr_index = RATR_INX_WIRELESS_B;
3628                 if (ratr_bitmap & 0x0000000c)
3629                         ratr_bitmap &= 0x0000000d;
3630                 else
3631                         ratr_bitmap &= 0x0000000f;
3632                 break;
3633         case WIRELESS_MODE_G:
3634                 ratr_index = RATR_INX_WIRELESS_GB;
3635
3636                 if (rssi_level == 1)
3637                         ratr_bitmap &= 0x00000f00;
3638                 else if (rssi_level == 2)
3639                         ratr_bitmap &= 0x00000ff0;
3640                 else
3641                         ratr_bitmap &= 0x00000ff5;
3642                 break;
3643         case WIRELESS_MODE_A:
3644                 ratr_index = RATR_INX_WIRELESS_G;
3645                 ratr_bitmap &= 0x00000ff0;
3646                 break;
3647         case WIRELESS_MODE_N_24G:
3648         case WIRELESS_MODE_N_5G:
3649                 if (wirelessmode == WIRELESS_MODE_N_24G)
3650                         ratr_index = RATR_INX_WIRELESS_NGB;
3651                 else
3652                         ratr_index = RATR_INX_WIRELESS_NG;
3653
3654                 if (mimo_ps == IEEE80211_SMPS_STATIC
3655                         || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3656                         if (rssi_level == 1)
3657                                 ratr_bitmap &= 0x000f0000;
3658                         else if (rssi_level == 2)
3659                                 ratr_bitmap &= 0x000ff000;
3660                         else
3661                                 ratr_bitmap &= 0x000ff005;
3662                 } else {
3663                         if (rf_type == RF_1T1R) {
3664                                 if (curtxbw_40mhz) {
3665                                         if (rssi_level == 1)
3666                                                 ratr_bitmap &= 0x000f0000;
3667                                         else if (rssi_level == 2)
3668                                                 ratr_bitmap &= 0x000ff000;
3669                                         else
3670                                                 ratr_bitmap &= 0x000ff015;
3671                                 } else {
3672                                         if (rssi_level == 1)
3673                                                 ratr_bitmap &= 0x000f0000;
3674                                         else if (rssi_level == 2)
3675                                                 ratr_bitmap &= 0x000ff000;
3676                                         else
3677                                                 ratr_bitmap &= 0x000ff005;
3678                                 }
3679                         } else {
3680                                 if (curtxbw_40mhz) {
3681                                         if (rssi_level == 1)
3682                                                 ratr_bitmap &= 0x0fff0000;
3683                                         else if (rssi_level == 2)
3684                                                 ratr_bitmap &= 0x0ffff000;
3685                                         else
3686                                                 ratr_bitmap &= 0x0ffff015;
3687                                 } else {
3688                                         if (rssi_level == 1)
3689                                                 ratr_bitmap &= 0x0fff0000;
3690                                         else if (rssi_level == 2)
3691                                                 ratr_bitmap &= 0x0ffff000;
3692                                         else
3693                                                 ratr_bitmap &= 0x0ffff005;
3694                                 }
3695                         }
3696                 }
3697                 break;
3698
3699         case WIRELESS_MODE_AC_24G:
3700                 ratr_index = RATR_INX_WIRELESS_AC_24N;
3701                 if (rssi_level == 1)
3702                         ratr_bitmap &= 0xfc3f0000;
3703                 else if (rssi_level == 2)
3704                         ratr_bitmap &= 0xfffff000;
3705                 else
3706                         ratr_bitmap &= 0xffffffff;
3707                 break;
3708
3709         case WIRELESS_MODE_AC_5G:
3710                 ratr_index = RATR_INX_WIRELESS_AC_5N;
3711
3712                 if (rf_type == RF_1T1R) {
3713                         if (rssi_level == 1)    /*add by Gary for ac-series*/
3714                                 ratr_bitmap &= 0x003f8000;
3715                         else if (rssi_level == 2)
3716                                 ratr_bitmap &= 0x003ff000;
3717                         else
3718                                 ratr_bitmap &= 0x003ff010;
3719                 } else {
3720                         if (rssi_level == 1)
3721                                 ratr_bitmap &= 0xfe3f8000;
3722                         else if (rssi_level == 2)
3723                                 ratr_bitmap &= 0xfffff000;
3724                         else
3725                                 ratr_bitmap &= 0xfffff010;
3726                 }
3727                 break;
3728
3729         default:
3730                 ratr_index = RATR_INX_WIRELESS_NGB;
3731
3732                 if (rf_type == RF_1T2R)
3733                         ratr_bitmap &= 0x000ff0ff;
3734                 else
3735                         ratr_bitmap &= 0x0f8ff0ff;
3736                 break;
3737         }
3738
3739         ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3740         sta_entry->ratr_index = ratr_index;
3741         ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3742                                                         ratr_bitmap);
3743
3744         RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3745                  "ratr_bitmap :%x\n", ratr_bitmap);
3746
3747         /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3748                                        (ratr_index << 28)); */
3749
3750         rate_mask[0] = macid;
3751         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3752         rate_mask[2] = rtlphy->current_chan_bw
3753                            | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3754                            | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3755
3756         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3757         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3758         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3759         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3760
3761         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3762                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3763                  ratr_index, ratr_bitmap,
3764                  rate_mask[0], rate_mask[1],
3765                  rate_mask[2], rate_mask[3],
3766                  rate_mask[4], rate_mask[5],
3767                  rate_mask[6]);
3768         rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3769         _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3770 }
3771
3772 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3773                 struct ieee80211_sta *sta, u8 rssi_level)
3774 {
3775         struct rtl_priv *rtlpriv = rtl_priv(hw);
3776         if (rtlpriv->dm.useramask)
3777                 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3778         else
3779                 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3780                            "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3781                 rtl8821ae_update_hal_rate_table(hw, sta);
3782 }
3783
3784 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3785 {
3786         struct rtl_priv *rtlpriv = rtl_priv(hw);
3787         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3788         u16 wireless_mode = mac->mode;
3789         u8 sifs_timer, r2t_sifs;
3790
3791         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3792                                       (u8 *)&mac->slot_time);
3793         if (wireless_mode == WIRELESS_MODE_G)
3794                 sifs_timer = 0x0a;
3795         else
3796                 sifs_timer = 0x0e;
3797         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3798
3799         r2t_sifs = 0xa;
3800
3801         if (wireless_mode == WIRELESS_MODE_AC_5G &&
3802             (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3803             (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3804                 if (mac->vendor == PEER_ATH)
3805                         r2t_sifs = 0x8;
3806                 else
3807                         r2t_sifs = 0xa;
3808         } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3809                 r2t_sifs = 0xa;
3810         }
3811
3812         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3813 }
3814
3815 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3816 {
3817         struct rtl_priv *rtlpriv = rtl_priv(hw);
3818         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3819         struct rtl_phy *rtlphy = &rtlpriv->phy;
3820         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3821         u8 u1tmp = 0;
3822         bool b_actuallyset = false;
3823
3824         if (rtlpriv->rtlhal.being_init_adapter)
3825                 return false;
3826
3827         if (ppsc->swrf_processing)
3828                 return false;
3829
3830         spin_lock(&rtlpriv->locks.rf_ps_lock);
3831         if (ppsc->rfchange_inprogress) {
3832                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3833                 return false;
3834         } else {
3835                 ppsc->rfchange_inprogress = true;
3836                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3837         }
3838
3839         cur_rfstate = ppsc->rfpwr_state;
3840
3841         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3842                         rtl_read_byte(rtlpriv,
3843                                         REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3844
3845         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3846
3847         if (rtlphy->polarity_ctl)
3848                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3849         else
3850                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3851
3852         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3853                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3854                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
3855
3856                 e_rfpowerstate_toset = ERFON;
3857                 ppsc->hwradiooff = false;
3858                 b_actuallyset = true;
3859         } else if ((!ppsc->hwradiooff)
3860                    && (e_rfpowerstate_toset == ERFOFF)) {
3861                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3862                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3863
3864                 e_rfpowerstate_toset = ERFOFF;
3865                 ppsc->hwradiooff = true;
3866                 b_actuallyset = true;
3867         }
3868
3869         if (b_actuallyset) {
3870                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3871                 ppsc->rfchange_inprogress = false;
3872                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3873         } else {
3874                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3875                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3876
3877                 spin_lock(&rtlpriv->locks.rf_ps_lock);
3878                 ppsc->rfchange_inprogress = false;
3879                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3880         }
3881
3882         *valid = 1;
3883         return !ppsc->hwradiooff;
3884 }
3885
3886 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3887                      u8 *p_macaddr, bool is_group, u8 enc_algo,
3888                      bool is_wepkey, bool clear_all)
3889 {
3890         struct rtl_priv *rtlpriv = rtl_priv(hw);
3891         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3892         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3893         u8 *macaddr = p_macaddr;
3894         u32 entry_id = 0;
3895         bool is_pairwise = false;
3896
3897         static u8 cam_const_addr[4][6] = {
3898                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3899                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3900                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3901                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3902         };
3903         static u8 cam_const_broad[] = {
3904                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3905         };
3906
3907         if (clear_all) {
3908                 u8 idx = 0;
3909                 u8 cam_offset = 0;
3910                 u8 clear_number = 5;
3911
3912                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3913
3914                 for (idx = 0; idx < clear_number; idx++) {
3915                         rtl_cam_mark_invalid(hw, cam_offset + idx);
3916                         rtl_cam_empty_entry(hw, cam_offset + idx);
3917
3918                         if (idx < 5) {
3919                                 memset(rtlpriv->sec.key_buf[idx], 0,
3920                                        MAX_KEY_LEN);
3921                                 rtlpriv->sec.key_len[idx] = 0;
3922                         }
3923                 }
3924         } else {
3925                 switch (enc_algo) {
3926                 case WEP40_ENCRYPTION:
3927                         enc_algo = CAM_WEP40;
3928                         break;
3929                 case WEP104_ENCRYPTION:
3930                         enc_algo = CAM_WEP104;
3931                         break;
3932                 case TKIP_ENCRYPTION:
3933                         enc_algo = CAM_TKIP;
3934                         break;
3935                 case AESCCMP_ENCRYPTION:
3936                         enc_algo = CAM_AES;
3937                         break;
3938                 default:
3939                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3940                                  "switch case %#x not processed\n", enc_algo);
3941                         enc_algo = CAM_TKIP;
3942                         break;
3943                 }
3944
3945                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3946                         macaddr = cam_const_addr[key_index];
3947                         entry_id = key_index;
3948                 } else {
3949                         if (is_group) {
3950                                 macaddr = cam_const_broad;
3951                                 entry_id = key_index;
3952                         } else {
3953                                 if (mac->opmode == NL80211_IFTYPE_AP) {
3954                                         entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3955                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
3956                                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
3957                                                          "Can not find free hwsecurity cam entry\n");
3958                                                 return;
3959                                         }
3960                                 } else {
3961                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
3962                                 }
3963
3964                                 key_index = PAIRWISE_KEYIDX;
3965                                 is_pairwise = true;
3966                         }
3967                 }
3968
3969                 if (rtlpriv->sec.key_len[key_index] == 0) {
3970                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3971                                  "delete one entry, entry_id is %d\n",
3972                                  entry_id);
3973                         if (mac->opmode == NL80211_IFTYPE_AP)
3974                                 rtl_cam_del_entry(hw, p_macaddr);
3975                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3976                 } else {
3977                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3978                                  "add one entry\n");
3979                         if (is_pairwise) {
3980                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3981                                          "set Pairwise key\n");
3982
3983                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
3984                                                       entry_id, enc_algo,
3985                                                       CAM_CONFIG_NO_USEDK,
3986                                                       rtlpriv->sec.key_buf[key_index]);
3987                         } else {
3988                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3989                                          "set group key\n");
3990
3991                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3992                                         rtl_cam_add_one_entry(hw,
3993                                                         rtlefuse->dev_addr,
3994                                                         PAIRWISE_KEYIDX,
3995                                                         CAM_PAIRWISE_KEY_POSITION,
3996                                                         enc_algo,
3997                                                         CAM_CONFIG_NO_USEDK,
3998                                                         rtlpriv->sec.key_buf
3999                                                         [entry_id]);
4000                                 }
4001
4002                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
4003                                                 entry_id, enc_algo,
4004                                                 CAM_CONFIG_NO_USEDK,
4005                                                 rtlpriv->sec.key_buf[entry_id]);
4006                         }
4007                 }
4008         }
4009 }
4010
4011 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4012 {
4013         struct rtl_priv *rtlpriv = rtl_priv(hw);
4014
4015         /* 0:Low, 1:High, 2:From Efuse. */
4016         rtlpriv->btcoexist.reg_bt_iso = 2;
4017         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4018         rtlpriv->btcoexist.reg_bt_sco = 3;
4019         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4020         rtlpriv->btcoexist.reg_bt_sco = 0;
4021 }
4022
4023 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4024 {
4025         struct rtl_priv *rtlpriv = rtl_priv(hw);
4026
4027         if (rtlpriv->cfg->ops->get_btc_status())
4028                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4029 }
4030
4031 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4032 {
4033 }
4034
4035 void rtl8821ae_resume(struct ieee80211_hw *hw)
4036 {
4037 }
4038
4039 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4040 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4041         bool allow_all_da, bool write_into_reg)
4042 {
4043         struct rtl_priv *rtlpriv = rtl_priv(hw);
4044         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4045
4046         if (allow_all_da) /* Set BIT0 */
4047                 rtlpci->receive_config |= RCR_AAP;
4048         else /* Clear BIT0 */
4049                 rtlpci->receive_config &= ~RCR_AAP;
4050
4051         if (write_into_reg)
4052                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4053
4054         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4055                 "receive_config=0x%08X, write_into_reg=%d\n",
4056                 rtlpci->receive_config, write_into_reg);
4057 }
4058
4059 /* WKFMCAMAddAllEntry8812 */
4060 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4061                                   struct rtl_wow_pattern *rtl_pattern,
4062                                   u8 index)
4063 {
4064         struct rtl_priv *rtlpriv = rtl_priv(hw);
4065         u32 cam = 0;
4066         u8 addr = 0;
4067         u16 rxbuf_addr;
4068         u8 tmp, count = 0;
4069         u16 cam_start;
4070         u16 offset;
4071
4072         /* Count the WFCAM entry start offset. */
4073
4074         /* RX page size = 128 byte */
4075         offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4076         /* We should start from the boundry */
4077         cam_start = offset * 128;
4078
4079         /* Enable Rx packet buffer access. */
4080         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4081         for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4082                 /* Set Rx packet buffer offset.
4083                  * RxBufer pointer increases 1,
4084                  * we can access 8 bytes in Rx packet buffer.
4085                  * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4086                  * RxBufer addr = (CAM start offset +
4087                  *                 per entry offset of a WKFM CAM)/8
4088                  *      * index: The index of the wake up frame mask
4089                  *      * WKFMCAM_SIZE: the total size of one WKFM CAM
4090                  *      * per entry offset of a WKFM CAM: Addr*4 bytes
4091                  */
4092                 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4093                 /* Set R/W start offset */
4094                 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4095
4096                 if (addr == 0) {
4097                         cam = BIT(31) | rtl_pattern->crc;
4098
4099                         if (rtl_pattern->type == UNICAST_PATTERN)
4100                                 cam |= BIT(24);
4101                         else if (rtl_pattern->type == MULTICAST_PATTERN)
4102                                 cam |= BIT(25);
4103                         else if (rtl_pattern->type == BROADCAST_PATTERN)
4104                                 cam |= BIT(26);
4105
4106                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4107                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4108                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4109                                   REG_PKTBUF_DBG_DATA_L, cam);
4110
4111                         /* Write to Rx packet buffer. */
4112                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4113                 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4114                         cam = rtl_pattern->mask[addr - 2];
4115
4116                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4117                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4118                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4119                                   REG_PKTBUF_DBG_DATA_L, cam);
4120
4121                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4122                 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4123                         cam = rtl_pattern->mask[addr - 2];
4124
4125                         rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4126                         RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4127                                  "WRITE entry[%d] 0x%x: %x\n", addr,
4128                                   REG_PKTBUF_DBG_DATA_H, cam);
4129
4130                         rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4131                 }
4132
4133                 count = 0;
4134                 do {
4135                         tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4136                         udelay(2);
4137                         count++;
4138                 } while (tmp && count < 100);
4139
4140                 RT_ASSERT((count < 100),
4141                           "Write wake up frame mask FAIL %d value!\n", tmp);
4142         }
4143         /* Disable Rx packet buffer access. */
4144         rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4145                        DISABLE_TRXPKT_BUF_ACCESS);
4146 }