1 /******************************************************************************
3 * Copyright(c) 2009-2014 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
36 #include "../rtl8723com/phy_common.h"
38 #include "../rtl8723com/dm_common.h"
40 #include "../rtl8723com/fw_common.h"
43 #include "../pwrseqcmd.h"
45 #include "../btcoexist/rtl_btc.h"
49 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
56 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
57 while (skb_queue_len(&ring->queue)) {
58 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
59 struct sk_buff *skb = __skb_dequeue(&ring->queue);
61 pci_unmap_single(rtlpci->pdev,
62 rtlpriv->cfg->ops->get_desc(
63 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
64 skb->len, PCI_DMA_TODEVICE);
66 ring->idx = (ring->idx + 1) % ring->entries;
68 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
71 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
72 u8 set_bits, u8 clear_bits)
74 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 rtlpci->reg_bcn_ctrl_val |= set_bits;
78 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
80 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
83 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
85 struct rtl_priv *rtlpriv = rtl_priv(hw);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
89 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
91 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
92 tmp1byte &= ~(BIT(0));
93 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
96 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
98 struct rtl_priv *rtlpriv = rtl_priv(hw);
101 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
102 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
104 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
106 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
109 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
111 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
114 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
116 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
119 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
120 bool b_need_turn_off_ckk)
122 struct rtl_priv *rtlpriv = rtl_priv(hw);
123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
124 bool b_support_remote_wake_up;
125 u32 count = 0, isr_regaddr, content;
126 bool b_schedule_timer = b_need_turn_off_ckk;
127 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
128 (u8 *)(&b_support_remote_wake_up));
130 if (!rtlhal->fw_ready)
132 if (!rtlpriv->psc.fw_current_inpsmode)
136 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
137 if (rtlhal->fw_clk_change_in_progress) {
138 while (rtlhal->fw_clk_change_in_progress) {
139 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
144 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
146 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
148 rtlhal->fw_clk_change_in_progress = false;
149 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
154 if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
155 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
157 if (FW_PS_IS_ACK(rpwm_val)) {
158 isr_regaddr = REG_HISR;
159 content = rtl_read_dword(rtlpriv, isr_regaddr);
160 while (!(content & IMR_CPWM) && (count < 500)) {
163 content = rtl_read_dword(rtlpriv, isr_regaddr);
166 if (content & IMR_CPWM) {
167 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
168 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
169 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
170 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
171 rtlhal->fw_ps_state);
175 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
176 rtlhal->fw_clk_change_in_progress = false;
177 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
178 if (b_schedule_timer)
179 mod_timer(&rtlpriv->works.fw_clockoff_timer,
180 jiffies + MSECS(10));
182 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
183 rtlhal->fw_clk_change_in_progress = false;
184 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
188 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
190 struct rtl_priv *rtlpriv = rtl_priv(hw);
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
193 struct rtl8192_tx_ring *ring;
194 enum rf_pwrstate rtstate;
195 bool b_schedule_timer = false;
198 if (!rtlhal->fw_ready)
200 if (!rtlpriv->psc.fw_current_inpsmode)
202 if (!rtlhal->allow_sw_to_change_hwclc)
204 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
205 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
208 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
209 ring = &rtlpci->tx_ring[queue];
210 if (skb_queue_len(&ring->queue)) {
211 b_schedule_timer = true;
216 if (b_schedule_timer) {
217 mod_timer(&rtlpriv->works.fw_clockoff_timer,
218 jiffies + MSECS(10));
222 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
243 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
246 rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
247 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
250 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255 bool fw_current_inps = false;
256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
258 if (ppsc->low_power_enable) {
259 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
260 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
261 rtlhal->allow_sw_to_change_hwclc = false;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
267 rpwm_val = FW_PS_STATE_ALL_ON; /* RF on */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&fw_pwrmode));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
273 (u8 *)(&fw_current_inps));
278 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
280 struct rtl_priv *rtlpriv = rtl_priv(hw);
281 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
282 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
283 bool fw_current_inps = true;
286 if (ppsc->low_power_enable) {
287 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
288 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
291 (u8 *)(&ppsc->fwctrl_psmode));
292 rtlhal->allow_sw_to_change_hwclc = true;
293 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
295 rpwm_val = FW_PS_STATE_RF_OFF; /* RF off */
296 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
297 (u8 *)(&fw_current_inps));
298 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
299 (u8 *)(&ppsc->fwctrl_psmode));
300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
306 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
308 struct rtl_priv *rtlpriv = rtl_priv(hw);
309 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
310 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
314 *((u32 *)(val)) = rtlpci->receive_config;
316 case HW_VAR_RF_STATE:
317 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
319 case HW_VAR_FWLPS_RF_ON:{
320 enum rf_pwrstate rfState;
323 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
325 if (rfState == ERFOFF) {
326 *((bool *)(val)) = true;
328 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
329 val_rcr &= 0x00070000;
331 *((bool *)(val)) = false;
333 *((bool *)(val)) = true;
337 case HW_VAR_FW_PSMODE_STATUS:
338 *((bool *)(val)) = ppsc->fw_current_inpsmode;
340 case HW_VAR_CORRECT_TSF:{
342 u32 *ptsf_low = (u32 *)&tsf;
343 u32 *ptsf_high = ((u32 *)&tsf) + 1;
345 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
346 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
348 *((u64 *)(val)) = tsf;
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
353 "switch case not process %x\n", variable);
358 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
360 struct rtl_priv *rtlpriv = rtl_priv(hw);
361 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
362 u8 count = 0, dlbcn_count = 0;
363 bool b_recover = false;
365 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
366 rtl_write_byte(rtlpriv, REG_CR + 1,
367 (tmp_regcr | BIT(0)));
369 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
370 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
372 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
373 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
374 if (tmp_reg422 & BIT(6))
378 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
379 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
380 (bcnvalid_reg | BIT(0)));
381 _rtl8723be_return_beacon_queue_skb(hw);
383 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
384 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
386 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
389 bcnvalid_reg = rtl_read_byte(rtlpriv,
393 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
395 if (bcnvalid_reg & BIT(0))
396 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
398 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
399 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
402 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
408 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
412 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
413 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
414 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
418 case HW_VAR_ETHER_ADDR:
419 for (idx = 0; idx < ETH_ALEN; idx++)
420 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
422 case HW_VAR_BASIC_RATE:{
423 u16 b_rate_cfg = ((u16 *)val)[0];
425 b_rate_cfg = b_rate_cfg & 0x15f;
427 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
428 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
429 while (b_rate_cfg > 0x1) {
430 b_rate_cfg = (b_rate_cfg >> 1);
433 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
437 for (idx = 0; idx < ETH_ALEN; idx++)
438 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
442 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
443 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
445 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
446 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
449 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
451 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
454 case HW_VAR_SLOT_TIME:{
457 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
458 "HW_VAR_SLOT_TIME %x\n", val[0]);
460 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
462 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
463 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
468 case HW_VAR_ACK_PREAMBLE:{
470 u8 short_preamble = (bool)(*(u8 *)val);
471 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
472 if (short_preamble) {
474 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
477 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
481 case HW_VAR_WPA_CONFIG:
482 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
484 case HW_VAR_AMPDU_MIN_SPACE:{
485 u8 min_spacing_to_set;
488 min_spacing_to_set = *((u8 *)val);
489 if (min_spacing_to_set <= 7) {
492 if (min_spacing_to_set < sec_min_space)
493 min_spacing_to_set = sec_min_space;
495 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
498 *val = min_spacing_to_set;
500 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
501 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
504 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
509 case HW_VAR_SHORTGI_DENSITY:{
512 density_to_set = *((u8 *)val);
513 mac->min_space_cfg |= (density_to_set << 3);
515 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
516 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
519 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
523 case HW_VAR_AMPDU_FACTOR:{
524 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
526 u8 *p_regtoset = NULL;
529 p_regtoset = regtoset_normal;
531 factor_toset = *((u8 *)val);
532 if (factor_toset <= 3) {
533 factor_toset = (1 << (factor_toset + 2));
534 if (factor_toset > 0xf)
537 for (index = 0; index < 4; index++) {
538 if ((p_regtoset[index] & 0xf0) >
541 (p_regtoset[index] & 0x0f) |
544 if ((p_regtoset[index] & 0x0f) > factor_toset)
546 (p_regtoset[index] & 0xf0) |
549 rtl_write_byte(rtlpriv,
550 (REG_AGGLEN_LMT + index),
555 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
556 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
561 case HW_VAR_AC_PARAM:{
562 u8 e_aci = *((u8 *)val);
563 rtl8723_dm_init_edca_turbo(hw);
565 if (rtlpci->acm_method != EACMWAY2_SW)
566 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
570 case HW_VAR_ACM_CTRL:{
571 u8 e_aci = *((u8 *)val);
572 union aci_aifsn *p_aci_aifsn =
573 (union aci_aifsn *)(&(mac->ac[0].aifs));
574 u8 acm = p_aci_aifsn->f.acm;
575 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
578 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
583 acm_ctrl |= ACMHW_BEQEN;
586 acm_ctrl |= ACMHW_VIQEN;
589 acm_ctrl |= ACMHW_VOQEN;
592 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
593 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
600 acm_ctrl &= (~ACMHW_BEQEN);
603 acm_ctrl &= (~ACMHW_VIQEN);
606 acm_ctrl &= (~ACMHW_VOQEN);
609 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
610 "switch case not process\n");
615 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
616 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
618 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
622 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
623 rtlpci->receive_config = ((u32 *)(val))[0];
625 case HW_VAR_RETRY_LIMIT:{
626 u8 retry_limit = ((u8 *)(val))[0];
628 rtl_write_word(rtlpriv, REG_RL,
629 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
630 retry_limit << RETRY_LIMIT_LONG_SHIFT);
633 case HW_VAR_DUAL_TSF_RST:
634 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
636 case HW_VAR_EFUSE_BYTES:
637 rtlefuse->efuse_usedbytes = *((u16 *)val);
639 case HW_VAR_EFUSE_USAGE:
640 rtlefuse->efuse_usedpercentage = *((u8 *)val);
643 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
645 case HW_VAR_SET_RPWM:{
648 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
651 if (rpwm_val & BIT(7)) {
652 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
654 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
655 ((*(u8 *)val) | BIT(7)));
659 case HW_VAR_H2C_FW_PWRMODE:
660 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
662 case HW_VAR_FW_PSMODE_STATUS:
663 ppsc->fw_current_inpsmode = *((bool *)val);
665 case HW_VAR_RESUME_CLK_ON:
666 _rtl8723be_set_fw_ps_rf_on(hw);
668 case HW_VAR_FW_LPS_ACTION:{
669 bool b_enter_fwlps = *((bool *)val);
672 _rtl8723be_fwlps_enter(hw);
674 _rtl8723be_fwlps_leave(hw);
677 case HW_VAR_H2C_FW_JOINBSSRPT:{
678 u8 mstatus = (*(u8 *)val);
680 if (mstatus == RT_MEDIA_CONNECT) {
681 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
682 _rtl8723be_download_rsvd_page(hw);
684 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
687 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
688 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
692 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
694 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
695 (u2btmp | mac->assoc_id));
698 case HW_VAR_CORRECT_TSF:{
699 u8 btype_ibss = ((u8 *)(val))[0];
702 _rtl8723be_stop_tx_beacon(hw);
704 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
706 rtl_write_dword(rtlpriv, REG_TSFTR,
707 (u32) (mac->tsf & 0xffffffff));
708 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
709 (u32) ((mac->tsf >> 32) & 0xffffffff));
711 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
714 _rtl8723be_resume_tx_beacon(hw);
717 case HW_VAR_KEEP_ALIVE:{
720 array[1] = *((u8 *)val);
721 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
725 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
726 "switch case not process %x\n",
732 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
737 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
738 _LLT_OP(_LLT_WRITE_ACCESS);
740 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
743 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
744 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
747 if (count > POLLING_LLT_THRESHOLD) {
748 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
749 "Failed to polling write LLT done at address %d!\n",
759 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
761 struct rtl_priv *rtlpriv = rtl_priv(hw);
770 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
771 (0x27FF0000 | txpktbuf_bndy));
772 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
774 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
775 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
777 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
778 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
779 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
781 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
782 status = _rtl8723be_llt_write(hw, i, i + 1);
787 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
792 for (i = txpktbuf_bndy; i < maxPage; i++) {
793 status = _rtl8723be_llt_write(hw, i, (i + 1));
798 status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
802 rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
803 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
808 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
811 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
812 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
813 struct rtl_led *pled0 = &(pcipriv->ledctl.sw_led0);
815 if (rtlpriv->rtlhal.up_first_time)
818 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
819 rtl8723be_sw_led_on(hw, pled0);
820 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
821 rtl8723be_sw_led_on(hw, pled0);
823 rtl8723be_sw_led_off(hw, pled0);
826 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
828 struct rtl_priv *rtlpriv = rtl_priv(hw);
829 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
830 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
831 unsigned char bytetmp;
832 unsigned short wordtmp;
834 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
836 /*Auto Power Down to CHIP-off State*/
837 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
838 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
840 /* HW Power on sequence */
841 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
842 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
843 RTL8723_NIC_ENABLE_FLOW)) {
844 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
845 "init MAC Fail as power on failure\n");
849 bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
850 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
852 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
853 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
855 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
857 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
860 bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
862 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
865 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
866 if (bytetmp & BIT(0)) {
867 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
868 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
871 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
872 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
873 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
874 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
876 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
878 if (!rtlhal->mac_func_enable) {
879 if (_rtl8723be_llt_table_init(hw) == false)
883 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
884 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
886 /* Enable FW Beamformer Interrupt */
887 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
888 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
890 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
893 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
895 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
896 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
897 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
898 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
900 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
901 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
903 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
904 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
906 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
907 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
908 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
909 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
910 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
911 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
912 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
913 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
914 rtl_write_dword(rtlpriv, REG_HQ_DESA,
915 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
917 rtl_write_dword(rtlpriv, REG_RX_DESA,
918 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
921 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
922 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
924 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
926 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
928 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
930 /* <20130114, Kordan> The following setting is
931 * only for DPDT and Fixed board type.
932 * TODO: A better solution is configure it
933 * according EFUSE during the run-time.
935 rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
936 rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
937 rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
938 rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
939 rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
940 rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
941 rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
942 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
944 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
945 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
947 _rtl8723be_gen_refresh_led_state(hw);
951 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
957 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
958 /* Init value for RRSR. */
959 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
961 /* ARFB table 9 for 11ac 5G 2SS */
962 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
964 /* ARFB table 10 for 11ac 5G 1SS */
965 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
967 /* CF-End setting. */
968 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
970 /* 0x456 = 0x70, sugguested by Zhilin */
971 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
973 /* Set retry limit */
974 rtl_write_word(rtlpriv, REG_RL, 0x0707);
976 /* Set Data / Response auto rate fallack retry count */
977 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
978 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
979 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
980 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
982 rtlpci->reg_bcn_ctrl_val = 0x1d;
983 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
985 /* TBTT prohibit hold time. Suggested by designer TimChen. */
986 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
988 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
990 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
991 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
993 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
995 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
997 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
1000 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1002 u16 read_addr = addr & 0xfffc;
1003 u8 ret = 0, tmp = 0, count = 0;
1005 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1006 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1007 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1009 while (tmp && count < 20) {
1011 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1015 read_addr = REG_DBI_RDATA + addr % 4;
1016 ret = rtl_read_byte(rtlpriv, read_addr);
1022 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1024 u8 tmp = 0, count = 0;
1025 u16 write_addr = 0, remainder = addr % 4;
1027 /* Write DBI 1Byte Data */
1028 write_addr = REG_DBI_WDATA + remainder;
1029 rtl_write_byte(rtlpriv, write_addr, data);
1031 /* Write DBI 2Byte Address & Write Enable */
1032 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1033 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1035 /* Write DBI Write Flag */
1036 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1038 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1040 while (tmp && count < 20) {
1042 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1047 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1050 u8 tmp = 0, count = 0;
1052 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1053 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1055 while (tmp && count < 20) {
1057 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1062 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1067 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1069 u8 tmp = 0, count = 0;
1071 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1072 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1073 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1075 while (tmp && count < 20) {
1077 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1082 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1084 struct rtl_priv *rtlpriv = rtl_priv(hw);
1088 /* <Roger_Notes> Overwrite following ePHY parameter for
1089 * some platform compatibility issue,
1090 * especially when CLKReq is enabled, 2012.11.09.
1092 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1093 if (tmp16 != 0x0663)
1094 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1096 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1097 if (tmp16 != 0x7544)
1098 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1100 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1101 if (tmp16 != 0xB880)
1102 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1104 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1105 if (tmp16 != 0x4000)
1106 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1108 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1109 if (tmp16 != 0x9003)
1110 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1112 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1113 if (tmp16 != 0x0D03)
1114 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1116 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1117 if (tmp16 != 0x4037)
1118 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1120 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1121 if (tmp16 != 0x0070)
1122 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1124 /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1125 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1126 _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
1127 ASPM_L1_LATENCY << 3);
1129 /* Configuration Space offset 0x719 Bit3 is for L1
1130 * BIT4 is for clock request
1132 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1133 _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1136 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1138 struct rtl_priv *rtlpriv = rtl_priv(hw);
1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1142 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1143 rtlpriv->sec.pairwise_enc_algorithm,
1144 rtlpriv->sec.group_enc_algorithm);
1146 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1147 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1148 "not open hw encryption\n");
1152 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1154 if (rtlpriv->sec.use_defaultkey) {
1155 sec_reg_value |= SCR_TXUSEDK;
1156 sec_reg_value |= SCR_RXUSEDK;
1159 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1161 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1163 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1164 "The SECR-value %x\n", sec_reg_value);
1166 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1169 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1175 rtlhal->mac_func_enable = false;
1176 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1177 /* 1. Run LPS WL RFOFF flow */
1178 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1179 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1181 /* 2. 0x1F[7:0] = 0 */
1183 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1184 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1186 rtl8723be_firmware_selfreset(hw);
1189 /* Reset MCU. Suggested by Filen. */
1190 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1191 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1193 /* g. MCUFWDL 0x80[1:0]=0 */
1194 /* reset MCU ready status */
1195 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1197 /* HW card disable configuration. */
1198 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1199 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1201 /* Reset MCU IO Wrapper */
1202 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1203 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1204 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1205 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1207 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1208 /* lock ISO/CLK/Power control register */
1209 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1212 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1216 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1217 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1218 if (!(tmp & BIT(2))) {
1219 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1220 mdelay(100); /* Suggested by DD Justin_tsai. */
1223 /* read reg 0x350 Bit[25] if 1 : RX hang
1224 * read reg 0x350 Bit[24] if 1 : TX hang
1226 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1227 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1228 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1229 "CheckPcieDMAHang8723BE(): true!!\n");
1235 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1239 bool release_mac_rx_pause;
1240 u8 backup_pcie_dma_pause;
1242 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1243 "ResetPcieInterfaceDMA8723BE()\n");
1245 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1246 * released by SD1 Alan.
1247 * 2013.05.07, by tynli.
1250 /* 1. disable register write lock
1251 * write 0x1C bit[1:0] = 2'h0
1252 * write 0xCC bit[2] = 1'b1
1254 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1255 tmp &= ~(BIT(1) | BIT(0));
1256 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1257 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1259 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1261 /* 2. Check and pause TRX DMA
1262 * write 0x284 bit[18] = 1'b1
1263 * write 0x301 = 0xFF
1265 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1267 /* Already pause before the function for another purpose. */
1268 release_mac_rx_pause = false;
1270 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1271 release_mac_rx_pause = true;
1274 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1275 if (backup_pcie_dma_pause != 0xFF)
1276 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1279 /* 3. reset TRX function
1280 * write 0x100 = 0x00
1282 rtl_write_byte(rtlpriv, REG_CR, 0);
1285 /* 4. Reset PCIe DMA
1286 * write 0x003 bit[0] = 0
1288 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1290 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1292 /* 5. Enable PCIe DMA
1293 * write 0x003 bit[0] = 1
1295 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1297 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1300 /* 6. enable TRX function
1301 * write 0x100 = 0xFF
1303 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1305 /* We should init LLT & RQPN and
1306 * prepare Tx/Rx descrptor address later
1307 * because MAC function is reset.
1311 /* 7. Restore PCIe autoload down bit
1312 * write 0xF8 bit[17] = 1'b1
1314 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1316 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1318 /* In MAC power on state, BB and RF maybe in ON state,
1319 * if we release TRx DMA here
1320 * it will cause packets to be started to Tx/Rx,
1321 * so we release Tx/Rx DMA later.
1323 if (!mac_power_on) {
1324 /* 8. release TRX DMA
1325 * write 0x284 bit[18] = 1'b0
1326 * write 0x301 = 0x00
1328 if (release_mac_rx_pause) {
1329 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1330 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1333 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1334 backup_pcie_dma_pause);
1337 /* 9. lock system register
1338 * write 0xCC bit[2] = 1'b0
1340 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1342 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1345 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1347 struct rtl_priv *rtlpriv = rtl_priv(hw);
1348 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1349 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1350 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1351 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1352 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1353 bool rtstatus = true;
1356 unsigned long flags;
1358 /* reenable interrupts to not interfere with other devices */
1359 local_save_flags(flags);
1362 rtlhal->fw_ready = false;
1363 rtlpriv->rtlhal.being_init_adapter = true;
1364 rtlpriv->intf_ops->disable_aspm(hw);
1366 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1367 if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1368 rtlhal->mac_func_enable = true;
1370 rtlhal->mac_func_enable = false;
1371 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1374 if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1375 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1376 rtlhal->mac_func_enable);
1377 rtlhal->mac_func_enable = false;
1379 if (rtlhal->mac_func_enable) {
1380 _rtl8723be_poweroff_adapter(hw);
1381 rtlhal->mac_func_enable = false;
1383 rtstatus = _rtl8723be_init_mac(hw);
1385 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1390 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1391 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1393 err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1395 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1396 "Failed to download FW. Init HW without FW now..\n");
1400 rtlhal->fw_ready = true;
1402 rtlhal->last_hmeboxnum = 0;
1403 rtl8723be_phy_mac_config(hw);
1404 /* because last function modify RCR, so we update
1405 * rcr var here, or TP will unstable for receive_config
1406 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1407 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1409 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1410 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1411 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1413 rtl8723be_phy_bb_config(hw);
1414 rtl8723be_phy_rf_config(hw);
1416 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1417 RF_CHNLBW, RFREG_OFFSET_MASK);
1418 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1419 RF_CHNLBW, RFREG_OFFSET_MASK);
1420 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1421 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1423 _rtl8723be_hw_configure(hw);
1424 rtlhal->mac_func_enable = true;
1425 rtl_cam_reset_all_entry(hw);
1426 rtl8723be_enable_hw_security_config(hw);
1428 ppsc->rfpwr_state = ERFON;
1430 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1431 _rtl8723be_enable_aspm_back_door(hw);
1432 rtlpriv->intf_ops->enable_aspm(hw);
1434 rtl8723be_bt_hw_init(hw);
1436 if (ppsc->rfpwr_state == ERFON) {
1437 rtl8723be_phy_set_rfpath_switch(hw, 1);
1438 /* when use 1ant NIC, iqk will disturb BT music
1439 * root cause is not clear now, is something
1440 * related with 'mdelay' and Reg[0x948]
1442 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1443 !rtlpriv->cfg->ops->get_btc_status()) {
1444 rtl8723be_phy_iq_calibrate(hw, false);
1445 rtlphy->iqk_initialized = true;
1447 rtl8723be_dm_check_txpower_tracking(hw);
1448 rtl8723be_phy_lc_calibrate(hw);
1450 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1452 /* Release Rx DMA. */
1453 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1454 if (tmp_u1b & BIT(2)) {
1455 /* Release Rx DMA if needed */
1456 tmp_u1b &= (~BIT(2));
1457 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1459 /* Release Tx/Rx PCIE DMA. */
1460 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1462 rtl8723be_dm_init(hw);
1464 local_irq_restore(flags);
1465 rtlpriv->rtlhal.being_init_adapter = false;
1469 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1471 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1473 enum version_8723e version = VERSION_UNKNOWN;
1476 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1477 if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1478 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unkown chip version\n");
1480 version = (enum version_8723e)CHIP_8723B;
1482 rtlphy->rf_type = RF_1T1R;
1484 /* treat rtl8723be chip as MP version in default */
1485 version = (enum version_8723e)(version | NORMAL_CHIP);
1487 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1489 version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1491 if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1492 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1494 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1495 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1496 "RF_2T2R" : "RF_1T1R");
1501 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1502 enum nl80211_iftype type)
1504 struct rtl_priv *rtlpriv = rtl_priv(hw);
1505 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1506 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1507 u8 mode = MSR_NOLINK;
1510 case NL80211_IFTYPE_UNSPECIFIED:
1512 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1513 "Set Network type to NO LINK!\n");
1515 case NL80211_IFTYPE_ADHOC:
1516 case NL80211_IFTYPE_MESH_POINT:
1518 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1519 "Set Network type to Ad Hoc!\n");
1521 case NL80211_IFTYPE_STATION:
1523 ledaction = LED_CTL_LINK;
1524 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1525 "Set Network type to STA!\n");
1527 case NL80211_IFTYPE_AP:
1529 ledaction = LED_CTL_LINK;
1530 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1531 "Set Network type to AP!\n");
1534 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1535 "Network type %d not support!\n", type);
1539 /* MSR_INFRA == Link in infrastructure network;
1540 * MSR_ADHOC == Link in ad hoc network;
1541 * Therefore, check link state is necessary.
1543 * MSR_AP == AP mode; link state is not cared here.
1545 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1547 ledaction = LED_CTL_NO_LINK;
1550 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1551 _rtl8723be_stop_tx_beacon(hw);
1552 _rtl8723be_enable_bcn_sub_func(hw);
1553 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1554 _rtl8723be_resume_tx_beacon(hw);
1555 _rtl8723be_disable_bcn_sub_func(hw);
1557 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1558 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1562 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1563 rtlpriv->cfg->ops->led_control(hw, ledaction);
1565 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1567 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1571 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1573 struct rtl_priv *rtlpriv = rtl_priv(hw);
1574 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1575 u32 reg_rcr = rtlpci->receive_config;
1577 if (rtlpriv->psc.rfpwr_state != ERFON)
1581 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1582 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1584 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1585 } else if (!check_bssid) {
1586 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1587 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1588 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1594 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1595 enum nl80211_iftype type)
1597 struct rtl_priv *rtlpriv = rtl_priv(hw);
1599 if (_rtl8723be_set_media_status(hw, type))
1602 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1603 if (type != NL80211_IFTYPE_AP)
1604 rtl8723be_set_check_bssid(hw, true);
1606 rtl8723be_set_check_bssid(hw, false);
1612 /* don't set REG_EDCA_BE_PARAM here
1613 * because mac80211 will send pkt when scan
1615 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1617 struct rtl_priv *rtlpriv = rtl_priv(hw);
1619 rtl8723_dm_init_edca_turbo(hw);
1622 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1627 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1630 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1633 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1638 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1640 struct rtl_priv *rtlpriv = rtl_priv(hw);
1641 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1643 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1644 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1645 rtlpci->irq_enabled = true;
1647 /*enable system interrupt*/
1648 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1651 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1653 struct rtl_priv *rtlpriv = rtl_priv(hw);
1654 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1656 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1657 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1658 rtlpci->irq_enabled = false;
1659 /*synchronize_irq(rtlpci->pdev->irq);*/
1662 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1664 struct rtl_priv *rtlpriv = rtl_priv(hw);
1665 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1666 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1667 enum nl80211_iftype opmode;
1669 mac->link_state = MAC80211_NOLINK;
1670 opmode = NL80211_IFTYPE_UNSPECIFIED;
1671 _rtl8723be_set_media_status(hw, opmode);
1672 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1673 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1674 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1675 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1676 _rtl8723be_poweroff_adapter(hw);
1678 /* after power off we should do iqk again */
1679 rtlpriv->phy.iqk_initialized = false;
1682 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1683 u32 *p_inta, u32 *p_intb)
1685 struct rtl_priv *rtlpriv = rtl_priv(hw);
1686 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1688 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1689 rtl_write_dword(rtlpriv, ISR, *p_inta);
1691 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1692 rtlpci->irq_mask[1];
1693 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1696 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1698 struct rtl_priv *rtlpriv = rtl_priv(hw);
1699 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1700 u16 bcn_interval, atim_window;
1702 bcn_interval = mac->beacon_interval;
1703 atim_window = 2; /*FIX MERGE */
1704 rtl8723be_disable_interrupt(hw);
1705 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1706 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1707 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1708 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1709 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1710 rtl_write_byte(rtlpriv, 0x606, 0x30);
1711 rtl8723be_enable_interrupt(hw);
1714 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1716 struct rtl_priv *rtlpriv = rtl_priv(hw);
1717 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1718 u16 bcn_interval = mac->beacon_interval;
1720 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1721 "beacon_interval:%d\n", bcn_interval);
1722 rtl8723be_disable_interrupt(hw);
1723 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1724 rtl8723be_enable_interrupt(hw);
1727 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1728 u32 add_msr, u32 rm_msr)
1730 struct rtl_priv *rtlpriv = rtl_priv(hw);
1731 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1733 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1734 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1737 rtlpci->irq_mask[0] |= add_msr;
1739 rtlpci->irq_mask[0] &= (~rm_msr);
1740 rtl8723be_disable_interrupt(hw);
1741 rtl8723be_enable_interrupt(hw);
1744 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1757 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1758 struct txpower_info_2g *pw2g,
1759 struct txpower_info_5g *pw5g,
1760 bool autoload_fail, u8 *hwinfo)
1762 struct rtl_priv *rtlpriv = rtl_priv(hw);
1763 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1765 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1766 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1767 (addr + 1), hwinfo[addr + 1]);
1768 if (0xFF == hwinfo[addr + 1]) /*YJ,add,120316*/
1769 autoload_fail = true;
1771 if (autoload_fail) {
1772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1773 "auto load fail : Use Default value!\n");
1774 for (path = 0; path < MAX_RF_PATH; path++) {
1775 /* 2.4G default value */
1776 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1777 pw2g->index_cck_base[path][group] = 0x2D;
1778 pw2g->index_bw40_base[path][group] = 0x2D;
1780 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1782 pw2g->bw20_diff[path][0] = 0x02;
1783 pw2g->ofdm_diff[path][0] = 0x04;
1785 pw2g->bw20_diff[path][cnt] = 0xFE;
1786 pw2g->bw40_diff[path][cnt] = 0xFE;
1787 pw2g->cck_diff[path][cnt] = 0xFE;
1788 pw2g->ofdm_diff[path][cnt] = 0xFE;
1795 for (path = 0; path < MAX_RF_PATH; path++) {
1796 /*2.4G default value*/
1797 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1798 pw2g->index_cck_base[path][group] = hwinfo[addr++];
1799 if (pw2g->index_cck_base[path][group] == 0xFF)
1800 pw2g->index_cck_base[path][group] = 0x2D;
1803 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1804 pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1805 if (pw2g->index_bw40_base[path][group] == 0xFF)
1806 pw2g->index_bw40_base[path][group] = 0x2D;
1808 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1810 pw2g->bw40_diff[path][cnt] = 0;
1811 if (hwinfo[addr] == 0xFF) {
1812 pw2g->bw20_diff[path][cnt] = 0x02;
1814 pw2g->bw20_diff[path][cnt] =
1815 (hwinfo[addr] & 0xf0) >> 4;
1816 /*bit sign number to 8 bit sign number*/
1817 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1818 pw2g->bw20_diff[path][cnt] |=
1822 if (hwinfo[addr] == 0xFF) {
1823 pw2g->ofdm_diff[path][cnt] = 0x04;
1825 pw2g->ofdm_diff[path][cnt] =
1826 (hwinfo[addr] & 0x0f);
1827 /*bit sign number to 8 bit sign number*/
1828 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1829 pw2g->ofdm_diff[path][cnt] |=
1832 pw2g->cck_diff[path][cnt] = 0;
1835 if (hwinfo[addr] == 0xFF) {
1836 pw2g->bw40_diff[path][cnt] = 0xFE;
1838 pw2g->bw40_diff[path][cnt] =
1839 (hwinfo[addr] & 0xf0) >> 4;
1840 if (pw2g->bw40_diff[path][cnt] & BIT(3))
1841 pw2g->bw40_diff[path][cnt] |=
1845 if (hwinfo[addr] == 0xFF) {
1846 pw2g->bw20_diff[path][cnt] = 0xFE;
1848 pw2g->bw20_diff[path][cnt] =
1849 (hwinfo[addr] & 0x0f);
1850 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1851 pw2g->bw20_diff[path][cnt] |=
1856 if (hwinfo[addr] == 0xFF) {
1857 pw2g->ofdm_diff[path][cnt] = 0xFE;
1859 pw2g->ofdm_diff[path][cnt] =
1860 (hwinfo[addr] & 0xf0) >> 4;
1861 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1862 pw2g->ofdm_diff[path][cnt] |=
1866 if (hwinfo[addr] == 0xFF)
1867 pw2g->cck_diff[path][cnt] = 0xFE;
1869 pw2g->cck_diff[path][cnt] =
1870 (hwinfo[addr] & 0x0f);
1871 if (pw2g->cck_diff[path][cnt] & BIT(3))
1872 pw2g->cck_diff[path][cnt] |=
1879 /*5G default value*/
1880 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1881 pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1882 if (pw5g->index_bw40_base[path][group] == 0xFF)
1883 pw5g->index_bw40_base[path][group] = 0xFE;
1886 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1888 pw5g->bw40_diff[path][cnt] = 0;
1890 if (hwinfo[addr] == 0xFF) {
1891 pw5g->bw20_diff[path][cnt] = 0;
1893 pw5g->bw20_diff[path][0] =
1894 (hwinfo[addr] & 0xf0) >> 4;
1895 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1896 pw5g->bw20_diff[path][cnt] |=
1900 if (hwinfo[addr] == 0xFF)
1901 pw5g->ofdm_diff[path][cnt] = 0x04;
1903 pw5g->ofdm_diff[path][0] =
1904 (hwinfo[addr] & 0x0f);
1905 if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1906 pw5g->ofdm_diff[path][cnt] |=
1911 if (hwinfo[addr] == 0xFF) {
1912 pw5g->bw40_diff[path][cnt] = 0xFE;
1914 pw5g->bw40_diff[path][cnt] =
1915 (hwinfo[addr] & 0xf0) >> 4;
1916 if (pw5g->bw40_diff[path][cnt] & BIT(3))
1917 pw5g->bw40_diff[path][cnt] |= 0xF0;
1920 if (hwinfo[addr] == 0xFF) {
1921 pw5g->bw20_diff[path][cnt] = 0xFE;
1923 pw5g->bw20_diff[path][cnt] =
1924 (hwinfo[addr] & 0x0f);
1925 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1926 pw5g->bw20_diff[path][cnt] |= 0xF0;
1932 if (hwinfo[addr] == 0xFF) {
1933 pw5g->ofdm_diff[path][1] = 0xFE;
1934 pw5g->ofdm_diff[path][2] = 0xFE;
1936 pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1937 pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1941 if (hwinfo[addr] == 0xFF)
1942 pw5g->ofdm_diff[path][3] = 0xFE;
1944 pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1947 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1948 if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1949 pw5g->ofdm_diff[path][cnt] = 0xFE;
1950 else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1951 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1956 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1960 struct rtl_priv *rtlpriv = rtl_priv(hw);
1961 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1962 struct txpower_info_2g pw2g;
1963 struct txpower_info_5g pw5g;
1967 _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1970 for (rf_path = 0; rf_path < 2; rf_path++) {
1971 for (i = 0; i < 14; i++) {
1972 index = _rtl8723be_get_chnl_group(i+1);
1974 rtlefuse->txpwrlevel_cck[rf_path][i] =
1975 pw2g.index_cck_base[rf_path][index];
1976 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1977 pw2g.index_bw40_base[rf_path][index];
1979 for (i = 0; i < MAX_TX_COUNT; i++) {
1980 rtlefuse->txpwr_ht20diff[rf_path][i] =
1981 pw2g.bw20_diff[rf_path][i];
1982 rtlefuse->txpwr_ht40diff[rf_path][i] =
1983 pw2g.bw40_diff[rf_path][i];
1984 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1985 pw2g.ofdm_diff[rf_path][i];
1988 for (i = 0; i < 14; i++) {
1989 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1990 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1992 rtlefuse->txpwrlevel_cck[rf_path][i],
1993 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1998 rtlefuse->eeprom_thermalmeter =
1999 hwinfo[EEPROM_THERMAL_METER_88E];
2001 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2003 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
2004 rtlefuse->apk_thermalmeterignore = true;
2005 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2008 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2009 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2010 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
2012 if (!autoload_fail) {
2013 rtlefuse->eeprom_regulatory =
2014 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2015 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2016 rtlefuse->eeprom_regulatory = 0;
2018 rtlefuse->eeprom_regulatory = 0;
2020 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2021 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2024 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2027 struct rtl_priv *rtlpriv = rtl_priv(hw);
2028 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2029 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2031 u8 hwinfo[HWSET_MAX_SIZE];
2033 bool is_toshiba_smid1 = false;
2034 bool is_toshiba_smid2 = false;
2035 bool is_samsung_smid = false;
2036 bool is_lenovo_smid = false;
2037 u16 toshiba_smid1[] = {
2038 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2039 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2040 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2041 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2043 u16 toshiba_smid2[] = {
2044 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2045 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2047 u16 samsung_smid[] = {
2048 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2049 0x8193, 0x9191, 0x9192, 0x9193
2051 u16 lenovo_smid[] = {
2052 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2056 /* needs to be added */
2059 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2060 rtl_efuse_shadow_map_update(hw);
2062 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2064 } else if (rtlefuse->epromtype == EEPROM_93C46) {
2065 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2066 "RTL819X Not boot from eeprom, check it !!");
2068 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
2069 hwinfo, HWSET_MAX_SIZE);
2071 eeprom_id = *((u16 *)&hwinfo[0]);
2072 if (eeprom_id != RTL8723BE_EEPROM_ID) {
2073 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2074 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
2075 rtlefuse->autoload_failflag = true;
2077 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2078 rtlefuse->autoload_failflag = false;
2081 if (rtlefuse->autoload_failflag)
2084 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
2085 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
2086 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
2087 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
2088 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2089 "EEPROMId = 0x%4x\n", eeprom_id);
2090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
2092 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2093 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2094 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2096 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2097 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2099 for (i = 0; i < 6; i += 2) {
2100 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2101 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2103 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "dev_addr: %pM\n",
2104 rtlefuse->dev_addr);
2107 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2108 if (rtlefuse->crystalcap == 0xFF)
2109 rtlefuse->crystalcap = 0x20;
2111 _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2114 rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2115 rtlefuse->autoload_failflag,
2118 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
2119 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
2120 rtlefuse->txpwr_fromeprom = true;
2121 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
2123 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2124 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2126 /* set channel plan from efuse */
2127 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2129 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2130 /* Does this one have a Toshiba SMID from group 1? */
2131 for (i = 0; i < sizeof(toshiba_smid1) / sizeof(u16); i++) {
2132 if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2133 is_toshiba_smid1 = true;
2137 /* Does this one have a Toshiba SMID from group 2? */
2138 for (i = 0; i < sizeof(toshiba_smid2) / sizeof(u16); i++) {
2139 if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2140 is_toshiba_smid2 = true;
2144 /* Does this one have a Samsung SMID? */
2145 for (i = 0; i < sizeof(samsung_smid) / sizeof(u16); i++) {
2146 if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2147 is_samsung_smid = true;
2151 /* Does this one have a Lenovo SMID? */
2152 for (i = 0; i < sizeof(lenovo_smid) / sizeof(u16); i++) {
2153 if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2154 is_lenovo_smid = true;
2158 switch (rtlefuse->eeprom_oemid) {
2159 case EEPROM_CID_DEFAULT:
2160 if (rtlefuse->eeprom_did == 0x8176) {
2161 if (rtlefuse->eeprom_svid == 0x10EC &&
2163 rtlhal->oem_id = RT_CID_TOSHIBA;
2164 } else if (rtlefuse->eeprom_svid == 0x1025) {
2165 rtlhal->oem_id = RT_CID_819X_ACER;
2166 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2168 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2169 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2171 rtlhal->oem_id = RT_CID_819X_LENOVO;
2172 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2173 rtlefuse->eeprom_smid == 0x8197) ||
2174 (rtlefuse->eeprom_svid == 0x10EC &&
2175 rtlefuse->eeprom_smid == 0x9196)) {
2176 rtlhal->oem_id = RT_CID_819X_CLEVO;
2177 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2178 rtlefuse->eeprom_smid == 0x8194) ||
2179 (rtlefuse->eeprom_svid == 0x1028 &&
2180 rtlefuse->eeprom_smid == 0x8198) ||
2181 (rtlefuse->eeprom_svid == 0x1028 &&
2182 rtlefuse->eeprom_smid == 0x9197) ||
2183 (rtlefuse->eeprom_svid == 0x1028 &&
2184 rtlefuse->eeprom_smid == 0x9198)) {
2185 rtlhal->oem_id = RT_CID_819X_DELL;
2186 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2187 rtlefuse->eeprom_smid == 0x1629)) {
2188 rtlhal->oem_id = RT_CID_819X_HP;
2189 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2190 rtlefuse->eeprom_smid == 0x2315)) {
2191 rtlhal->oem_id = RT_CID_819X_QMI;
2192 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2193 rtlefuse->eeprom_smid == 0x8203)) {
2194 rtlhal->oem_id = RT_CID_819X_PRONETS;
2195 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2196 rtlefuse->eeprom_smid == 0x84B5)) {
2197 rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2199 rtlhal->oem_id = RT_CID_DEFAULT;
2201 } else if (rtlefuse->eeprom_did == 0x8178) {
2202 if (rtlefuse->eeprom_svid == 0x10EC &&
2204 rtlhal->oem_id = RT_CID_TOSHIBA;
2205 else if (rtlefuse->eeprom_svid == 0x1025)
2206 rtlhal->oem_id = RT_CID_819X_ACER;
2207 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2208 rtlefuse->eeprom_smid == 0x8186))
2209 rtlhal->oem_id = RT_CID_819X_PRONETS;
2210 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2211 rtlefuse->eeprom_smid == 0x84B6))
2213 RT_CID_819X_EDIMAX_ASUS;
2215 rtlhal->oem_id = RT_CID_DEFAULT;
2217 rtlhal->oem_id = RT_CID_DEFAULT;
2220 case EEPROM_CID_TOSHIBA:
2221 rtlhal->oem_id = RT_CID_TOSHIBA;
2223 case EEPROM_CID_CCX:
2224 rtlhal->oem_id = RT_CID_CCX;
2226 case EEPROM_CID_QMI:
2227 rtlhal->oem_id = RT_CID_819X_QMI;
2229 case EEPROM_CID_WHQL:
2232 rtlhal->oem_id = RT_CID_DEFAULT;
2238 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2240 struct rtl_priv *rtlpriv = rtl_priv(hw);
2241 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2242 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2244 pcipriv->ledctl.led_opendrain = true;
2245 switch (rtlhal->oem_id) {
2246 case RT_CID_819X_HP:
2247 pcipriv->ledctl.led_opendrain = true;
2249 case RT_CID_819X_LENOVO:
2250 case RT_CID_DEFAULT:
2251 case RT_CID_TOSHIBA:
2253 case RT_CID_819X_ACER:
2258 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2259 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2262 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2264 struct rtl_priv *rtlpriv = rtl_priv(hw);
2265 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2266 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2267 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2270 rtlhal->version = _rtl8723be_read_chip_version(hw);
2271 if (get_rf_type(rtlphy) == RF_1T1R)
2272 rtlpriv->dm.rfpath_rxenable[0] = true;
2274 rtlpriv->dm.rfpath_rxenable[0] =
2275 rtlpriv->dm.rfpath_rxenable[1] = true;
2276 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2278 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2279 if (tmp_u1b & BIT(4)) {
2280 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2281 rtlefuse->epromtype = EEPROM_93C46;
2283 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2284 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2286 if (tmp_u1b & BIT(5)) {
2287 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2288 rtlefuse->autoload_failflag = false;
2289 _rtl8723be_read_adapter_info(hw, false);
2291 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2293 _rtl8723be_hal_customized_behavior(hw);
2296 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2300 switch (rate_index) {
2301 case RATR_INX_WIRELESS_NGB:
2304 case RATR_INX_WIRELESS_N:
2305 case RATR_INX_WIRELESS_NG:
2308 case RATR_INX_WIRELESS_NB:
2311 case RATR_INX_WIRELESS_GB:
2314 case RATR_INX_WIRELESS_G:
2317 case RATR_INX_WIRELESS_B:
2327 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2328 struct ieee80211_sta *sta,
2331 struct rtl_priv *rtlpriv = rtl_priv(hw);
2332 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2333 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2334 struct rtl_sta_info *sta_entry = NULL;
2337 u8 curtxbw_40mhz = (sta->ht_cap.cap &
2338 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2339 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2341 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2343 enum wireless_mode wirelessmode = 0;
2344 bool shortgi = false;
2348 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2349 wirelessmode = sta_entry->wireless_mode;
2350 if (mac->opmode == NL80211_IFTYPE_STATION ||
2351 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2352 curtxbw_40mhz = mac->bw_40;
2353 else if (mac->opmode == NL80211_IFTYPE_AP ||
2354 mac->opmode == NL80211_IFTYPE_ADHOC)
2355 macid = sta->aid + 1;
2357 ratr_bitmap = sta->supp_rates[0];
2359 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2360 ratr_bitmap = 0xfff;
2362 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2363 sta->ht_cap.mcs.rx_mask[0] << 12);
2364 switch (wirelessmode) {
2365 case WIRELESS_MODE_B:
2366 ratr_index = RATR_INX_WIRELESS_B;
2367 if (ratr_bitmap & 0x0000000c)
2368 ratr_bitmap &= 0x0000000d;
2370 ratr_bitmap &= 0x0000000f;
2372 case WIRELESS_MODE_G:
2373 ratr_index = RATR_INX_WIRELESS_GB;
2375 if (rssi_level == 1)
2376 ratr_bitmap &= 0x00000f00;
2377 else if (rssi_level == 2)
2378 ratr_bitmap &= 0x00000ff0;
2380 ratr_bitmap &= 0x00000ff5;
2382 case WIRELESS_MODE_N_24G:
2383 case WIRELESS_MODE_N_5G:
2384 ratr_index = RATR_INX_WIRELESS_NGB;
2385 if (rtlphy->rf_type == RF_1T1R) {
2386 if (curtxbw_40mhz) {
2387 if (rssi_level == 1)
2388 ratr_bitmap &= 0x000f0000;
2389 else if (rssi_level == 2)
2390 ratr_bitmap &= 0x000ff000;
2392 ratr_bitmap &= 0x000ff015;
2394 if (rssi_level == 1)
2395 ratr_bitmap &= 0x000f0000;
2396 else if (rssi_level == 2)
2397 ratr_bitmap &= 0x000ff000;
2399 ratr_bitmap &= 0x000ff005;
2402 if (curtxbw_40mhz) {
2403 if (rssi_level == 1)
2404 ratr_bitmap &= 0x0f8f0000;
2405 else if (rssi_level == 2)
2406 ratr_bitmap &= 0x0f8ff000;
2408 ratr_bitmap &= 0x0f8ff015;
2410 if (rssi_level == 1)
2411 ratr_bitmap &= 0x0f8f0000;
2412 else if (rssi_level == 2)
2413 ratr_bitmap &= 0x0f8ff000;
2415 ratr_bitmap &= 0x0f8ff005;
2418 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2419 (!curtxbw_40mhz && curshortgi_20mhz)) {
2422 else if (macid == 1)
2427 ratr_index = RATR_INX_WIRELESS_NGB;
2429 if (rtlphy->rf_type == RF_1T2R)
2430 ratr_bitmap &= 0x000ff0ff;
2432 ratr_bitmap &= 0x0f0ff0ff;
2436 sta_entry->ratr_index = ratr_index;
2438 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2439 "ratr_bitmap :%x\n", ratr_bitmap);
2440 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2442 rate_mask[0] = macid;
2443 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2444 (shortgi ? 0x80 : 0x00);
2445 rate_mask[2] = curtxbw_40mhz;
2447 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2448 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2449 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2450 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2452 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2453 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2454 ratr_index, ratr_bitmap,
2455 rate_mask[0], rate_mask[1],
2456 rate_mask[2], rate_mask[3],
2457 rate_mask[4], rate_mask[5],
2459 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2460 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2463 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2464 struct ieee80211_sta *sta,
2467 struct rtl_priv *rtlpriv = rtl_priv(hw);
2468 if (rtlpriv->dm.useramask)
2469 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2472 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2474 struct rtl_priv *rtlpriv = rtl_priv(hw);
2475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2478 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2479 if (!mac->ht_enable)
2480 sifs_timer = 0x0a0a;
2482 sifs_timer = 0x0e0e;
2483 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2486 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2488 struct rtl_priv *rtlpriv = rtl_priv(hw);
2489 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2490 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2491 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2493 bool b_actuallyset = false;
2495 if (rtlpriv->rtlhal.being_init_adapter)
2498 if (ppsc->swrf_processing)
2501 spin_lock(&rtlpriv->locks.rf_ps_lock);
2502 if (ppsc->rfchange_inprogress) {
2503 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2506 ppsc->rfchange_inprogress = true;
2507 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2510 cur_rfstate = ppsc->rfpwr_state;
2512 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2513 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2515 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2517 if (rtlphy->polarity_ctl)
2518 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2520 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2522 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2523 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2524 "GPIOChangeRF - HW Radio ON, RF ON\n");
2526 e_rfpowerstate_toset = ERFON;
2527 ppsc->hwradiooff = false;
2528 b_actuallyset = true;
2529 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2530 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2531 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2533 e_rfpowerstate_toset = ERFOFF;
2534 ppsc->hwradiooff = true;
2535 b_actuallyset = true;
2538 if (b_actuallyset) {
2539 spin_lock(&rtlpriv->locks.rf_ps_lock);
2540 ppsc->rfchange_inprogress = false;
2541 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2543 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2544 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2546 spin_lock(&rtlpriv->locks.rf_ps_lock);
2547 ppsc->rfchange_inprogress = false;
2548 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2552 return !ppsc->hwradiooff;
2556 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2557 u8 *p_macaddr, bool is_group, u8 enc_algo,
2558 bool is_wepkey, bool clear_all)
2560 struct rtl_priv *rtlpriv = rtl_priv(hw);
2561 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2562 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2563 u8 *macaddr = p_macaddr;
2565 bool is_pairwise = false;
2567 static u8 cam_const_addr[4][6] = {
2568 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2569 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2570 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2571 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2573 static u8 cam_const_broad[] = {
2574 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2580 u8 clear_number = 5;
2582 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2584 for (idx = 0; idx < clear_number; idx++) {
2585 rtl_cam_mark_invalid(hw, cam_offset + idx);
2586 rtl_cam_empty_entry(hw, cam_offset + idx);
2589 memset(rtlpriv->sec.key_buf[idx], 0,
2591 rtlpriv->sec.key_len[idx] = 0;
2597 case WEP40_ENCRYPTION:
2598 enc_algo = CAM_WEP40;
2600 case WEP104_ENCRYPTION:
2601 enc_algo = CAM_WEP104;
2603 case TKIP_ENCRYPTION:
2604 enc_algo = CAM_TKIP;
2606 case AESCCMP_ENCRYPTION:
2610 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2611 "switch case not process\n");
2612 enc_algo = CAM_TKIP;
2616 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2617 macaddr = cam_const_addr[key_index];
2618 entry_id = key_index;
2621 macaddr = cam_const_broad;
2622 entry_id = key_index;
2624 if (mac->opmode == NL80211_IFTYPE_AP) {
2625 entry_id = rtl_cam_get_free_entry(hw,
2627 if (entry_id >= TOTAL_CAM_ENTRY) {
2628 RT_TRACE(rtlpriv, COMP_SEC,
2630 "Can not find free hw security cam entry\n");
2634 entry_id = CAM_PAIRWISE_KEY_POSITION;
2637 key_index = PAIRWISE_KEYIDX;
2642 if (rtlpriv->sec.key_len[key_index] == 0) {
2643 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2644 "delete one entry, entry_id is %d\n",
2646 if (mac->opmode == NL80211_IFTYPE_AP)
2647 rtl_cam_del_entry(hw, p_macaddr);
2648 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2650 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2653 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2654 "set Pairwiase key\n");
2656 rtl_cam_add_one_entry(hw, macaddr, key_index,
2658 CAM_CONFIG_NO_USEDK,
2659 rtlpriv->sec.key_buf[key_index]);
2661 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2664 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2665 rtl_cam_add_one_entry(hw,
2668 CAM_PAIRWISE_KEY_POSITION,
2670 CAM_CONFIG_NO_USEDK,
2671 rtlpriv->sec.key_buf
2675 rtl_cam_add_one_entry(hw, macaddr, key_index,
2677 CAM_CONFIG_NO_USEDK,
2678 rtlpriv->sec.key_buf[entry_id]);
2684 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2685 bool auto_load_fail, u8 *hwinfo)
2687 struct rtl_priv *rtlpriv = rtl_priv(hw);
2688 struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2692 if (!auto_load_fail) {
2693 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2694 if (tmpu_32 & BIT(18))
2695 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2697 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2698 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2699 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2700 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2702 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2703 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2704 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2707 /* override ant_num / ant_path */
2708 if (mod_params->ant_sel)
2709 rtlpriv->btcoexist.btc_info.ant_num =
2710 (mod_params->ant_sel == 1 ? ANT_X2 : ANT_X1);
2713 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2715 struct rtl_priv *rtlpriv = rtl_priv(hw);
2717 /* 0:Low, 1:High, 2:From Efuse. */
2718 rtlpriv->btcoexist.reg_bt_iso = 2;
2719 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2720 rtlpriv->btcoexist.reg_bt_sco = 3;
2721 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2722 rtlpriv->btcoexist.reg_bt_sco = 0;
2725 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2727 struct rtl_priv *rtlpriv = rtl_priv(hw);
2729 if (rtlpriv->cfg->ops->get_btc_status())
2730 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2734 void rtl8723be_suspend(struct ieee80211_hw *hw)
2738 void rtl8723be_resume(struct ieee80211_hw *hw)